Patent application number | Description | Published |
20130136980 | ELECTROCHEMICAL CELL, ELECTRODE COMPOSITION THEREOF AND METHOD FOR MAKING SAME - A composition of the positive electrode comprises at least one electroactive metal, at least one iodide of at least one transition metal, a first alkali metal halide, and an electrolyte salt having a melting point of less than about 300° C. The at least one electroactive metal is selected from the group consisting of titanium, vanadium, niobium, nickel, cobalt, chromium, manganese, silver, antimony, cadmium, tin, lead, iron, and zinc. An electrochemical cell and a method for making an electrochemical cell are also presented. | 05-30-2013 |
20130157140 | METHODS OF MAKING AND USING ELECTRODE COMPOSITIONS AND ARTICLES - A positive electrode composition is described, containing granules of at least one electroactive metal, at least one alkali metal halide and carbon black. An energy storage device and an uninterruptable power supply device are also described. Related methods for the preparation of a positive electrode and an energy storage device are also disclosed | 06-20-2013 |
20140038038 | ELECTROCHEMICAL CELLS AND RELATED METHODS - An electrochemical cell is presented. The electrochemical cell includes an elongated ion-conducting separator defining at least a portion of a first compartment; a positive electrode composition disposed in the first compartment, the positive electrode composition comprising at least one electroactive metal, at least one alkali metal halide, and at least one electrolyte. A positive current collector is further disposed in the first compartment such that a portion of the positive current collector extends into the positive electrode composition, and a primary dimension of the extended portion of the positive current collector is less than about 20% of a primary dimension of the first compartment. A related method for the preparation of an electrochemical cell is also presented. | 02-06-2014 |
20140062412 | METHOD OF CHARGING AN ELECTROCHEMICAL CELL - A method of pulse charging a secondary electrochemical storage cell is provided. The secondary cell includes a negative electrode comprising an alkaline metal; a positive electrode comprising at least one transition metal halide; a molten salt electrolyte comprising alkaline metal haloaluminate; and a solid electrolyte partitioning the positive electrode from the negative electrode, such that a first surface of the solid electrolyte is in contact with the positive electrode, and a second surface of the solid electrolyte is in contact with the negative electrode. The method of charging includes polarizing the cell by applying a polarizing voltage greater than about 0.1 V above the cell's rest potential for a first predetermined period of time; depolarizing the cell for a second predetermined period of time; and repeating the polarizing and depolarizing steps until a charging end-point is reached. | 03-06-2014 |
20140349159 | ELECTROCHEMICAL CELLS AND RELATED DEVICES - An electrochemical cell is presented. The electrochemical cell includes an ion-conducting separator having a first surface that defines at least a portion of a first compartment and a second surface that defines at least a portion of a second compartment, and a positive electrode composition disposed in the first compartment, the positive electrode composition comprising an electroactive metal, an alkali metal halide, and an electrolyte. The electroactive metal includes metal flakes of an average aspect ratio greater than about 5. An energy storage battery including a plurality of electrochemical cells is also presented. | 11-27-2014 |
Patent application number | Description | Published |
20080204046 | Capacitance Measurement Apparatus and Method - A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage. | 08-28-2008 |
20100001889 | Current-Time Digital-to-Analog Converter - A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2 | 01-07-2010 |
20100017490 | Serial Communications Device with Dynamic Allocation of Acceptance Masks Using Serial Implementation - A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal. | 01-21-2010 |
20110175659 | Generating a time delayed event - A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times there between. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage. | 07-21-2011 |
20110178767 | MEASURING A TIME PERIOD - A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage. | 07-21-2011 |
20120171706 | GLUCOSE MEASUREMENT USING A CURRENT SOURCE - A blood glucose meter comprises a blood sample test strip, a constant current source, a precision timer, a digital processor and memory, and an analog measurement circuit, e.g., voltage comparator, analog-to-digital converter (ADC), etc., that eliminates the complex analog front end and other related circuits of present technology glucose meters. When a blood sample is applied to the blood sample test strip a charge, Q, develops from the reaction between an enzyme in the test strip and the blood sample. The constant current source injects a constant current value, I, into the charge, Q, on the blood sample test strip over a precisely measured time determined by when the excess charge, Q, has been removed from the test strip. The amount of charge, Q, is determined by Q=I*T, the charge, Q, is then converted into a blood glucose level for display. | 07-05-2012 |
20120271580 | TOUCH SENSE DETERMINED BY CHARACTERIZING IMPEDANCE CHANGES IN A TRANSMISSION LINE - A touch panel or screen has a serpentine transmission line fabricated on a substrate, e.g., printed circuit board, LCD, plasma or LED screen, etc., and has a constant impedance. Touches to the touch panel will cause changes of impedance of the transmission line at the locations of the touches. Time domain reflectometry (TDR) is used for determining the locations of the changes of impedance of the transmission line by accurately measuring the return pulse times at the source of a plurality of pulses, and then converting the return pulse times to X-Y coordinates of the touch panel or screen. | 10-25-2012 |
20130121372 | HIGH RESOLUTION TEMPERATURE MEASUREMENT - Temperature is determined by measuring the time it takes to charge a capacitor with a resistive temperature sensor. A clock, time counter, a voltage comparator and voltage reference are used in determining a course time measurement. The time measurement resolution is enhanced with the addition of a constant current source charging another timing capacitor within a single clock pulse time to provide a fine time measurement. | 05-16-2013 |
20130241626 | INPUT CAPTURE PERIPHERAL WITH GATING LOGIC - A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated. | 09-19-2013 |
Patent application number | Description | Published |
20100002488 | F-SRAM Margin Screen - A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage. | 01-07-2010 |
20120297165 | Electronic Device and Method for Data Processing Using Virtual Register Mode - The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit. | 11-22-2012 |
20140103728 | SINGLE INDUCTOR ENERGY MANAGEMENT AND HARVESTING INTERFACE SYSTEM AND METHOD - A system comprising an ambient energy source, a power supply, and a power storage device. The ambient energy source is coupled to a first terminal end of an inductor. The power supply is also coupled to the first terminal end of the inductor. The power storage device is coupled to a second terminal end of the inductor. The ambient energy source provides power through the inductor in a first direction to the power storage device. The power storage device provides power through the inductor to the power supply in a second direction opposite the first direction. | 04-17-2014 |
20140218090 | NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode. | 08-07-2014 |
20140218091 | POSITIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-07-2014 |
20140232439 | NEGATIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-21-2014 |
20140232440 | POSITIVE EDGE RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-21-2014 |
20140232441 | POSITIVE EDGE PRESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-21-2014 |
20140232442 | NEGATIVE EDGE RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-21-2014 |
20140232443 | NEGATIVE EDGE PRESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-21-2014 |
20140328115 | POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 11-06-2014 |
20140347113 | POSITIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 11-27-2014 |
20140347114 | NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode. | 11-27-2014 |
20150042390 | DUAL-PORT POSITIVE LEVEL SENSITIVE DATA RETENTION LATCH - In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 02-12-2015 |
20150048872 | DUAL-PORT POSITIVE LEVEL SENSITIVE RESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 02-19-2015 |
20150309801 | Electronic Device and Method for Data Processing Using Virtual Register Mode - The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit. | 10-29-2015 |
Patent application number | Description | Published |
20080258790 | Systems and Devices for Sub-threshold Data Capture - Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide differential jam latches. Such differential jam latches include a data input, a latch input, and an output. Further, such differential jam latches include a PMOS stage and an NMOS stage. The PMOS stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the latch input. The gate of the third PMOS transistor is electrically coupled to the data input, and the gate of the fourth PMOS transistor is electrically coupled to an inverted version of the data input. The NMOS stage includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to the latch input. The gate of the third NMOS transistor is electrically coupled to the data input, and the gate of the fourth NMOS transistor is electrically coupled to an inverted version of the data input. In addition, the jam latches include two inverters. The PMOS stage is electrically coupled to a first node and a second node, and the NMOS stage is electrically coupled to the first node and the second node. The first inverter drives an inverted version of the signal on the first node to the second node, and the second inverter drives an inverted version of the signal on the second node to the first node. | 10-23-2008 |
20080259681 | Systems and Devices for Implementing Sub-Threshold Memory Devices - Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input. The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor. In addition, the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor by the first inverter, and the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor by the second inverter. | 10-23-2008 |
20090015413 | WIRELESSLY TRANSMITTING BIOLOGICAL PARAMETERS - A radio frequency identification (RFID) tag is disclosed that comprises a transceiver and a component coupled to the transceiver. The component is adapted to collect at least one biological parameter. The transceiver is adapted to wirelessly receive power from a base device, where the power received from the base device is used to power the component. | 01-15-2009 |
20100332929 | SCAN TESTABLE REGISTER FILE - Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches. | 12-30-2010 |
20150054544 | DUAL-PORT POSITIVE LEVEL SENSITIVE PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 02-26-2015 |
20150054545 | DUAL-PORT POSITIVE LEVEL SENSITIVE RESET PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode. | 02-26-2015 |
20150054557 | DUAL-PORT NEGATIVE LEVEL SENSITIVE PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 02-26-2015 |
20150070061 | DUAL-PORT NEGATIVE LEVEL SENSITIVE RESET PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 03-12-2015 |
Patent application number | Description | Published |
20100296329 | Differential Plate Line Screen Test for Ferroelectric Latch Circuits - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability. | 11-25-2010 |
20120168837 | Ferroelectric Memory Electrical Contact - A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor. | 07-05-2012 |
20120170348 | Ferroelectric Memory Write-Back - A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time. | 07-05-2012 |
20120170349 | Ferroelectric Memory with Shunt Device - A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle. | 07-05-2012 |
20120170350 | METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY - An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device. | 07-05-2012 |
20120170351 | METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY - An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage). | 07-05-2012 |
20120195096 | DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability. | 08-02-2012 |
20130021833 | DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability. | 01-24-2013 |
20130062733 | Integrated Circuit with Integrated Decoupling Capacitors - Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown. | 03-14-2013 |
20130313679 | INTEGRATED CIRCUIT WITH INTEGRATED DECOUPLING CAPACITORS - Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown. | 11-28-2013 |
20140075087 | Priority Based Backup in Nonvolatile Logic Arrays - A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration. | 03-13-2014 |
20140075088 | Processing Device With Nonvolatile Logic Array Backup - A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements. | 03-13-2014 |
20140075089 | Nonvolatile Logic Array With Retention Flip Flops To Reduce Switching Power During Wakeup - A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device. | 03-13-2014 |
20140075090 | Configuration Bit Sequencing Control of Nonvolatile Domain and Array Wakeup and Backup - A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store | 03-13-2014 |
20140075091 | Processing Device With Restricted Power Domain Wakeup Restore From Nonvolatile Logic Array - A processing device handles two or more operating threads. A non-volatile logic controller stores first program data from a first program in a first set of non-volatile logic element arrays and second program data from a second program in a second set of non-volatile logic element arrays. The first program and the second program can correspond to distinct executing threads, and the storage can be completed in response to receiving a stimulus regarding an interrupt for the computing device apparatus or in response to a power supply quality problem for the computing device apparatus. When the device needs to switch between processing threads, the non-volatile logic controller restores the first program data or the second program data from the non-volatile logic element arrays in response to receiving a stimulus regarding whether the first program or the second program is to be executed by the computing device apparatus. | 03-13-2014 |
20140075174 | Boot State Restore from Nonvolatile Bitcell Array - A processing device using a plurality of volatile storage elements to execute a boot process for and stores in a plurality of non-volatile logic element arrays a boot state representing a state of the processing device after a given amount of the boot process is completed. When it is determined that the processing device needs to restart from a boot state, energy can be saved by restoring the machine state at that boot state instead of re-booting. The stored boot state will not change, and given the nature of certain non-volatile storage elements, the data read from the NVL storage elements needs to be re-written to the elements after read out. Accordingly, a round-trip data restoration operation is executed that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations. | 03-13-2014 |
20140075175 | Control of Dedicated Non-Volatile Arrays for Specific Function Availability - A device's configuration is controlled through control of its pre-boot process. Protected non-volatile logic element arrays store a machine state configuration of a processing device configured to backup data from volatile storage elements in a plurality of non-volatile logic element arrays. The machine state configuration is read in response to the processing device's entering a pre-boot process. The processing device's configuration is then set to the machine state configuration. This setting of the device configuration can be done by receiving instructions from the protected non-volatile logic element arrays to direct an order in which data for individual device functions are restored from non-volatile logic element arrays in response to the processing device's entering a wakeup or recovery mode. In one approach, the instructions arrange configuration bits that direct operation of a non-volatile logic controller during the wakeup or recovery mode to control the order of data restoration. | 03-13-2014 |
20140075218 | Nonvolatile Logic Array And Power Domain Segmentation In Processing Device - A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device. | 03-13-2014 |
20140075225 | Non-Volatile Array Wakeup and Backup Sequencing Control - Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof. | 03-13-2014 |
20140075232 | Nonvolatile Logic Array Based Computing Over Inconsistent Power Supply - Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply. | 03-13-2014 |
20140075233 | Customizable Backup And Restore From Nonvolatile Logic Array - Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics. | 03-13-2014 |
20140210511 | Error Detection in Nonvolatile Logic Arrays Using Parity - A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected. | 07-31-2014 |
20140210535 | Signal Level Conversion in Nonvolatile Bitcell Array - A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage. | 07-31-2014 |
20140211532 | Four Capacitor Nonvolatile Bit Cell - A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed. | 07-31-2014 |
20140211533 | Two Capacitor Self-Referencing Nonvolatile Bitcell - A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor. | 07-31-2014 |
20140211572 | Nonvolatile Logic Array with Built-In Test Result Signal - A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller. | 07-31-2014 |
20140211576 | Nonvolatile Logic Array with Built-In Test Drivers - A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits. | 07-31-2014 |
20150054556 | DUAL-PORT NEGATIVE LEVEL SENSITIVE RESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 02-26-2015 |
20150061739 | DUAL-PORT NEGATIVE LEVEL SENSITIVE DATA RETENTION LATCH - In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 03-05-2015 |
20150089293 | Non-Volatile Logic Based Processing Device - A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain. | 03-26-2015 |