Patent application number | Description | Published |
20100137026 | MOBILE TERMINAL AND METHOD OF CONTROLLING DISPLAY THEREOF - A mobile terminal includes a projector module configured to project an image onto an external surface to display the image on the external surface and a controller configured to adjust at least one of an area or a position of the displayed image. | 06-03-2010 |
20100137027 | CONTROL OF INPUT/OUTPUT THROUGH TOUCH - A mobile terminal including a speaker configured to output sound data, a microphone configured to receive voice data, a sensing unit configured to sense a touching operation of at least one of 1) the speaker or the microphone and 2) a neighborhood area of the speaker or the microphone, and a controller configured to control a volume of the speaker or the microphone based on the sensed touching operation of said at least one of 1) the speaker or the microphone and 2) the neighborhood area of the speaker or the microphone. | 06-03-2010 |
20100289740 | TOUCHLESS CONTROL OF AN ELECTRONIC DEVICE - A method of controlling an electronic device includes detecting an object at a distance from the electronic device, displaying a symbol at a fixed location on a screen of the electronic device in response to detection of the object, and performing an operation corresponding to the symbol based on a state of the object detected after display of the symbol on the screen. | 11-18-2010 |
20110039603 | MOBILE TERMINAL AND DISPLAY CONTROLLING METHOD THEREOF - A mobile terminal including a display unit; a first power source configured to supply a first power; a first control unit configured to control operations of the mobile terminal; and an attaching mechanism configured to receive a detachable e-paper kit including e-paper, a second power source configured to supply a second power, and a second control unit configured to control operations of the e-paper kit. Further, when the e-paper kit is attached to the mobile terminal via the attaching mechanism, the first control unit is configured to control the display unit to display first information via the first power supplied by the first power source, and the second control unit of the e-paper kit is configured to control the e-paper to display second information via the second power supplied by the second power source. | 02-17-2011 |
20110039605 | MOBILE TERMINAL AND POWER SOURCE CONTROLLING METHOD THEREOF - A mobile terminal and power source controlling method thereof are disclosed, by which inter-power source power forwarding operations among a plurality of power sources can be efficiently performed to correspond to a power forwarding command operation inputted by a user. The present invention includes a power supply unit including a first power source and a second power source, an output unit displaying first power source state information of the first power source and second power source state information of the second power source, a user input unit receiving an input of a power forwarding command action for forwarding a power from one of the first and second power sources to the other, and a control unit controlling the power supply unit to forward the power from one of the first and second power sources to the other to correspond to the inputted power forwarding command action, the control unit controlling the output unit to display the first and second power source state informations according to the power forwarding. | 02-17-2011 |
20110039606 | MOBILE TERMINAL AND POWER SOURCE CONTROLLING METHOD THEREOF - A mobile terminal and power source controlling method thereof are disclosed, by which power consumption can be efficiently controlled in a low power mode. The present invention includes calculating a remaining power level of a power supply unit, if the calculated remaining power level is equal to or lower than a predetermined reference, entering a power saving mode, if the power saving mode is entered, activating a basic operation related module, if the power saving mode is entered, comparing a power consumption level required for a designated operation execution to the calculated remaining power level, and if the remaining power level is equal to or higher by a predetermined level or more than the power consumption level as a result of the comparing step, outputting designated operation execution possibility indication information. | 02-17-2011 |
20130056068 | PREPARATION METHOD OF FLEXIBLE ELECTRODES AND FLEXIBLE DYE-SENSITIZED SOLAR CELLS USING THE SAME - The present invention relates to a method for manufacturing a flexible photoelectrode and a dye-sensitized solar cell using the same. More specifically, the method for manufacturingg a photoelectrode comprises forming a nanoparticle metal oxide layer on a flexible substrate, adsorbing dyes, and then, coating polymer, thereby forming a nanoparticle metal oxide layer consisting of nanoparticle metal oxide-dye-polymer. | 03-07-2013 |
20130125970 | COUNTER ELECTRODE FOR DYE-SENSITIZED SOLAR CELL AND PREPARATION METHOD THEREOF - The present invention relates to a counter electrode for DSSC which includes a porous membrane include a carbon-based material calcinated at high temperature and a platinum nano-particles and maintains higher conductivity than a thin membrane and in which the electrolyte moves smoothly, a method of preparing the same, and a DSSC using the same which is improved in photoelectric efficiency. | 05-23-2013 |
20130234075 | TRIPHENYLAMINE DERIVATIVES AND ORGANIC PHOTOVOLTAIC CELLS INCLUDING THE DERIVATIVES - Disclose is a triphenylamine derivative with a low band gap. The triphenylamine derivative is represented by Formula (I): | 09-12-2013 |
20130269781 | POLYMER GEL ELECTROLYTE COMPOSITION, METHOD FOR PREPARING THE COMPOSITION AND DYE-SENSITIZED SOLAR CELL INCLUDING THE COMPOSITION - Disclosed is a polymer gel electrolyte composition. The composition includes an aqueous solution of a polysaccharide-based polymer and a liquid electrolyte in which a redox derivative is mixed with an organic solvent. The composition is easy to inject. The composition is free from problems of leakage and volatilization, thus being environmentally friendly. Further disclosed is a highly efficient dye-sensitized solar cell using the composition. The dye-sensitized solar cell is stable for a long period of time and can be readily commercialized. | 10-17-2013 |
20140020736 | METHOD FOR PRODUCING CIS-BASED THIN FILM, CIS-BASED THIN FILM PRODUCED BY THE METHOD AND THIN-FILM SOLAR CELL INCLUDING THE THIN FILM - Disclosed is a method for producing a CIS-based thin film based on self-accelerated photoelectrochemical deposition. The method includes 1) mixing precursors of elements constituting a CIS-based compound with a solvent to prepare an electrolyte solution, 2) connecting an electrochemical cell including a working electrode, the electrolyte solution and a counter electrode to a voltage or current applying device to construct an electro-deposition circuit, 3) irradiating light onto the working electrode while at the same time applying a cathodic voltage or current to the working electrode to induce self-accelerated photoelectrochemical deposition, thereby electro-depositing a CIS-based thin film, and 4) annealing the electro-deposited CIS-based thin film under a gas atmosphere including sulfur or selenium. | 01-23-2014 |
20140253775 | CONTROL OF INPUT/OUTPUT THROUGH TOUCH - A mobile terminal which includes a touch-screen display method thereof are provided. The mobile terminal includes a touch-screen display; a camera configured to capture image data; a sensing unit located in a corresponding area of the camera; and a controller configured to: receive a first touch gesture in the corresponding area of the camera, turn on the camera in response to the received first touch gesture and display a preview image on the touch-screen display, receive a second touch gestures in the corresponding area of the camera, said first touch gesture being different than the second touch gesture, and capture the image data in response to the second touch gesture, wherein the camera and the sensing unit are mounted on an area of the mobile terminal that excludes the touch-screen display. | 09-11-2014 |
20140335648 | MANUFACTURING METHOD OF SOLID-STATE DYE-SENSITIZED SOLAR CELLS AND ELECTROLYTE FILLING DEVICE USED THEREFOR - The present description is directed to a manufacturing method of solid-state dye-sensitized solar cells and a solid-state electrolyte filling device used in the manufacturing method. The present invention provides a manufacturing method of dye-sensitized solar cells that fills the solid-state electrolyte more uniformly with enhanced efficiency to secure higher light-to-energy conversion efficiency. | 11-13-2014 |
20150027896 | METHOD FOR PRODUCING Cu2ZnSnS4-xSex (0 LESS THAN-EQUAL TO X LESS THAN-EQUAL TO 4) THIN FILM BY ONE STEP ELECTRODEPOSITION IN ELECTROLYTIC BATH CONTAINING IONIC LIQUID | 01-29-2015 |
Patent application number | Description | Published |
20090013824 | Binary alloy single-crystalline metal nanostructures and fabrication method thereof - Disclosed are a method of fabricating a binary alloy nanostructure by using metal oxides, metal substances or metal halides of metal elements used to form a binary alloy and/or binary alloy substances as a precursor through a vapor phase synthesis method and a binary alloy nanostructure fabricated by the same. More particularly, the present invention provides a method of fabricating a binary alloy nanowire or nanobelt which comprises placing a precursor on the front part of a reaction furnace and a substrate on the rear part of the furnace, and heat treating both of them under inert gas atmosphere to produce the nanowire or nanobelt and, in addition, a binary alloy nanowire or nanobelt fabricated by the method according to the present invention. | 01-15-2009 |
20110002251 | TIME SYNCHRONIZATION AND ROUTING METHOD IN WIRELESS SENSOR NETWORK, AND APPARATUS FOR ENABLING THE METHOD - A time synchronization method in a wireless sensor network, a low power routing method using a reservation scheme, and an apparatus for performing the method are provided. The time synchronization method in the wireless sensor network may include: receiving a first synchronization request command packet from a parent node that manages time synchronization for a predetermined synchronization region; receiving, from the parent node, a second synchronization request command packet that has a transmission timestamp value of the first synchronization request command packet; and performing time synchronization for a child node based on a reception time of the first synchronization request command packet, a reception time of the second synchronization request command packet, and the transmission timestamp value of the first synchronization request command packet. | 01-06-2011 |
20110145378 | OPERATING METHOD OF NETWORK NODE OF NETWORK WITH TREE STRUCTURE BASED ON DISTRIBUTED ADDRESS ASSIGNMENT AND NETWORK FORMING METHOD - Provided is a method for operating a network node in a specific cluster of a tree-structured network based on distributed address assignment. In the method, a non-registered node is detected. A routing depth of the network node is determined. When the determined routing depth corresponds to a reference value, a sub cluster using a cluster address is generated, and the detected non-registered node is registered as a child node in the generated sub cluster using an internal address. | 06-16-2011 |
20110149858 | MESH ROUTING METHOD AND MESH ROUTING APPARATUS IN BEACON ENABLED WIRELESS AD-HOC NETWORKS - There is provided a mesh routing method in beacon-enabled wireless AD-HOC networks that includes: broadcasting, by nodes constituting a wireless AD-HOC network, a beacon message loading neighbor node information on a beacon payload; managing, by a node receiving the broadcasted beacon message, its own neighbor node table by extracting the neighbor node information loaded on the beacon payload; and performing, by a source node attempting to transmit data or commands, mesh routing on the basis of its own neighbor node table. | 06-23-2011 |
20140003344 | APPARATUS AND METHOD FOR MULTI-HOP ROUTING DECISION AND LOOPING PREVENTION | 01-02-2014 |
Patent application number | Description | Published |
20100008275 | NODE SYNCHRONIZATION SYSTEM FOR LOW-POWER IN SENSOR NETWORK AND METHOD THEREOF - Provided are a node synchronization system for low-power in a sensor network and a method thereof. The node synchronization system includes: a network transmitting means for transmitting information on a synchronization time difference to the sensing data collecting means and transmitting sensing data to a network; the sensing data collecting means for receiving synchronization time information from the network transmitting means, being synchronized with the network transmitting means, collecting the sensing data from a sensing means, and transmitting the sensing data to the network transmitting means; and the sensing means for receiving synchronization time information from the sensing data collecting means, being synchronized with the sensing data collecting means, sensing a sensing peripheral environment information, and transmitting the sensing data to the sensing data collecting means. | 01-14-2010 |
20100089993 | APPARATUS AND METHOD FOR COLLECTING SHOPPING INFORMATION USING MAGNETIC SENSOR - Provided are an apparatus and method for collecting shopping information using a magnetic sensor. The shopping information collecting apparatus, includes: a magnetic value sensing and analyzing means for sensing and analyzing a magnetic value within own zone in real-time; a central processing means for processing shopping information based on the magnetic value analyzed by the magnetic value sensing and analyzing means; and a shopping information transmitting means for transmitting shopping information processed by the central processing means. | 04-15-2010 |
20100321150 | SYSTEM AND METHOD FOR GUIDING VISITOR USING SENSOR NETWORK - Provided are a system and method for guiding a visitor using a sensor network. The system includes: an entry approval requesting unit for requesting an entry approval of the visitor to the visitee terminal according to destination information; a route setting unit for setting a route along which the visitor terminal is to move to the destination, based on the destination information of the visitor, according to an entry approval result of the visitee terminal; a location detecting unit for detecting a current location of the visitor terminal based on identification information of the visitor terminal and location information of the sensor node, the identification information and the location information being obtained through the sensor network on the route; and a location confirming unit for confirming if the detected current location of the visitor terminal is out of a preset area. | 12-23-2010 |
20100322125 | REMOTE CONTROL METHOD OF SENSOR NODE FOR LOW-POWER AND SENSOR NETWORK THEREFOR - Provided are a remote control method of a sensor node for low-power and a sensor network therefor. The remote control method, including: generating an interrupt signal when a node receives a remote control signal from a corresponding micro radio frequency (RF) processor installed in a gateway; regenerating the interrupt signal when the node is not converted from a sleep mode to a wake-up mode; collecting sensing data by communicating with other nodes when the node is converted from the sleep mode to the wake-up mode; and converting from the wake-up mode into the sleep mode when the communication is completed. | 12-23-2010 |
Patent application number | Description | Published |
20080211013 | SEMICONDUCTOR MEMORY DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions. | 09-04-2008 |
20090035930 | METHOD OF FORMING A WIRE STRUCTURE - In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence. | 02-05-2009 |
20100151655 | METHOD OF FORMING A FINE PATTERN OF A SEMICONUCTOR DEVICE USING A DOUBLE PATTERNING TECHNIQUE - A method of forming a fine pattern of a semiconductor device uses a double patterning technique. A first mask pattern is formed on a first hard mask layer disposed on a substrate. A conformal buffer layer is formed over the first mask pattern. A second mask pattern is formed such that segments of the buffer layer are interposed between the first and second mask patterns, and each topographical feature of the second mask pattern is disposed between two adjacent ones of each respective pair of topographical features of the first mask pattern. A first hard mask pattern is formed by etching the first hard mask layer using the first mask pattern, the second mask pattern, and/or the buffer layer as an etch mask. A trench is formed by etching the substrate using the first hard mask pattern as an etch mask. An isolation layer, of a material that is different from that of first hard mask pattern, is formed in the trench. | 06-17-2010 |
20100221875 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING GATE PATTERNS HAVING STEP DIFFERENCE THEREBETWEEN AND A CONNECTION LINE DISPOSED BETWEEN THE GATE PATTERNS AND METHODS OF FABRICATING THE SAME - Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern. | 09-02-2010 |
20100267210 | Semiconductor device and method of fabricating the same - A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers. | 10-21-2010 |
20100283094 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME - There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively. | 11-11-2010 |
20110175229 | Semiconductor Device and Semiconductor Module Including the Same - Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively. | 07-21-2011 |
20110186923 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F | 08-04-2011 |
20110210421 | TRENCH-TYPE CAPACITOR, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR MODULE HAVING THE SEMICONDUCTOR DEVICE - Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided. | 09-01-2011 |
20110217820 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer. | 09-08-2011 |
20110241102 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 10-06-2011 |
20120001272 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULE AND ELECTRONIC SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a cell area and a peripheral area, the cell area having an active region defined by an isolation region, a cell gate structure below an upper surface of the substrate in the cell area, the cell gate crossing the active region, a bit line structure above an upper surface of the substrate in the cell area, the bit line structure including bit line offset spacers on at least two side surfaces thereof, and a peripheral gate structure above an upper surface of the substrate in the peripheral area, the peripheral gate structure including peripheral gate offset spacers and peripheral gate spacers on at least two side surfaces thereof. | 01-05-2012 |
20120273898 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F | 11-01-2012 |
20130228856 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 09-05-2013 |
20150048444 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 02-19-2015 |