Patent application number | Description | Published |
20100320078 | ELECTROEROSION SPINDLE ASSEMBLY - An electroerosion spindle assembly includes a main shaft, a tool electrode having a rear end directly or indirectly attached to the shaft and in alignment with the main shaft in a longitudinal direction, a container surrounding the main shaft, a stationary-to-rotary electrical conduction device mounted on the container for transitting power energy to the tool electrode, and a channel routing a flushing fluid to a front end of the tool electrode. The channel has at least one flushing slot in the container. | 12-23-2010 |
20100324720 | MACHINING CONTROL SYSTEM - An electroerosion control system includes a general CNC controller being configured for controlling a general CNC machine process, a power supply for energizing a tool electrode and a workpiece to be machined, an electroerosion controller electrically connecting with the power supply for controlling an output of the power supply, and adaptively and electrically connecting with the general CNC controller for communication thereof, and a sensor sensing real-time status information of a working gap between the tool electrode and the workpiece and for sending said real-time status information to said electroerosion controller. Said electroerosion controller automatically controls the electroerosion machining process through the general CNC controller according to the real-time status information of the working gap. | 12-23-2010 |
20120240386 | TOOL COMPENSATION METHOD AND DEVICE - A Method and machine tool for compensating a wear of an electrode that machines a workpiece. The method includes selecting a current pocket from plural pockets of the workpiece; updating a wear compensation to be applied to the electrode for the current pocket based on wear compensation of a previous pocket, where the previous pocket is adjacent to the current pocket; and applying the updated wear compensation to the electrode for machining the current pocket. | 09-27-2012 |
20130220826 | MACHINING SYSTEMS AND METHODS - A machining system for machining a workpiece is provided. The machining system comprises a machine tool, a plurality of cutting tools, a CNC controller. The plurality of cutting tools comprises an electrode and a conventional cutting tool exchangeably disposed on the machine tool. The machining system further comprises a power supply, a process controller, and an electrolyte supply, wherein the machine tool, the electrode, the CNC controller, the power supply, the process controller and the electrolyte supply are configured to cooperate to function as an electroerosion machining device, wherein the machine tool, the CNC controller, the conventional cutting tool and the electrolyte supply are configured to cooperate to function as a conventional machining device, and wherein the machining system is configured to function alternately as the electroerosion machining device and the conventional machining device. | 08-29-2013 |
20140177781 | COLLIMATOR GRID AND AN ASSOCIATED METHOD OF FABRICATION - A collimator grid and a method of fabricating the collimator grid are disclosed. The method includes molding a plurality of plates, each plate includes a plurality of grooves in a first surface, a plurality of fin tips in a second surface disposed opposite to the first surface, plurality of ribs on a first pair of peripheral sides, a plurality of first fiducials formed on the plurality of ribs, and a plurality of second fiducials formed on a second pair of peripheral sides. The method includes machining the second surface to form the plurality of fins having predefined dimensions. Further, the method includes stacking the plurality of plates overlapping each other based on the plurality of first fiducials, and machining the plurality of ribs and first fiducials to form the collimator grid. | 06-26-2014 |
Patent application number | Description | Published |
20110138452 | CROSS SECURITY-DOMAIN IDENTITY CONTEXT PROJECTION WITHIN A COMPUTING ENVIRONMENT - Processing within a computing environment is facilitated by: determining by a local security manager of a first system in a first security domain whether a local security context of a user is acceptable to a second system in a second security domain; responsive to the user's security context being unacceptable to the second system, creating by a local security manager of the second system a runtime security context for the user in the second system; and providing the first system with a reference to the runtime security context for the user in the second system which is resolvable within the computing environment or a portable representation of the runtime security context for the user in the second system, the reference or the portable representation being subsequently returned to the second system with a request from the first system to process work at the second system. | 06-09-2011 |
20110288659 | APPARATUS CONTROL METHOD AND SYSTEM - An apparatus control method and system. The method includes disabling by a computer processor of a computing system, an apparatus. The computer processor retrieves detection data, safety gear detection data, and safety gear indication data. The computer processor analyzes the detection data, the safety gear detection data, and the safety gear indication data and in response to results of the analysis, the computer processor enables the apparatus. | 11-24-2011 |
20110304464 | ATTACHMENT DETECTION METHOD AND SYSTEM - An attachment detection method and system. The method includes receiving, by a computer processor of a computing system, attachment data describing different devices associated with and attachable to an electro/mechanical apparatus. The computer processor retrieves first data describing a first attachment device currently attached to the electro/mechanical apparatus and analyzes the attachment data with respect to the first data. In response to the analysis, the computer processor determines specified protective gear required for operation of the electro/mechanical apparatus and the first attachment device. The computer processor generates indication data specifying required usage of the specified protective gear and presents the indication data to a user. | 12-15-2011 |
20110305375 | DEVICE FUNCTION MODIFICATION METHOD AND SYSTEM - A modification method and system. The method includes performing a computer processor of a computing system, a facial recognition process of an individual associated with a device. The computer processor retrieves from a detection device, eyewear detection data indicating that the individual is correctly wearing eyewear and tint detection data indicating that the eyewear comprises tinted lenses. In response, the computer processor analyzes results of the facial recognition process, the eyewear detection data, and the tint detection data. The computer processor modifies functions associated with the first device in response to results of the analysis. | 12-15-2011 |
20110309936 | INTELLIGENT SWITCHING METHOD AND APPARATUS - An intelligent switching method and system. The method includes retrieving by a computer processor of an intelligent switching device, detection data indicating that an individual is located within a specified proximity of an apparatus. The intelligent switching device is lockably attached to the apparatus. The computer processor receives a request from an individual for enabling the apparatus. The computer processor determines that the individual is in compliance with safety procedures associated with operating the apparatus and generates an enable signal. The enable signal enables a power signal for the apparatus. The computer processor indicates that the apparatus has been enabled and is operational. | 12-22-2011 |
20120290424 | PERSONALIZED ITEM SORTING AND PACKING RECOMMENDATIONS AT A POINT OF SALE - A method and system for determining a recommendation for packing an item at a point of sale (POS). A preference indicating a maximum bag weight is received at a POS device. The weight of a next item to be packed is determined. Based on the maximum bag weight preference and based on the determined weight of the item, the recommendation for packing the item is determined by selecting a bag from multiple bags that are available to pack items to be purchased by a customer. The bag is selected so that a sum of the weight of the item and a weight of zero or more other items already packed in the bag does not exceed the maximum bag weight preference. The recommendation for packing the item in the selected bag is presented to a user. | 11-15-2012 |
20130178955 | APPARATUS SAFEGUARD - A safeguard method and system. The method includes receiving and analyzing apparatus data associated with an electro/mechanical apparatus. A type, mode, and state of the electro/mechanical apparatus are determined and a list of associated safeguard devices is generated and presented to a user. A selection for a safeguard device is received and it is determined if the safeguard device is currently present. In response, a specified action is executed. | 07-11-2013 |
20130241732 | ATTACHMENT DETECTION - An attachment detection method and system. The method includes receiving, by a computer processor of a computing system, attachment data describing different devices associated with and attachable to an electro/mechanical apparatus. The computer processor retrieves first data describing a first attachment device currently attached to the electro/mechanical apparatus and analyzes the attachment data with respect to the first data. In response to the analysis, the computer processor determines specified protective gear required for operation of the electro/mechanical apparatus and the first attachment device. The computer processor generates indication data specifying required usage of the specified protective gear and presents the indication data to a user. | 09-19-2013 |
20130289748 | INTELLIGENT SWITCHING - An intelligent switching method and system. The method includes retrieving by a computer processor of an intelligent switching device, detection data indicating that an individual is located within a specified proximity of an apparatus. The intelligent switching device is lockably attached to the apparatus. The computer processor receives a request from an individual for enabling the apparatus. The computer processor determines that the individual is in compliance with safety procedures associated with operating the apparatus and generates an enable signal. The enable signal enables a power signal for the apparatus. The computer processor indicates that the apparatus has been enabled and is operational. | 10-31-2013 |
20150109612 | OBJECT LOCATION IN THREE DIMENSIONAL SPACE USING LED LIGHTS - A method for performing an action at a device is disclosed. A first signal is sent into a first zone from a first light source, wherein the first signal identifies the first zone. The first signal is received at the device when the device is in the zone. The device determines from the received first signal that the device is in the first zone and performs the action at the device based on the device being in the first zone. A second variable light source may send a second signal into a second zone, wherein the second signal identifies the second zone. Triangulation may be performed to determine a location of the device using the first signal and the second signal. Alternately, a parameter of motion of the device may be determined using the received messages. | 04-23-2015 |
20150113071 | SYMBOLIC VARIABLES WITHIN EMAIL ADDRESSES - Embodiments of the disclosure relate to processing email having symbolic variables in the address. Aspects include receiving, by an email server, an email comprising an email address for an intended recipient and determining whether the email address includes a symbolic variable. Based on determining that the email address includes the symbolic variable, the symbolic variable from the email address are extracted, an email address for an additional recipient by querying a database based on the symbolic variable is identified, and the email is transmitted to the email address of the intended recipient and the email address of the additional recipient. Based on determining that the email address does not include the symbolic variable, the email is transmitted to the email address of the intended recipient. | 04-23-2015 |
20150113081 | SYMBOLIC VARIABLES WITHIN EMAIL ADDRESSES - Embodiments of the disclosure relate to processing email having symbolic variables in the address. Aspects include receiving, by an email server, an email comprising an email address for an intended recipient and determining whether the email address includes a symbolic variable. Based on determining that the email address includes the symbolic variable, the symbolic variable from the email address are extracted, an email address for an additional recipient by querying a database based on the symbolic variable is identified, and the email is transmitted to the email address of the intended recipient and the email address of the additional recipient. Based on determining that the email address does not include the symbolic variable, the email is transmitted to the email address of the intended recipient. | 04-23-2015 |
20150333913 | DETECTION OF DELETED RECORDS IN A SECURE RECORD MANAGEMENT ENVIRONMENT - An automated secure record management system and method that receives a plurality of digitally signed records subsequent to a resetting of a running counter. In response to each received digitally signed record, the automated secure record management system and method increments the running counter. Further, upon receiving an accumulation record, automated secure record management system and method compares a value of the running counter and a signature record number of the accumulation record, such that a notification is generated whenever the comparison detects that the value of the running counter is not equal to the signature record number. | 11-19-2015 |
20150378323 | INTELLIGENT SWITCHING - An intelligent switching method and system. The method includes retrieving by a computer processor of an intelligent switching device, detection data indicating that an individual is located within a specified proximity of an apparatus. The intelligent switching device is lockably attached to the apparatus. The computer processor receives a request from an individual for enabling the apparatus. The computer processor determines that the individual is in compliance with safety procedures associated with operating the apparatus and generates an enable signal. The enable signal enables a power signal for the apparatus. The computer processor indicates that the apparatus has been enabled and is operational. | 12-31-2015 |
Patent application number | Description | Published |
20090081826 | PROCESS FOR MAKING DOPED ZINC OXIDE - The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material. | 03-26-2009 |
20090081842 | PROCESS FOR ATOMIC LAYER DEPOSITION - The present invention relates to a process of making thin film electronic components and devices, such as thin film transistors, environmental barrier layers, capacitors, insulators and bus lines, where most or all of the layers are made by an atmospheric atomic layer deposition process. | 03-26-2009 |
20090261323 | N,N'-DI(ARYLALKYL)-SUBSTITUTED NAPHTHALENE-BASED TETRACARBOXYLIC DIIMIDE COMPOUNDS AS N-TYPE SEMICONDUCTOR MATERIALS FOR THIN FILM TRANSISTORS - A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, a substituted or unsubstituted arylalkyl moiety. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation deposition onto a substrate, wherein the substrate temperature is no more than 100° C. | 10-22-2009 |
20090312553 | N-TYPE SEMICONDUCTOR MATERIALS FOR THIN FILM TRANSISTORS - A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, an aromatic moiety, at least one of which moieties is substituted with at least one electron donating group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation deposition onto a substrate, wherein the substrate temperature is no more than 100° C. | 12-17-2009 |
20100248423 | DELIVERY DEVICE COMPRISING GAS DIFFUSER FOR THIN FILM DEPOSITION - A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed. | 09-30-2010 |
20110097489 | DISTRIBUTION MANIFOLD INCLUDING MULTIPLE FLUID COMMUNICATION PORTS - A fluid conveyance device for thin film material deposition includes a fluid distribution manifold, a primary chamber, and a secondary fluid source. The fluid distribution manifold includes an output face that is connected in fluid communication to the primary chamber. The secondary fluid source is connected in fluid communication to the primary chamber through a plurality of conveyance ports. | 04-28-2011 |
20110210783 | TRANSISTOR INCLUDING REENTRANT PROFILE - A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile. | 09-01-2011 |
20120175614 | TRANSISTOR INCLUDING MULTI-LAYER REENTRANT PROFILE - A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. A third electrically conductive material layer is in contact with and positioned on the second electrically conductive material layer. The third electrically conductive material layer overhangs the second electrically conductive material layer. | 07-12-2012 |
20120175623 | TRANSISTOR INCLUDING MULTIPLE REENTRANT PROFILES - A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer. | 07-12-2012 |
20120175684 | TRANSISTOR INCLUDING REDUCED CHANNEL LENGTH - A transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer. | 07-12-2012 |
20120176181 | ACTUATING TRANSISTOR INCLUDING MULTIPLE REENTRANT PROFILES - A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer. An electrically insulating material layer is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A third electrically conductive material layer is nonconformally positioned over and in contact with a first portion of the semiconductor material layer. A fourth electrically conductive material layer is nonconformally positioned over and in contact with a second portion of the semiconductor material layer. A voltage is applied between the third electrically conductive material layer and the fourth electrically conductive material layer. A voltage is applied to the first electrically conductive material layer to electrically connect the third electrically conductive material layer and the fourth electrically conductive material layer. | 07-12-2012 |
20120176182 | ACTUATING TRANSISTOR INCLUDING MULTI-LAYER REENTRANT PROFILE - A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. A third electrically conductive material layer is in contact with and positioned on the second electrically conductive material layer. The third electrically conductive material layer overhangs the second electrically conductive material layer. An electrically insulating material layer is conformally positioned over the third electrically conductive material layer, the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A fourth electrically conductive material layer is in contact with the semiconductor material layer. A fifth electrically conductive material layer is in contact with the semiconductor material layer. A voltage is applied between the fourth electrically conductive material layer and the fifth electrically conductive material layer. A voltage is applied to the first electrically conductive material layer to electrically connect the fourth electrically conductive material layer and the fifth electrically conductive material layer. | 07-12-2012 |
20120178225 | PRODUCING TRANSISTOR INCLUDING REDUCED CHANNEL LENGTH - A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. The first electrically conductive material layer has a thickness. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer. The second electrically conductive material layer, the first conductive material layer, and at least a portion of the substrate are conformally coated with an electrically insulating material layer having a thickness such that the thickness of the first conductive material layer is greater than the thickness of the electrically insulating material layer. | 07-12-2012 |
20120178246 | PRODUCING TRANSISTOR INCLUDING MULTIPLE REENTRANT PROFILES - A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer. | 07-12-2012 |
20120178247 | PRODUCING TRANSISTOR INCLUDING MULTI-LAYER REENTRANT PROFILE - A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer, a second electrically conductive material layer, and a third electrically conductive material layer. A resist material layer is deposited over the third electrically conductive material layer. The resist material layer is patterned to expose a portion of the third electrically conductive material layer. Some of the third electrically conductive material layer is removed to expose a portion of the second electrically conductive material layer. The third electrically conductive material layer is caused to overhang the second electrically conductive material layer by removing some of the second electrically conductive material layer. Some of the first electrically conductive material layer is removed. | 07-12-2012 |
20130052832 | PRODUCING TRANSISTOR INCLUDING SINGLE LAYER REENTRANT PROFILE - A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer. | 02-28-2013 |
20130082746 | VERTICAL TRANSISTOR HAVING REDUCED PARASITIC CAPACITANCE - A transistor includes a substrate and an electrically conductive material layer stack positioned on the substrate. The electrically conductive material layer stack includes a reentrant profile. A first electrically insulating material layer positioned is in contact with a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally positioned in contact with the first electrically insulating layer, and conformally positioned in contact with a second portion of the electrically conductive material layer stack, and conformally positioned in contact with at least a portion of the substrate. | 04-04-2013 |
20130084681 | PRODUCING A VERTICAL TRANSISTOR INCLUDING REENTRANT PROFILE - Producing a vertical transistor includes providing a substrate including a gate material layer stack with a reentrant profile. A patterned deposition inhibiting material is deposited over a portion of the gate material layer stack and over a portion of the substrate. An electrically insulating material layer is deposited over a portion of the gate material layer stack and over a portion of the substrate using a selective area deposition process in which the electrically insulating material layer is not deposited over the patterned deposition inhibiting material. A semiconductor material layer is deposited over the electrically insulating material layer. | 04-04-2013 |
20130084692 | PRODUCING VERTICAL TRANSISTOR HAVING REDUCED PARASITIC CAPACITANCE - A method of producing a transistor includes providing a substrate including an electrically conductive material layer stack positioned on the substrate. A first electrically insulating material layer is deposited so that the first electrically insulating material layer contacts a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally deposited so that the second electrically insulating material contacts the first electrically insulating layer, and contacts a second portion of the electrically conductive material layer stack, and contacts at least a portion of the substrate. | 04-04-2013 |
20130100183 | VISCOSITY MODULATED DUAL FEED CONTINUOUS LIQUID EJECTOR - A continuous liquid ejector includes a structure including a wall. A portion of the wall defines a nozzle having a first fluidic resistance R | 04-25-2013 |
20130214347 | CIRCUIT INCLUDING VERTICAL TRANSISTORS - An electrical circuit includes a first transistor and a second transistor. Each transistor includes a substrate and a first electrically conductive material layer stack positioned on the substrate. The first electrically conductive material layer stack includes a reentrant profile. A second electrically conductive material layer includes first and second discrete portions in contact with first and second portions of a semiconductor material layer that conforms to the reentrant profile and is in contact with the electrically insulating material layer that conforms to the reentrant profile. A third electrically conductive material layer is in contact with a third portion of the semiconductor material layer and is positioned over the first electrically conductive material layer stack but is not in electrical contact with the first electrically conductive material layer stack. The third electrically conductive material layer of the first transistor and the second transistor are physically separate from each other. | 08-22-2013 |
20130214845 | VERTICAL TRANSISTOR ACTUATION - A method of actuating a semiconductor device includes providing a transistor including a substrate and a first electrically conductive material layer stack positioned on the substrate. The first electrically conductive material layer stack includes a reentrant profile. A second electrically conductive material layer includes first and second discrete portions in contact with first and second portions of a semiconductor material layer that conforms to the reentrant profile and is in contact with an electrically insulating material layer that conforms to the reentrant profile. A voltage is applied between the first discrete portion and the second discrete portion of the second electrically conductive material layer. A voltage is applied to the first electrically conductive material layer stack to modulate a resistance between the first discrete portion and the second discrete portion of the second electrically conductive material layer. | 08-22-2013 |
20140061648 | THIN FILM TRANSISTOR INCLUDING DIELECTRIC STACK - A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A semiconductor layer has a third pattern. A source/drain includes a second electrically conductive layer stack. | 03-06-2014 |
20140061649 | HIGH PERFORMANCE THIN FILM TRANSISTOR - A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack. | 03-06-2014 |
20140061795 | THIN FILM TRANSISTOR INCLUDING IMPROVED SEMICONDUCTOR INTERFACE - A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer has a second pattern. A semiconductor layer is in contact with and has the same pattern as the second inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack. | 03-06-2014 |
20140061869 | ELECTRONIC ELEMENT INCLUDING DIELECTRIC STACK - An electronic element includes a substrate; a patterned first electrically conductive layer on the substrate; a patterned second electrically conductive layer on the substrate; and a dielectric stack on the substrate. A portion of the first electrically conductive layer and a portion of the second electrically conductive layer overlap each other such that an overlap region is present. At least a portion of the dielectric stack is positioned in the overlap region between the patterned first electrically conductive layer and the patterned second electrically conductive layer. The dielectric stack includes a first inorganic thin film dielectric material layer and a second inorganic thin film dielectric material layer. The first inorganic thin film dielectric material layer and the second inorganic thin film dielectric material layer have the same material composition. | 03-06-2014 |
20140065803 | PATTERNED THIN FILM DIELECTRIC STACK FORMATION - A method of producing an inorganic multi-layered thin film structure includes providing a substrate. A patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. A second inorganic thin film material layer is selectively deposited on the region of the substrate where the thin film deposition inhibiting material layer is not present using an atomic layer deposition process. | 03-06-2014 |
20140065830 | PATTERNED THIN FILM DIELECTRIC STACK FORMATION - A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process. The first and second inorganic thin film dielectric material layers form a patterned inorganic thin film dielectric stack. | 03-06-2014 |
20140065831 | PATTERNED THIN FILM DIELECTRIC LAYER FORMATION - A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. | 03-06-2014 |
20140065838 | THIN FILM DIELECTRIC LAYER FORMATION - A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A second inorganic thin film dielectric material layer is deposited on the treated surface of the first inorganic thin film dielectric material layer using an atomic layer deposition process. | 03-06-2014 |
20140374762 | CIRCUIT INCLUDING FOUR TERMINAL TRANSISTOR - An electrical circuit includes a substrate and a plurality of transistors. The plurality of transistors includes a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate includes a second electrically conductive material and a reentrant profile in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. A second electrically insulating material layer conforms to the reentrant profile of the gate and in positioned on at least a portion of the first electrically insulating material layer. A semiconductor material ayer conforms to and is in contact with the second electrically insulating material layer. | 12-25-2014 |
20140374806 | FOUR TERMINAL TRANSISTOR - A transistor includes a substrate, a first electrically conductive material layer positioned on the substrate, and a first electrically insulating material layer is positioned on the first electrically conductive material layer. A gate includes a second electrically conductive material and a reentrant profile in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. A second electrically insulating material layer conforms to the reentrant profile of the gate and in positioned on at least a portion of the first electrically insulating material layer. A semiconductor material layer conforms to and is in contact with the second electrically insulating material layer. | 12-25-2014 |
20140377943 | FOUR TERMINAL TRANSISTOR FABRICATION - Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer. | 12-25-2014 |
20140377955 | SUBSTRATE PREPARATION FOR SELECTIVE AREA DEPOSITION - A method of producing a patterned inorganic thin film element includes providing a substrate having a patterned thin layer of polymeric inhibitor on the surface. The substrate and the patterned thin layer of polymeric inhibitor are exposed to a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in areas without inhibitor using an atomic layer deposition process. | 12-25-2014 |
20140377963 | PATTERNING FOR SELECTIVE AREA DEPOSITION - A method of producing a patterned inorganic thin film element includes providing a substrate. A thin layer of polymeric inhibitor is uniformly depositing on the substrate. A patterned mask having open areas is provided on the thin layer of polymeric inhibitor. The thin layer of polymeric inhibitor is patterned by removing inhibitor from areas exposed by the open areas of the patterned mask using a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in the areas exposed by the removal of the thin layer of polymeric inhibitor using an atomic layer deposition process. | 12-25-2014 |
Patent application number | Description | Published |
20140262452 | EMBOSSED MICRO-STRUCTURE WITH CURED TRANSFER MATERIAL METHOD - A method of making an embossed micro-structure includes providing a transfer substrate, an emboss substrate, and an embossing stamp having one or more stamp structures. Transfer material is coated on the transfer substrate. The transfer material on the transfer substrate is contacted with the stamp structures to adhere transfer material to the stamp structures. A curable emboss layer is coated on the emboss substrate. The stamp structures and adhered transfer material are contacted to the curable emboss layer on the emboss substrate to emboss a micro-structure in the curable emboss layer and transfer the transfer material to the embossed micro-structure. The curable emboss layer is cured to form a cured emboss layer having embossed micro-structures corresponding to the stamp structures and having transfer material in the embossed micro-structures. The stamp structures is removed from the cured emboss layer, substantially leaving the transfer material in the micro-structure. | 09-18-2014 |
20140266402 | TRANSISTOR INCLUDING REENTRANT PROFILE - A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile. | 09-18-2014 |
20140272313 | EMBOSSED MICRO-STRUCTURE WITH CURED TRANSFER MATERIAL - An embossed micro-structure includes an emboss substrate having a cured emboss layer formed thereon. The cured emboss layer has a cured-layer surface opposite the substrate and one or more micro-channels embossed in the cured emboss layer extending from the cured-layer surface into the cured emboss layer toward the substrate. A cured transfer material is located on, in, or beneath the micro-channels. | 09-18-2014 |
20150255292 | FORMING A VTFT WITH ALIGNED GATE - A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure and in the reentrant profile. A photoresist is deposited on the conformal conductive inorganic thin film over the gate structure and filling the reentrant profile. The photoresist is exposed from a side of the photoresist opposite the substrate allowing the photoresist in the reentrant profile to remain unexposed. The conformal conductive inorganic thin film is etched in areas not protected by the photoresist to form a patterned conductive gate layer located in the reentrant profile of the gate structure. | 09-10-2015 |
20150255558 | FORMING A VTFT GATE USING PRINTING - A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure. A polymeric resist is printed that wicks along the reentrant profile of the gate structure. The conformal conductive inorganic thin film is etched in areas not protected by the polymeric resist to form a patterned conductive gate layer located in the reentrant profile of the gate structure. | 09-10-2015 |
20150255579 | VTFT FORMATION USING SELECTIVE AREA DEPOSITION - A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile. | 09-10-2015 |
20150255580 | FORMING A VTFT USING PRINTING - Fabricating a vertical thin film transistor includes printing a polymeric inhibitor in a cap pattern on a structural polymer layer on a substrate. A polymeric inhibitor is printed in a gate pattern on the substrate, in a dielectric pattern on the substrate, in a semiconductor pattern on a patterned conformal dielectric layer, and in an electrode pattern. The electrode pattern includes an open area over a portion of a reentrant profile that allows the polymeric inhibitor to wick along the reentrant profile in the open area. Fabrication of the vertical transistor also includes depositing an inorganic thin film, a first conductive thin film, a dielectric thin film, a semiconductor thin film, and a second conductive thin film using an atomic layer deposition (ALD) process. | 09-10-2015 |
20150255583 | FABRICATING VTFT WITH POLYMER CORE - Fabricating a vertical transistor includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. Exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post defining a reentrant profile. A conformal conductive gate layer and a conformal dielectric layer on the gate layer are formed in the reentrant profile. A conformal semiconductor layer is formed on the dielectric layer. First and second electrodes are formed in contact with a first portion (over the cap) and a second portion (not over the post) of the semiconductor layer. | 09-10-2015 |
20150255620 | VTFTS INCLUDING OFFSET ELECTRODES - A device with multiple vertical transistors includes a substrate and an electrically conductive gate structure including first and second edges opposite each other and including first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the reentrant profiles and is in contact with the gate. A conformal semiconductor layer maintains the reentrant profiles and is in contact with the insulating layer. First and second electrodes are in contact with first and second portions of the semiconductor and adjacent to the first and second reentrant profiles, respectively. A third electrode is in contact with a third portion of the semiconductor on a top of the gate structure. The first and third electrodes and the second and third electrodes define ends of first and second channels of first and second transistors, respectively. First and second lines, extending between the ends of the first and second channels, are not parallel. | 09-10-2015 |
20150255621 | VTFT WITH POLYMER CORE - A transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the post, extends beyond an edge of the post to define a reentrant profile. A conformal conductive material gate layer is over the edge of the post in the reentrant profile. A conformal insulating material layer is on the gate layer in the reentrant profile. A conformal semiconductor material layer is on the insulating material layer in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap. A second electrode is in contact with a second portion of the semiconductor layer over the substrate and not over the post, and adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. | 09-10-2015 |
20150255623 | VTFT WITH POST, CAP, AND ALIGNED GATE - A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top, and an edge along the height dimension. A cap covers the top of the post and extends to a distance beyond the edge of the post to define a reentrant profile. A conformal conductive gate layer is located on the edge of the post in the reentrant profile and not over the cap, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with a first portion of the semiconductor layer over the cap and a second portion of the semiconductor layer not over the post, respectively. | 09-10-2015 |
20150255624 | VTFT INCLUDING OVERLAPPING ELECTRODES - A vertical transistor includes a substrate and an electrically conductive gate structure having a top surface and including a reentrant profile. A conformal electrically insulating layer that maintains the reentrant profile is in contact with the electrically conductive gate structure and at least a portion of the substrate. A conformal semiconductor layer that maintains the reentrant profile is in contact with the conformal electrically insulating layer. An electrode that extends into the reentrant profile is in contact with a first portion of the semiconductor layer. Another electrode is vertically spaced apart from the electrode, overlaps a portion of the electrode that extends into the reentrant profile, is in contact with a second portion of the semiconductor material layer over the top surface of the electrically conductive gate structure, and is within the reentrant profile. | 09-10-2015 |
20150255625 | OFFSET INDEPENDENTLY OPERABLE VTFT ELECTRODES - A multiple vertical transistor device includes a polymeric material post on a substrate. An inorganic material cap extends beyond first and second edge of the post to define first and second reentrant profiles. First and second portions of a conformal conductive gate layer define first and second gates in the first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the first and second reentrant profiles and is in contact with the first and second gates. First and second portions of a semiconductor layer, maintaining the first and second reentrant profiles, are in contact with the conformal electrically insulating layer that is in contact with the first and second gates, respectively. The first and second portions of the semiconductor layer are electrically independent from each other. First and second electrodes are associated with the first gate. Third and fourth electrodes are associated with the second gate. | 09-10-2015 |
20150255626 | VTFT WITH GATE ALIGNED TO VERTICAL STRUCTURE - A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top portion of the post which extends a distance beyond a bottom portion of the post in a direction parallel to the substrate to define a reentrant profile. A conformal conductive gate layer is located on an edge of the post in the reentrant profile and not over the top portion of the post, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with first and second portions of the semiconductor layer over the top portion of the post and not over the top portion of the post, respectively. | 09-10-2015 |
20150257283 | FORMING VERTICALLY SPACED ELECTRODES - Producing vertically separated electrodes includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. The exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post to define a reentrant profile. A polymeric inhibitor is provided in the reentrant profile. A conductive inorganic thin film is deposited where the polymeric inhibitor is absent using an atomic layer deposition process to form a first electrode located over the cap and a second electrode over the substrate and not over the post. | 09-10-2015 |
20160076146 | METHOD OF FORMING A PATTERNED POLYMER LAYER - A method of producing a patterned polymeric insulator includes providing a substrate. A patterned polymeric inhibitor is provided on the substrate. An inorganic thin film is deposited using an atomic layer deposition process on the substrate in an area where the patterned polymeric inhibitor is absent. A material layer is deposited over the inorganic thin film and the patterned polymeric inhibitor. | 03-17-2016 |
20160079385 | VERTICAL TFT WITH MULTILAYER PASSIVATION - A vertical transistor includes an electrically conductive gate structure having a reentrant profile in contact with a substrate. A conformal gate insulating layer is in contact with the gate structure in the reentrant profile. A conformal semiconductor layer is in contact with the conformal gate insulating layer. A first electrode is in contact with a first portion of the conformal semiconductor layer over the electrically conductive gate structure. A second electrode is in contact with a second portion of the conformal semiconductor layer and separated vertically from the first electrode. The vertical TFT has a multilayer insulating structure that is in contact with at least the conformal semiconductor layer in the reentrant profile. The multilayer insulating structure includes an inorganic dielectric layer and a polymer structure in contact with the conformal semiconductor layer in the reentrant profile. | 03-17-2016 |
20160079429 | TOP GATE TFT WITH POLYMER INTERFACE CONTROL LAYER - A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap. | 03-17-2016 |
20160079440 | BOTTOM GATE TFT WITH MULTILAYER PASSIVATION - A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap. | 03-17-2016 |
Patent application number | Description | Published |
20090311416 | METHOD AND SYSTEM FOR MACHINING A PROFILE PATTERN IN CERAMIC COATING - A method of machining a profile pattern in a ceramic coating of a turbine shroud is provided and includes applying the ceramic coating substantially uniformly onto the turbine shroud, positioning a machining tool proximate the ceramic coating, and removing material from the ceramic coating by activating the machining tool to machine the ceramic coating and by moving the machining tool across the ceramic coating in a movement pattern that generally corresponds to the profile pattern. | 12-17-2009 |
20100081009 | Spray Application of Liquid Precursors for CMAS Resistant Coatings - Methods and systems of applying a liquid precursor for a calcium-magnesium-aluminosilicate (CMAS) resistant coating to a turbine engine component are provided. In one embodiment, a method of manufacturing a turbine engine includes spraying a liquid compound, wherein the liquid component is stored with a carrier gas, applying the compound to a component of a turbine engine, such that the compound is disposed on a thermal barrier coating of the component, and forming an oxide layer on the thermal barrier coating of the component. In another embodiment, a system includes a turbine engine component and a sprayer containing a compound and a carrier gas, wherein the sprayer is configured to apply the compound to a thermal barrier coating of the component such that the compound forms an oxide on the thermal barrier coating. | 04-01-2010 |
20100284797 | ABRADABLE SEALS - In one embodiment, an abradable seal includes a soft material that may be worn away and a hard material that may provide mechanical strength for the abradable seal. The soft material and the hard material may include different compositions of a base material. | 11-11-2010 |
20120134786 | COMPRESSOR BLADE WITH FLEXIBLE TIP ELEMENTS AND PROCESS THEREFOR - A compressor blade and process for inhibiting rub encounters between a blade tip of the blade and an interior surface of a case that surrounds the rotating hardware within a compressor section of a turbomachine. The compressor blade includes a cap that defines the blade tip at a radially outermost end of the blade, and a plurality of flexible elements extending from a surface of the cap that defines the blade tip. The flexible elements extend from the surface in a span-wise direction of the blade, and are operable to become rigid due to centrifugal stiffening at compressor operating speeds and, optionally, cut a groove the interior surface of the case. | 05-31-2012 |
20130180432 | COATING, A TURBINE COMPONENT, AND A PROCESS OF FABRICATING A TURBINE COMPONENT - Disclosed is a coating, a turbine component, and a process of fabricating a turbine component. The coating includes a ceramic phase formed by ceramic particles and a ductile matrix having a ductility greater than the ceramic phase. The ceramic phase includes substantially the same microstructure as the ceramic particles. The turbine component includes a surface having the coating. The process includes applying the coating to the surface of the turbine component. | 07-18-2013 |
20130216798 | COATED ARTICLE AND PROCESS OF COATING AN ARTICLE - A coated article and a coating application process are disclosed. The coated article includes a metallic surface, a first layer positioned proximal to the metallic surface, the first layer having a first ductility, and a second layer positioned distal from the metallic surface, the second layer having a second ductility. The first ductility is at least about 20% greater than the second ductility. The process includes providing an article, the article comprising a metallic surface, applying a first layer proximal to the metallic surface, the first layer having a first ductility, and applying a second layer distal from the metallic surface, the second layer having a second ductility. | 08-22-2013 |
20140147242 | SEAL SYSTEMS FOR USE IN TURBOMACHINES AND METHODS OF FABRICATING THE SAME - A seal system, for an apparatus that includes a rotatable portion with airfoils coupled thereto and a stationary portion with an inner surface, includes an abradable portion including at least one abradable layer of an abradable material formed over the inner surface. The seal system also includes an abrading portion disposed over at least a portion of a substrate of the airfoil. The abrading portion includes at least one abrading layer formed on at least a portion of the substrate and a plurality of abrasive particles embedded within the abrading layer. The plurality of abrasive particles includes at least one of substantially all of one of tantalum carbide (TaC), aluminum oxide (Al | 05-29-2014 |
20140193760 | COATED ARTICLE, PROCESS OF COATING AN ARTICLE, AND METHOD OF USING A COATED ARTICLE - A coated article, a process of coating an article, and a process of using an article are disclosed. The coated article includes a substrate, a porous coating material, and a thermal barrier coating material. The porous coating material includes a porosity between about 1 percent and about 20 percent, by volume. The thermal barrier coating material has a thermal conductivity that is lower than a thermal conductivity of the substrate. The porous coating material differs in one or both of composition and microstructure from the thermal barrier coating material. Additionally or alternatively, the porous coating material resists at least one of sintering, densification, and phase destabilization for a predetermined period at a predetermined temperature. The process of coating an article includes applying a coating to form the coated article. | 07-10-2014 |
20150118060 | TURBINE ENGINE BLADES, RELATED ARTICLES, AND METHODS - A compressor blade generally used in turbine engines is presented. The compressor blade includes a protective covering bonded to a tip portion of the blade with a braze material. The braze material includes from about 1 weight percent to about 10 weight percent of an active metal element, based on the total amount of the braze material. A compressor rotor is also provided that includes a plurality of the compressor blades. A method for joining a protective covering to a tip portion of a compressor blade, and a method for repair of a compressor blade, are also provided. | 04-30-2015 |