Patent application number | Description | Published |
20100134937 | Over-Voltage Protection Device and Method for Manufacturing thereof - An over-voltage protection device and a method for manufacturing the over-voltage protection device are provided. The over-voltage protection device includes a substrate, a pair of electrode layers, a mask layer, and a sealing layer. The electrode layers are disposed on the substrate, and a gap is formed between the electrode layers. The mask layer is disposed over the gap and a portion of the electrode layers. The sealing layer covers the mask layer and the gap. | 06-03-2010 |
20110057761 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a bridge element is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The bridge element spans across the metal element in a direction across direction of current flow in the metal element, wherein the bridge element facilitates breaking of the metal element upon melting. | 03-10-2011 |
20110058295 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a first auxiliary medium is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The first auxiliary medium is disposed between the metal element and the substrate, wherein the first auxiliary medium has a melting point lower than that of the metal element. The first auxiliary medium facilitates breaking of the metal element upon melting. | 03-10-2011 |
20130250470 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a first auxiliary medium is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The first auxiliary medium is disposed between the metal element and the substrate, wherein the first auxiliary medium has a melting point lower than that of the metal element. The first auxiliary medium facilitates breaking of the metal element upon melting. | 09-26-2013 |
20130321119 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a bridge element is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The bridge element spans across the metal element in a direction across direction of current flow in the metal element, wherein the bridge element facilitates breaking of the metal element upon melting. | 12-05-2013 |
20140133059 | PROTECTIVE DEVICE AND PROTECTIVE MODULE - A protective device includes a substrate, an electrode layer, a metal structure, an outer cover and an arc extinguishing structure. The electrode layer is disposed on the substrate. The electrode layer includes at least one gap. The metal structure is disposed on the electrode layer and located above the gap, and the metal structure has a melting temperature lower than a melting temperature of the electrode layer. The outer cover is disposed on the substrate and covers the metal structure and a portion of the electrode layer. The arc extinguishing structure is disposed between the outer cover and the substrate. A protective module is further provided. | 05-15-2014 |
Patent application number | Description | Published |
20090134929 | Level shifter for high-speed and low-leakage operation - The present invention discloses a voltage level shifter capable of interfacing between two circuit systems having different operating voltage swings. The voltage level shifter comprises an input buffer having a low supply voltage for inverting an external input signal to an internal input signal, and an output buffer having a high supply voltage for inverting the internal input signal to an external output signal. The high level of the external input signal is lower than the high level of the external output signal. The voltage level shifter is designed such that the input buffer is operating to achieve a low-leakage and high-speed performance. | 05-28-2009 |
20090174439 | MULTIFUNCTIONAL OUTPUT DRIVERS AND MULTIFUNCTIONAL TRANSMITTERS USING THE SAME - A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver. | 07-09-2009 |
20100111156 | TUNABLE EQUALIZER AND METHODS FOR ADJUSTING THE TUNABLE EQUALIZER - A tunable equalizer with a tunable equalizer frequency response is provided. The tunable equalizer includes an amplifier circuit for amplifying input signals and a tunable circuit coupled to the amplifier circuit. The tunable circuit is arranged to provide a zero point in the equalizer frequency response and the zero point is adjusted according to a controllable value. When the controllable value varies according to a uniform offset, the corresponding zero point varies according to a non-uniform offset. | 05-06-2010 |
20100118932 | MULTIFUNCTIONAL TRANSMITTERS - Multifunctional transmitters capable of transmitting signals of different specifications in different modes are provided, in which N output units are provided and each output unit comprises a serializer and an output driver. A control unit, according to a mode selection signal, selects a first set of output units from the N output units to transmit a first video data compatible with a first transmission interface under a first transmission mode and selects a second set of output units from the first set of output units to transmit a second video data compatible with a second transmission interface which is different from the first transmission interface under a second transmission mode. | 05-13-2010 |
20110006932 | PROGRAMMABLE DESERIALIZER - A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal. | 01-13-2011 |
20110043259 | Multifunctional Output Drivers and Multifunctional Transmitters Using the Same - A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver. | 02-24-2011 |
20120014080 | ELECTRONIC DEVICE HAVING CIRCUIT BOARD WITH CO-LAYOUT DESIGN OF MULTIPLE CONNECTOR PLACEMENT SITES AND RELATED CIRCUIT BOARD THEREOF - An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites. | 01-19-2012 |
20120112794 | DIFFERENTIAL DRIVER WITH CALIBRATION CIRCUIT AND RELATED CALIBRATION METHOD - A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage. | 05-10-2012 |
20120300831 | METHODS FOR PERFORMING ADAPTIVE EQUALIZATION AND ASSOCIATED APPARATUS - A method for performing adaptive equalization includes: dynamically detecting current levels of a plurality of sets of pattern levels respectively corresponding to a plurality of data patterns, wherein each set of the sets of pattern levels includes a previous level, a current level, and a next level respectively corresponding to one of the plurality of data patterns; and dynamically calculating a plurality of data decision levels according to the current levels of the sets of pattern levels, for use of data decision, wherein each data decision level of at least one portion of the plurality of data decision levels is not equal to zero, and the data decision levels are dynamically adjusted in accordance with the current levels of the sets of pattern levels, in order to enhance a signal-to-noise ratio (SNR). An associated method for performing adaptive equalization is also provided. Associated apparatus are also provided. | 11-29-2012 |
20130088929 | LOW POWER MEMORY CONTROLLERS - A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source. | 04-11-2013 |
20130113516 | TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF - A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers. | 05-09-2013 |
20140137065 | ELECTRONIC DEVICE HAVING CIRCUIT BOARD WITH CO-LAYOUT DESIGN OF MULTIPLE CONNECTOR PLACEMENT SITES AND RELATED CIRCUIT BOARD THEREOF - An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites. | 05-15-2014 |
20150022243 | DRIVER CIRCUIT FOR SIGNAL TRANSMISSION AND CONTROL METHOD OF DRIVER CIRCUIT - A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair of differential output terminals, a current mode drive unit and a voltage mode drive unit. The pair of differential output terminals has a first output terminal and a second output terminal. The current mode drive unit is arranged for outputting a first reference current from one of the first and second output terminals and receiving the first reference current from the other of the first and the second output terminals according to the first data input. The voltage mode drive unit is arranged for coupling a first reference voltage to one of the first and the second output terminals and coupling a second reference voltage to the other of the first and the second output terminals according to the first data input. | 01-22-2015 |
20150074346 | MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM - A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed. | 03-12-2015 |
20150091540 | REGULATOR AND REGULATING METHOD - A regulator applied to regulate a first reference voltage on an output terminal, the regulator includes: a sensing circuit, arranged to sense a variation of the first reference voltage on the output terminal to generate a sensing signal; and a gain stage, arranged to provide an adjusting current to the output terminal in response to the sensing signal for reducing the variation of the first reference voltage, and the gain stage is coupled in parallel to a loading circuit powered by the first reference voltage. | 04-02-2015 |
20150349763 | METHOD FOR PERFORMING PHASE SHIFT CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals. | 12-03-2015 |
20160056980 | METHOD FOR PERFORMING DATA SAMPLING CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver. | 02-25-2016 |
20160065397 | METHOD FOR PERFORMING LOOP UNROLLED DECISION FEEDBACK EQUALIZATION IN AN ELECTRONIC DEVICE WITH AID OF VOLTAGE FEEDFORWARD, AND ASSOCIATED APPARATUS - A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively. | 03-03-2016 |
20160099710 | METHOD FOR PERFORMING PHASE SHIFT CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital control signals. | 04-07-2016 |