Patent application number | Description | Published |
20090302327 | RUGGED SEMICONDUCTOR DEVICE ARCHITECTURE - A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer. | 12-10-2009 |
20120187474 | Trench Power MOSFET With Reduced On-Resistance - A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions. | 07-26-2012 |
20120267714 | DOUBLE LAYER METAL (DLM) POWER MOSFET - This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically. | 10-25-2012 |
20120273871 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 11-01-2012 |
20120273884 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 11-01-2012 |
20120273916 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 11-01-2012 |
20150069567 | SUPERJUNCTION STRUCTURES FOR POWER DEVICES AND METHODS OF MANUFACTURE - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 03-12-2015 |
20150187873 | SUPERJUNCTION STRUCTURES FOR POWER DEVICES AND METHODS OF MANUFACTURE - A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region. | 07-02-2015 |
Patent application number | Description | Published |
20090090966 | HIGH DENSITY FET WITH INTEGRATED SCHOTTKY - A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween. | 04-09-2009 |
20090111227 | Method for Forming Trench Gate Field Effect Transistor with Recessed Mesas Using Spacers - A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions. | 04-30-2009 |
20090315083 | Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices - A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. | 12-24-2009 |
20100320534 | Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices - A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench. | 12-23-2010 |
20120156845 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE - A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches. | 06-21-2012 |
20120319197 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 12-20-2012 |
20140203355 | FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES - In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region. | 07-24-2014 |
Patent application number | Description | Published |
20130268999 | DEVICE PINNING CAPABILITY FOR ENTERPRISE CLOUD SERVICE AND STORAGE ACCOUNTS - Device pinning capabilities for cloud-based services and/or storage accounts are disclosed. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, for authorizing synchronization of a synchronization client on a device with content associated with an account in the cloud-based service, responsive to determining that the device is on a list of devices that are authorized, and synchronizing the synchronization client on the device with the content associated with the account such that the content is also locally available for access on the device. The list of devices can be specific to and associated with devices for a user in the account and can be limited to an allowable number of devices for the account or a user associated with the account. | 10-10-2013 |
20130311894 | SECURITY ENHANCEMENT THROUGH APPLICATION ACCESS CONTROL - Security enhancement through application access control for cloud-based services and/or storage accounts is disclosed. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, for providing, via the collaboration environment, applications for use by a user in the collaboration environment. The applications are selectable by a user, through the collaboration environment, for use in interaction and engagement with other users in the collaboration environment in collaboration sessions. The applications that are visible or available for use by the user is configurable by another user (e.g., administrator or IT specialist) with appropriate permissions, though a designated console. | 11-21-2013 |
20140082071 | SANDBOXING INDIVIDUAL APPLICATIONS TO SPECIFIC USER FOLDERS IN A CLOUD-BASED SERVICE - An example system and method comprises receiving a request from the third-party application, wherein the request includes a user identifier; allocating an area that is specific for the third-party application and for the user; and granting access of the area to the third-party application. In one embodiments, the method further comprises providing to the third-party application a token which allows the third-party application to access a given area. Additional embodiments provided herein enable a third-party application to use a user identifier (e.g., an email address or other identifiers) of its user to access area specific of a cloud-based environment/platform/services (e.g., collaboration, file sharing, and/or storage services) without necessarily triggering user account authentication, thereby avoiding the process of requiring access codes from the user which can adversely impact user experience as well as compromise security and/or user's privacy. | 03-20-2014 |
20140082091 | CLOUD-BASED PLATFORM ENABLED WITH MEDIA CONTENT INDEXED FOR TEXT-BASED SEARCHES AND/OR METADATA EXTRACTION - Techniques are disclosed for enabling collaborative work on a media content among collaborators through a cloud-based environment. An example method comprises receiving the media content; extracting a plurality of text-based data based on the media content; and indexing the plurality of text-based data so as to enable one or more actions to be performed on the media content using the plurality of text-based data. In some embodiments, the media content comprises an audio component, and the method further comprises transcribing the audio component of the media content so that the plurality of text-based data comprises a transcript of the media content. In some embodiments, the actions include a text-based search or a semantics-based search. Among other benefits, some embodiments provided herein enable indexing media content for text-based searches and/or metadata extraction to effectively manage multimedia files in a cloud-based storage/service environment. | 03-20-2014 |