Patent application number | Description | Published |
20100110772 | Semiconductor memory device having bit line disturbance preventing unit - A read data path circuit for use in the semiconductor memory device includes a bit line sense amplifier, a local input/output line sense amplifier, a column selection unit operationally coupling a bit line pair with the local input/output line pair in response to a column selection signal, where the bit line pair is coupled to the bit line sense amplifier and the local input/output line pair is coupled to the local input/output line sense amplifier, and a bit line disturbance preventing unit configured to equalize signal levels of the local input/output line pair before the column selection signal is activated, and configured to sense and amplify signal levels of bit line data transferred to the local input/output line pair after the column selection signal is activated. | 05-06-2010 |
20100128545 | Sense amplifier and semiconductor memory device using it - A sense amplifier having a pre-amplifier and a main-amplifier is disclosed. The pre-amplifier is connected to paired data line, senses and amplifies data on the paired data line using voltage mode and outputting a pair of differential signal. The main-amplifier is connected to the paired data line, senses and amplifies data on the paired data line using current mode and generating a first amplified signal, senses and amplifies the first amplified signal using voltage mode in response to the pair of differential signal, and outputting an amplified data. | 05-27-2010 |
20100231280 | DELAY CELL THAT INVERSELY RESPONDS TO TEMPERATURE - A delay cell structure that inversely responds to temperature is provided. A first current mirror includes first and second transistors having sources commonly connected to a power supply terminal. A second current mirror includes third and fourth transistors having drains connected to the channels of the first and second transistors and sources commonly connected to a ground terminal. A resistor is connected between the drains of the first and second transistors. An inverter is provided between the drains of the second and fourth transistors so as to face the resistor and outputting a delay signal that is later than input signal by a delay time proportional to the threshold voltages of the first and third transistors which vary as a function of temperature. | 09-16-2010 |
Patent application number | Description | Published |
20080274610 | METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION BARRIER FILM - Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics. | 11-06-2008 |
20090166868 | Semiconductor devices including metal interconnections and methods of fabricating the same - A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern. | 07-02-2009 |
20100151672 | METHODS OF FORMING METAL INTERCONNECTION STRUCTURES - Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer. | 06-17-2010 |
20130005154 | METHOD OF FORMING A DIELECTRIC LAYER HAVING AN ONO STRUCTURE USING AN IN-SITU PROCESS - A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer. | 01-03-2013 |