Patent application number | Description | Published |
20100002159 | LIQUID CRYSTAL DISPLAY PANEL AND PIXEL STRUCTURE THEREOF - A pixel structure of a liquid crystal display panel includes a first transparent substrate, a first data line, a second data line, a transparent electrode, and a compensating conducting pattern layer. In a display region, the first side of the transparent electrode and the first data line partially overlap, forming a first parasitic capacitor, the second side of the transparent electrode and the second data line partially overlap, forming a second parasitic capacitor smaller than the first parasitic capacitor. In a non-display region, the first side of the transparent electrode and the first data line partially overlap, forming a third parasitic capacitor, and the second side of the transparent electrode and the compensating conducing pattern layer partially overlap, forming a fourth parasitic capacitor. The total parasitic capacitance of the first and the third parasitic capacitors and the total parasitic capacitance of the second and the fourth parasitic capacitors are substantially equal. | 01-07-2010 |
20110169018 | Liquid Crystal Display Device - An exemplary liquid crystal display device includes a data line, a pixel, a first gate line, a second gate line, an additional electrode and an additional gate line. The pixel includes a first sub-pixel and a second sub-pixel. The first gate line is electrically coupled to the first sub-pixel. The second gate line is electrically coupled to the second sub-pixel. The first sub-pixel is electrically coupled to the data line to receive a signal provided from the data line. The second sub-pixel is electrically coupled to the first sub-pixel through the additional electrode and to receive a signal provided from the data line through the first sub-pixel. The additional gate line is arranged crossing over the additional electrode and whereby a compensation capacitance is formed between the additional gate line and the additional electrode. | 07-14-2011 |
20110242065 | DISPLAY PANEL - A display panel includes at least twelve sub-pixels, arranged continuously in a row. In a scanning time of the display panel, sub-pixels respectively disposed at a 2nd, 3rd, 5th, 8th, 10th and 12th column have a first polarity, and sub-pixels respectively disposed at a 1st, 4th, 6th, 7th, 9th and 11th column have a second polarity. The first polarity is opposite to the second polarity. | 10-06-2011 |
20130120681 | LIQUID CRYSTAL DISPLAY DEVICE - An exemplary liquid crystal display device includes a data line, a pixel, a first gate line, a second gate line, an additional electrode and an additional gate line. The pixel includes a first sub-pixel and a second sub-pixel. The first gate line is electrically coupled to the first sub-pixel. The second gate line is electrically coupled to the second sub-pixel. The first sub-pixel is electrically coupled to the data line to receive a signal provided from the data line. The second sub-pixel is electrically coupled to the first sub-pixel through the additional electrode and to receive a signal provided from the data line through the first sub-pixel. The additional gate line is arranged crossing over the additional electrode and whereby a compensation capacitance is formed between the additional gate line and the additional electrode. | 05-16-2013 |
Patent application number | Description | Published |
20120270369 | Methods for Lead Free Solder Interconnections for Integrated Circuits - Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper. | 10-25-2012 |
20130056869 | PILLAR STRUCTURE HAVING A NON-PLANAR SURFACE FOR SEMICONDUCTOR DEVICES - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 03-07-2013 |
20130056872 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 03-07-2013 |
20130119539 | Package Structures and Methods for Forming the Same - A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface. | 05-16-2013 |
20130181325 | Through-Assembly Via Modules and Methods for Forming the Same - A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias. | 07-18-2013 |
20130182402 | PoP Structures Including Through-Assembly Via Modules - A device includes a Through-Assembly Via (TAV) Module, which includes a substrate, a plurality of through-vias penetrating through the substrate, and a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias. A polymer includes a first portion between and contacting sidewalls of the first package component and the TAV module, a second portion disposed between the first plurality of metal posts, and a third portion disposed between the second plurality of metal posts. A first plurality of Redistribution Lines (RDLs) is underlying a bottom surface of the second and the third portions of the polymer. A second plurality of RDLs is over the first package component and the TAV module. The first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module. | 07-18-2013 |
20130241052 | Methods and Apparatus for Solder on Slot Connections in Package on Package Structures - Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed. | 09-19-2013 |
20130256836 | Package-on-Package (PoP) Device with Integrated Passive Device - A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor. | 10-03-2013 |
20130270682 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 10-17-2013 |
20130292827 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 11-07-2013 |
20140021583 | PACKAGE STRUCTURES INCLUDING A CAPACITOR AND METHODS OF FORMING THE SAME - A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. | 01-23-2014 |
20140027901 | PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS AND METHODS FOR FORMING THE SAME - A device includes a device die and a plurality of metal posts at a surface of the device die and electrically coupled to the device die. The device further includes a plurality of through-assembly vias (TAVs), a dam member between the device die and the plurality of TAVs, and a polymer layer encompassing the device die, the plurality of metal posts, the plurality of TAVs, and the dam member. | 01-30-2014 |
20140061937 | Fan-Out Package Comprising Bulk Metal - A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package. | 03-06-2014 |
20140070422 | Semiconductor Device with Discrete Blocks - A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers. | 03-13-2014 |
20140077394 | Wafer Level Embedded Heat Spreader - Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads. | 03-20-2014 |
20140091471 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 04-03-2014 |
20140103540 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 04-17-2014 |
20140127866 | Package Structures Including a Capacitor and Methods of Forming the Same - A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. | 05-08-2014 |
20140131858 | Warpage Control of Semiconductor Die Package - Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved. | 05-15-2014 |
20140210099 | Packaged Semiconductor Devices and Packaging Methods - Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads. | 07-31-2014 |
20140231994 | APPARATUS FOR LEAD FREE SOLDER INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper. | 08-21-2014 |
20140239507 | Peripheral Electrical Connection of Package on Package - Various embodiments of mechanisms for forming a die package using through sidewall vias (TsVs), which are formed by sawing through substrate via (TSV) in half, at edges of dies described enable various semiconductor dies and passive components be electrically connected to achieve targeted electrical performance. Redistribution structures with redistribution layers (RDLs) are used along with the TsVs to enable the electrical connections. Since the TsVs are away from the device regions, the device regions do not suffer from the stress caused by the TSV formation. In addition, electrical connections between upper and lower dies by the TsVs increases the efficiency of the area utilization of the die package. | 08-28-2014 |
20140248722 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 09-04-2014 |
20140252647 | Warpage Reduction and Adhesion Improvement of Semiconductor Die Package - Various embodiments of mechanisms for forming a die package and a package on package (PoP) structure using one or more compressive dielectric layers to reduce warpage are provided. The compressive dielectric layer(s) is part of a redistribution structure of the die package and its compressive stress reduces or eliminates bowing of the die package. In addition, the one or more compressive dielectric layers improve the adhesion between redistribution structure and the materials surrounding the semiconductor die. As a result, the yield and reliability of the die package and PoP structure using the die package are improved. | 09-11-2014 |
20140264337 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost. | 09-18-2014 |
20140264769 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package. | 09-18-2014 |
20140302669 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 10-09-2014 |
20140335662 | METHODS FOR FORMING PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS - Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs. | 11-13-2014 |
20150069595 | Apparatus and Method for a Component Package - A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. | 03-12-2015 |
20150072476 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 03-12-2015 |
20150093881 | Through-Assembly Via Modules and Methods for Forming the Same - A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias. | 04-02-2015 |
Patent application number | Description | Published |
20080225506 | Display Panel and a Light Source Used Therein - A display panel and a light source device used therein are provided. The display panel includes a light-guide thin-film circuit substrate, a light source and a polarizing layer. The light-guide thin-film circuit substrate has a light entrance end and a light exit top surface, and the light source is disposed corresponding to the light entrance end. The polarizing layer is disposed on the light-guide thin-film circuit substrate and parallels the light exit top surface of the light-guide thin-film circuit substrate. The light produced by the light source enters the circuit substrate through the light entrance end, guided and transmitted through the circuit substrate, and then leaves the circuit substrate through the light exit top surface and enters the polarizing layer. The light after passing through the polarizing layer is turned into a polarized light having flat light source effect as a backlight source for the system. A polarizer may even be disposed between the light source and the light entrance end, so the light is turned into polarized light before entering the circuit substrate. | 09-18-2008 |
20100134999 | Display Panel and a Light Source Used Therein - A display panel and a light source device used therein are provided. The display panel includes a light-guide thin-film circuit substrate, a light source and a polarizing layer. The light-guide thin-film circuit substrate has a light entrance end and a light exit top surface, and the light source is disposed corresponding to the light entrance end. The polarizing layer is disposed on the light-guide thin-film circuit substrate and parallels the light exit top surface of the light-guide thin-film circuit substrate. The light produced by the light source enters the circuit substrate through the light entrance end, guided and transmitted through the circuit substrate, and then leaves the circuit substrate through the light exit top surface and enters the polarizing layer. The light after passing through the polarizing layer is turned into a polarized light having flat light source effect as a backlight source for the system. A polarizer may even be disposed between the light source and the light entrance end, so the light is turned into polarized light before entering the circuit substrate. | 06-03-2010 |
20120140434 | Display Panel and a Light Source Used Therein - A display panel and a light source device used therein are provided. The display panel includes a light-guide thin-film circuit substrate, a light source and a polarizing layer. The light-guide thin-film circuit substrate has a light entrance end and a light exit top surface, and the light source is disposed corresponding to the light entrance end. The polarizing layer is disposed on the light-guide thin-film circuit substrate and parallels the light exit top surface of the light-guide thin-film circuit substrate. The light produced by the light source enters the circuit substrate through the light entrance end, guided and transmitted through the circuit substrate, and then leaves the circuit substrate through the light exit top surface and enters the polarizing layer. The light after passing through the polarizing layer is turned into a polarized light having flat light source effect as a backlight source for the system. | 06-07-2012 |
20140016346 | ELECTRONIC APPARATUS - An electronic apparatus including a back cover, a frame body, a transparent plate, and a display unit is provided. The frame body is disposed on the back cover and has a first supporting surface and a second supporting surface. The transparent plate is supported on the first supporting surface. The display unit is supported on the second supporting surface and adhered to the transparent plate, and the display unit is held between the second supporting surface and the transparent plate. | 01-16-2014 |
20140029295 | HYBRID LIGHT GUIDE PLATE AND DISPLAY DEVICE - A display device includes a housing, a frame bonded to the housing, and a display module. The display module includes a back cover bonded to the frame, a light guide plate (LGP), a support element, a display panel, and an optical film set. The LGP is supported on the back cover and has a light exiting surface and an opposite back surface. At least two sides of the LGP's back surface are adhered on the back cover, and the LGP is made of glass. The support element and display panel are supported respectively on the LGP and support element. The optical film set is between the display panel and LGP. A hybrid LGP includes a first light guide sub-plates and a second light guide sub-plate. The second light guide sub-plate is stacked on and bonded to the first light guide sub-plate. | 01-30-2014 |
20150116607 | DISPLAY DEVICE - A display device includes a casing, a frame, a backlight module, at least one cable, and a display panel. The casing has a display opening. The frame is disposed in an inner edge of the display opening, wherein the frame has at least a cable management groove and a support surface. The backlight module is disposed on the frame. The cable is disposed in the cable management groove. The display panel is disposed on the frame and located in the display opening, wherein an edge portion of the display panel is located on the support surface, and the support surface supports the edge portion of the display panel. A part of the cable management groove is located under the display panel and at least partially overlapped with the edge portion. | 04-30-2015 |
20150185408 | PROTECTIVE COVER - A protective cover is adapted to cover a display region of a mobile electronic device. The protective cover includes a fixed side, a movable side, and a flexible portion connecting the fixed side and the movable side. The fixed side is adapted to detachably fix the mobile electronic device. The movable side is adapted to cover the display region and has a transparent plate and a light source device. The transparent plate has a first surface, a second surface opposite to the first surface, and at least one light incident surface capable of connecting the first and second surfaces. The light source device is disposed adjacent to the light incident surface. Light generated from the light source device enters the transparent plate and then reaches the display region through the first surface of the transparent plate. The display region receives the light and displays an image through the transparent plate. | 07-02-2015 |
Patent application number | Description | Published |
20110115077 | Method for Reducing Voids in a Copper-Tin Interface and Structure Formed Thereby - An embodiment is a method for forming a semiconductor assembly comprising cleaning a connector comprising copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector. | 05-19-2011 |
20110186989 | Semiconductor Device and Bump Formation Process - A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump. | 08-04-2011 |
20120211547 | In-Situ Accuracy Control in Flux Dipping - A flux dipping apparatus includes a flux plate having a top surface; and a dipping cavity in the flux plate and recessed from the top surface. A flux leveler is disposed over the flux plate and configured to move parallel to the top surface. A piezoelectric actuator is configured to adjust a distance between the flux leveler and the top surface in response to a controlling voltage applied to electrodes of the first piezoelectric actuator. | 08-23-2012 |
20120227886 | Substrate Assembly Carrier Using Electrostatic Force - A portable electrostatic chuck carrier includes a holder having a dielectric top surface, and bipolar electrodes under the dielectric top surface. The bipolar electrodes includes positive electrodes and negative electrodes electrically insulated from the positive electrodes. The positive electrodes and the negative electrodes are allocated in an alternating pattern in a plane substantially parallel to the dielectric top surface. | 09-13-2012 |
20130048027 | Package Assembly Cleaning Process Using Vaporized Solvent - A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly. | 02-28-2013 |
20130115752 | Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops | 05-09-2013 |
20130167373 | Methods for Stud Bump Formation and Apparatus for Performing the Same - An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump. | 07-04-2013 |
20130175683 | Semiconductor Device And Bump Formation Process - A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump. | 07-11-2013 |
20140030849 | Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops | 01-30-2014 |
20140061153 | Methods for Forming Apparatus for Stud Bump Formation - An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface. | 03-06-2014 |
20140131863 | Semiconductor Device with Copper-Tin Compound on Copper Connector - An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector. | 05-15-2014 |
20140262470 | Metal Post Bonding Using Pre-Fabricated Metal Posts - A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad. | 09-18-2014 |
20140263583 | Two-Step Direct Bonding Processes and Tools for Performing the Same - A method includes placing a plurality of first package components over second package components, which are included in a third package component. First metal connectors in the first package components are aligned to respective second metal connectors of the second package components. After the plurality of first package components is placed, a metal-to-metal bonding is performed to bond the first metal connectors to the second metal connectors. | 09-18-2014 |
20150102091 | Methods for Forming Apparatus for Stud Bump Formation - An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface. | 04-16-2015 |