Patent application number | Description | Published |
20110016141 | Web Traffic Analysis Tool - A log file may include a line corresponding to a request received at a web server. A rules file may include rules that are applied in a specified order. The rules may include a first rule associated with a first request identifier and a second rule associated with a second request identifier. A determination is made as to whether the line matches the first rule. If the line matches the first rule, then identification data is updated to associate the first request identifier with the line. If the line does not match the first rule, then a determination is made as to whether the line matches the second rule. If the line matches the second rule, then the identification data is updated to associate the second request identifier with the line. If the line does not match the second rule, additional rules in the rules may be similarly applied | 01-20-2011 |
20120084433 | WEB TEST GENERATION - Technologies are described herein for generating a suite of web tests that are then combined into a load test. A log file is received. The log file may contain one or more requests received at a web server. Relevant information is extracted from the log file into a data file. A web test template is retrieved. The web test template is populated with the relevant information from the data file to generate the web test. | 04-05-2012 |
20120101998 | UPGRADE OF HIGHLY AVAILABLE FARM SERVER GROUPS - A machine manager controls the deployment and management of machines (physical and virtual) for an online service. Multi-tier server groups are arranged in farms that each may include different configurations. For example, their may be content farms, federated services farms and SQL farms that are arranged to perform operations for the online service. When the multiple farms are upgraded, new farms are deployed and the associated content databases from the old farms are moved to the newly deployed farms. During the upgrade of the farms, requests may continue to be processed by the farms. The farms may be automatically load balanced during an upgrade. As content becomes available on the new farm, requests for the content may be automatically redirected to the new farm. | 04-26-2012 |
20120102480 | HIGH AVAILABILITY OF MACHINES DURING PATCHING - A cloud manager is utilized in the patching of physical machines and virtual machines that are used within an online service, such as an online content management service. The cloud manager assists in the scheduling of the application of software patches to the machines (physical and virtual) within the network such that the availability of the online service is maintained while machines are being patched. The machines to be patched are partitioned into groups that are patched at different times. Generally, the groups are partitioned into a highly available independent groups of machines such that one or more of the groups that are not currently being patched continue to provide the service(s) of the group that is being patched. The machines (physical and virtual) within each of the groups may be patched in parallel. | 04-26-2012 |
20120102484 | INSTALLING SOFTWARE REMOTELY USING A HIGH PRIVILEGE PROCESS - Software that would not normally be able to be installed on a machine through a remote process is installed by a high privilege installer running on the machine. A request is received from a remote machine to install software on the machine using the high privilege installer. The high privilege installer determines when software that was requested remotely is to be installed. For example, the high privilege installer may monitor an install queue for software to be installed. When there are entries in the install queue, the high privilege installer is used to install the software. When there are no entries in the install queue, the high privilege installer may sleep until there is more software that is identified to be installed. | 04-26-2012 |
20120102494 | MANAGING NETWORKS AND MACHINES FOR AN ONLINE SERVICE - A cloud manager assists in deploying and managing networks for an online service. The cloud manager system receives requests to perform operations relating to configuring, updating and performing tasks in networks that are used in providing the online service. The management of the assets may comprise deploying machines, updating machines, removing machines, performing configuration changes on servers, Virtual Machines (VMs), as well as performing other tasks relating to the management. The cloud manager is configured to receive requests through an idempotent and asynchronous application programming interface (API) that can not rely on a reliable network. | 04-26-2012 |
20120102506 | WEB SERVICE PATTERNS FOR GLOBALLY DISTRIBUTED SERVICE FABRIC - An idempotent and asynchronous application programming interface (API) that can not rely on a reliable network is used by a cloud manager to receive and process requests. The cloud manager system is a central coordination service that receives requests using the API to perform update operations and get operations relating to the online service. For example, the API includes methods for deploying machines, updating machines, removing machines, performing configuration changes on servers, Virtual Machines (VMs), as well as performing other tasks relating to the management of the online service. Receiving and processing a same API call multiple times results in a same result. | 04-26-2012 |
20130124481 | UPGRADE OF HIGHLY AVAILABLE FARM SERVER GROUPS - A machine manager controls the deployment and management of machines (physical and virtual) for an online service. Multi-tier server groups are arranged in farms that each may include different configurations. For example, their may be content farms, federated services farms and SQL farms that are arranged to perform operations for the online service. When the multiple farms are upgraded, new farms are deployed and the associated content databases from the old farms are moved to the newly deployed farms. During the upgrade of the farms, requests may continue to be processed by the farms. The farms may be automatically load balanced during an upgrade. As content becomes available on the new farm, requests for the content may be automatically redirected to the new farm. | 05-16-2013 |
20140337502 | MANAGING NETWORKS AND MACHINES FOR AN ONLINE SERVICE - A cloud manager assists in deploying and managing networks for an online service. The cloud manager system receives requests to perform operations relating to configuring, updating and performing tasks in networks that are used in providing the online service. The management of the assets may comprise deploying machines, updating machines, removing machines, performing configuration changes on servers, Virtual Machines (VMs), as well as performing other tasks relating to the management. The cloud manager is configured to receive requests through an idempotent and asynchronous application programming interface (API) that can not rely on a reliable network. | 11-13-2014 |
20150074546 | IN-APPLICATION CUSTOMIZATION - In-application customization is provided where users can both use and customize the application. Within a graphical user interface of an application developed by an original author, an interaction from a customizer user of the application can be received to make a modification to the application from a set of available modifications that the original author did not create for the application. The modification can be performed using functionality made available through a developer program service. | 03-12-2015 |
Patent application number | Description | Published |
20090310185 | CREDENTIAL AND METHOD AND SYSTEM OF MAKING SAME - A batch of credentials printed on a credential medium having a pattern of lenses (e.g., lenticular or other pattern), as well as a system and method for producing such credentials. A library of encoders is used to encode pixel locations of a plurality of view sets comprising a number of individual image frames. Each view set is associated with a distinct region on a credential having distinct polyoptic properties (e.g., orientation, frequency, shape). Encoded images produced by the library of encoders are combined (e.g., by interlacing or other encoding pattern) into a single print-ready image that is aligned (e.g., registered) with lenses of the distinct polyoptic areas on a medium on which the credential is printed. Encoding may take the form of positioning, sizing, intensifying, coloring, masking, interlacing, interleaving, scrambling, mixing, transformation, alteration, translation of pixels, or a combination thereof. | 12-17-2009 |
20100033739 | CUSTOMIZED CREDENTIAL AND METHOD AND SYSTEM OF PRODUCTION - A batch of individualized credentials, e.g., ID tags, event tickets, etc., taken from a credential medium that includes respective polyoptic regions each carrying an encoded image set associated with respective individualized credentials, as well as a system and a method or producing the same. The production process uses credential data retrieved from a data store to create a plurality of individualized credentials on a single sheet medium. The dynamic production process enables inclusion of variable customer or patronage data, or individual object data (e.g., a serial number or object characteristic) on individual credentials using a template file that identifies a type of data to be retrieved from the data store and/or a specified image generated according to the value, nature, or type of the individualized data. Encoding of images may take the form of positioning, sizing, intensity, color, masking, interlacing, interleaving, scrambling, mixing, transformation, alteration, translation of pixels of images of multiple images. | 02-11-2010 |
20100046022 | MARKET-SPECIFIC CREDENTIAL AND SYSTEM AND METHOD FOR MAKING SAME - A batch of printed credentials each including a polyoptic region including a respective image separately determined during production according to biographic or other information unique to the credential holder, as well as system and a method for producing such credentials. The respective images of the credentials in the batch may convey targeted marketing information. The production process uses credential data retrieved from a data store to print the plurality of customized credentials on a single medium where each credential on the single medium includes an image field based on dynamic data relationships of retrieved credential data. | 02-25-2010 |
Patent application number | Description | Published |
20100278061 | CINR FORMULA FOR SPATIAL MULTIPLEXING - A method for calculating channel quality in a multi-stream communication system, by calculating channel quality for each selectable stream of the multi-stream communication system, based on estimation of at lest one set of error vectors. | 11-04-2010 |
20110019573 | LOW COMPLEXITY USER SELECTION FOR SDMA - A method for grouping terminal devices in a wireless communication network containing a base-station, wherein each terminal reports to the base-station the level of signal received the terminal when the base-station transmits to another terminal or terminals. The base-station then selects from the plurality of the terminals, groups of terminals indicating low signal measurements for data transmissions sent to other group members of the group. | 01-27-2011 |
20110038272 | GENERALIZED EESM SYSTEM AND METHOD - A method for computing ECINR in communication systems, by calculating or measuring instantaneously CINR (yi) or per-tone CINR value for each channel and/or bandwidth and/or signal of interest, selecting κ and β parameters according to MCS and/or FEC block size used, calculating ECINR by using the CINR ((yi) or per-tone CINR values and the κ and β parameters with a generalized EESM formula, and providing a communication system with the updated γeff which is the ECINR value. | 02-17-2011 |
20110044356 | SYSTEM AND METHOD FOR MODE SELECTION BASED ON EFFECTIVE CINR - Selecting an optimal ECINR mode in a digital communication system, by constructing an offline relevant modes database having a list of transmission-reception methods for possible MIMO configurations, and mobility characterization, gathering online channel state and capabilities information, retrieving parameters from the relevant modes database, based on the gathered data/information for creating a concurrent list, excluding some MIMO modes off the list, for which the available channel matrix is insufficient, the modes left at the end of this step being “currently relevant modes’, calculating post processing per tome physical CINR (PCINR) for each of the currently relevant modes found, calculating ECINR for each of the currently relevant modes using the PCINR, choosing the optimal MIMO mode and MCS combination, which is the parameters' combination with highest throughput, which provide the best ECINR under QoS requirements. | 02-24-2011 |
20110069785 | System and Method for Low Complexity Sphere Decoding for Spatial Multiplexing MIMO - In this application, an algorithm for decoding multiple input-multiple output (MIMO) transmission for communication systems is provided; the algorithm combines sphere decoding (SD) and zero forcing (ZF) techniques to provide near optimal low complexity and high performance constant time modified sphere decoding algorithm; this algorithm was designed especially for large number of transmit antennas, that allows efficient implementation in hardware—this is done by limiting the number of overall SD iterations; moreover, we make sure that matrices with high condition number are more likely to undergo SD. | 03-24-2011 |
Patent application number | Description | Published |
20110275949 | MULTI-ELECTRODE MAPPING SYSTEM - In some aspects, a method includes measuring unipolar signals at one or more electrodes in response to electrical activity in a heart cavity. The method also includes determining, based at least in part on Laplace's equation, bipolar physiological information at multiple locations of an surface based on the measured unipolar signals and positions of the one or more electrodes with respect to the surface. | 11-10-2011 |
20120078077 | CARDIAC MAPPING CATHETER - A multi electrode catheter for non contact mapping of the heart having independent articulation and deployment features. | 03-29-2012 |
20120143030 | TRACKING SYSTEM USING FIELD MAPPING - In some aspects, a method includes (i) securing multiple sets of current injecting electrodes to an organ in a patient's body, (ii) causing current to flow among the multiple sets of current injecting electrodes to generate a field in the organ, (iii) in response to current flow caused by the multiple sets of current injecting electrodes, measuring the field at each of one or more additional electrodes, (iv) determining expected signal measurements of the field inside the organ using a pre-determined model of the field, and (v) determining a position of each of the one or more additional electrodes in the organ based on the measurements made by the additional electrodes and the determined expected signal measurements of the field. | 06-07-2012 |
20120184858 | BEAT ALIGNMENT AND SELECTION FOR CARDIAC MAPPING - This invention relates to the determination and/or representation of physiological information relating to a heart surface. | 07-19-2012 |
20120184863 | ELECTROANATOMICAL MAPPING - This invention relates to the determination and/or representation of physiological information relating to a heart surface. | 07-19-2012 |
20120184864 | ELECTROANATOMICAL MAPPING - This invention relates to the determination and/or representation of physiological information relating to a heart surface. | 07-19-2012 |
20120184865 | ELECTROANATOMICAL MAPPING - This invention relates to the determination and/or representation of physiological information relating to a heart surface. | 07-19-2012 |
20120253161 | IMPEDANCE BASED ANATOMY GENERATION - Methods and systems for the determination and representation of anatomy anatomical information are disclosed herein. | 10-04-2012 |
20120277567 | INTRA-CARDIAC TRACKING SYSTEM - In general, in one aspect, a method is disclosed for determining information about a position of an object. The method includes: (i) causing current to flow between each of three or more sets of current-injecting electrodes on a first catheter inserted into an organ in a patient's body, the organ having a periphery (ii) in response to current flow caused by each set of current injecting electrodes, measuring an electrical signal at each of one or more measuring electrodes located on one or more additional catheters inserted into the organ in the patient's body and (iii) determining the position of each of one or more of the measuring electrodes on the additional catheters relative to the first catheter based on the measured signals from the one or more measuring electrodes. | 11-01-2012 |
20130109945 | ELECTROANATOMICAL MAPPING | 05-02-2013 |
20130253298 | CARDIAC MAPPING CATHETER - A multi electrode catheter for non contact mapping of the heart having independent articulation and deployment features. | 09-26-2013 |
20130261483 | CARDIAC MAPPING - A non-contact cardiac mapping method is disclosed that includes: (i) inserting a catheter into a heart cavity having an endocardium surface, the catheter including multiple, spatially distributed electrodes; (ii) measuring signals at the catheter electrodes in response to electrical activity in the heart cavity with the catheter spaced from the endocardium surface; and (iii) determining physiological information at multiple locations of the endocardium surface based on the measured signals and positions of the electrodes with respect to the endocardium surface. Related systems and computer programs are also disclosed. | 10-03-2013 |
20130345538 | Intracardiac Tracking System - In general, in one aspect, a method is disclosed for determining information about a position of an object. The method includes: (i) causing current to flow between each of three or more sets of current-injecting electrodes on a first catheter inserted into an organ in a patient's body, the organ having a periphery (ii) in response to current flow caused by each set of current injecting electrodes, measuring an electrical signal at each of one or more measuring electrodes located on one or more additional catheters inserted into the organ in the patient's body and (iii) determining the position of each of one or more of the measuring electrodes on the additional catheters relative to the first catheter based on the measured signals from the one or more measuring electrodes. | 12-26-2013 |
20140024911 | TRACKING SYSTEM USING FIELD MAPPING - In some aspects, a method includes (i) securing multiple sets of current injecting electrodes to an organ in a patient's body, (ii) causing current to flow among the multiple sets of current injecting electrodes to generate a field in the organ, (iii) in response to current flow caused by the multiple sets of current injecting electrodes, measuring the field at each of one or more additional electrodes, (iv) determining expected signal measurements of the field inside the organ using a pre-determined model of the field, and (v) determining a position of each of the one or more additional electrodes in the organ based on the measurements made by the additional electrodes and the determined expected signal measurements of the field. | 01-23-2014 |
20140107508 | ELECTRODE DISPLACEMENT DETERMINATION - Methods and systems for determining whether a location of multiple current injecting electrodes has changed are disclosed herein. | 04-17-2014 |
20140200442 | Intracardiac Tracking System - In general, in one aspect, a method is disclosed for determining information about a position of an object. The method includes: (i) causing current to flow between each of three or more sets of current-injecting electrodes on a first catheter inserted into an organ in a patient's body, the organ having a periphery (ii) in response to current flow caused by each set of current injecting electrodes, measuring an electrical signal at each of one or more measuring electrodes located on one or more additional catheters inserted into the organ in the patient's body and (iii) determining the position of each of one or more of the measuring electrodes on the additional catheters relative to the first catheter based on the measured signals from the one or more measuring electrodes. | 07-17-2014 |
20140235986 | IMPEDANCE BASED ANATOMY GENERATION - Methods and systems for the determination and representation of anatomy anatomical information are disclosed herein. | 08-21-2014 |
20140275921 | CARDIAC MAPPING CATHETER - A multi electrode catheter for non contact mapping of the heart having independent articulation and deployment features. | 09-18-2014 |
Patent application number | Description | Published |
20090324026 | SYSTEM AND METHOD FOR FINDING A PICTURE IMAGE IN AN IMAGE COLLECTION USING LOCALIZED TWO-DIMENSIONAL VISUAL FINGERPRINTS - An image management method and system provides for storing, indexing, searching and/or retrieving image data. The content of an image collection is pre-processed to identify stable and repeatable keypoints for each image in the collection. Fingerprint information is computed from local groups of keypoints, and the resulting fingerprint information is stored in a compact fingerprint database. The computing of the fingerprint information is based on combinations of a subgroup of the strongest keypoints in an image, called anchor keypoints, in addition to a number of non-anchor keypoints. For each fingerprint in the compact fingerprint database, a sequence of candidate fingerprint combinations is generated and stored in a Fan Tree and/or hashtable and a corresponding fingerprint data structure. The sequence of fingerprint combinations allows several non-anchor keypoints to be missing, while still allowing the system and method to correctly detect fingerprints with high accuracy. A realtime image query is performed by identifying keypoints and computing fingerprints from the query image and matching the query fingerprints to the existing Fan Tree and/or hashtable fingerprint data to determine the best matching image or set of images within the collection. At least one target image is retrieved based on the determining operation, and the retrieved target image is displayed, printed, stored and/or transmitted. | 12-31-2009 |
20090324087 | SYSTEM AND METHOD FOR FINDING STABLE KEYPOINTS IN A PICTURE IMAGE USING LOCALIZED SCALE SPACE PROPERTIES - A method and system is provided for finding stable keypoints in a picture image using localized scale properties. An integral image of an input image is calculated. Then a scale space pyramid layer representation of the input image is constructed at mulitple scales, wherein at each scale, a set of specific filters are applied to the input image to produce an approximation of at least a portion of the input image. Outputs from filters are combined together to form a single function of scale and space. Stable keypoint locations are identified in each scale at pixel locations at which the single function attains a local peak value. The stable keypoint locations which have been identified are then stored in a memory storage. | 12-31-2009 |
20090324100 | METHOD AND SYSTEM FOR FINDING A DOCUMENT IMAGE IN A DOCUMENT COLLECTION USING LOCALIZED TWO-DIMENSIONAL VISUAL FINGERPRINTS - An image management method and system provides for storing, indexing, searching, and/or retrieving image data. Keypoints are identified in images, including keypoints in a query image of a query document, and keypoints in potential target document images of a collection of potential target documents. Fingerprint information from the keypoints are generated, and the fingerprint information of a query image is compared with fingerprint information of potential target document images, found in the collection of potential target documents. A best match is determined between the fingerprint information of the query image and the potential target document images. At least one target document image is retrieved based on the determined best match. The retrieved at least one target image may then be displayed, printed or transmitted. | 12-31-2009 |
20110052015 | METHOD AND APPARATUS FOR NAVIGATING AN ELECTRONIC MAGNIFIER OVER A TARGET DOCUMENT - A method for electronically magnifying a target object with an imaging device. The method includes obtaining a full view image of the target object, where the full view image is focused. The method further includes moving the imaging device in proximity to a portion of the target object and obtaining a key image of the portion of the target object. The method further includes matching the key image to a corresponding portion of the full view image. The method further includes magnifying the corresponding portion of the full view image and displaying the magnified portion of the full view image. | 03-03-2011 |
20110194736 | FINE-GRAINED VISUAL DOCUMENT FINGERPRINTING FOR ACCURATE DOCUMENT COMPARISON AND RETRIEVAL - A method and system generates fine-grained fingerprints for identifying content in a rendered document. It includes applying image-based techniques to identify patterns in a document rendered by an electronic document rendering system, irrespective of a file format in which the rendered document was electronically created. The applying of the image-based technique includes identifying candidate keypoints at locations in a local image neighborhood of the document, and combining the locations of the candidate keypoints to form a fine-grained fingerprint identifying patterns representing content in the document. | 08-11-2011 |
20110197121 | EFFECTIVE SYSTEM AND METHOD FOR VISUAL DOCUMENT COMPARISON USING LOCALIZED TWO-DIMENSIONAL VISUAL FINGERPRINTS - A method and system detects and highlights changes in documents and displays those documents in a side-by-side aligned view. Aspects of a source document and a revised document are detected and compared. Similarities and/or differences between the source document and the revised document are identified and visual identifiers are introduced to maintain consistent and accurate alignment between content in the source document and content in the revised document. A merged single file is output containing the aligned side-by-side view of the source document and the revised document, with all differences between the source document and the revised document visually identified. | 08-11-2011 |
20110316845 | SPATIAL ASSOCIATION BETWEEN VIRTUAL AND AUGMENTED REALITY - One embodiment of the present invention provides a system that facilitates interaction between two entities located away from each other. The system includes a virtual reality system, an augmented reality system, and an object-state-maintaining mechanism. During operation, the virtual reality system displays an object associated with a real-world object. The augmented reality system displays the object based on a change to the state of the object. The object-state-maintaining mechanism determines the state of the object and communicates a state change to the virtual reality system, the augmented reality system, or both. A respective state change of the object can be based on one or more of: a state change of the real-world object; a user input to the virtual reality system or the augmented reality system; and an analysis of an image of the real-world object. | 12-29-2011 |
20120093354 | FINDING SIMILAR CONTENT IN A MIXED COLLECTION OF PRESENTATION AND RICH DOCUMENT CONTENT USING TWO-DIMENSIONAL VISUAL FINGERPRINTS - Visual fingerprinting is used to provide a robust and highly effective method of finding similar content in a large document collection of rich document content composed of multiple text, line-art, and photo image objects. The visual fingerprints capture unique two-dimensional localized aspects of document appearance. The visual fingerprints are highly distinctive; fast for lookup; compact for storage requirements; and scalable to large document collections. | 04-19-2012 |
20120093421 | DETECTION OF DUPLICATE DOCUMENT CONTENT USING TWO-DIMENSIONAL VISUAL FINGERPRINTING - A system and method of detecting duplicate document content in a large document collection and automatically highlighting duplicate or different document content among the detected document content using two-dimensional visual fingerprints. | 04-19-2012 |
20130325970 | COLLABORATIVE VIDEO APPLICATION FOR REMOTE SERVICING - One embodiment of the present invention provides a system for sharing annotated videos. During operation, the system establishes a real-time video-sharing session between a remote field computer and a local computer. During the established real-time video-sharing session, the system receives a real-time video stream from a remote field computer, forwards the real-time video stream to a local computer to allow an expert to provide an annotation to the real-time video stream, receives the annotation from the local computer, and forwards the annotation to the remote field computer, which associates the annotation with a corresponding portion of the real-time video stream and displays the annotation on top of the corresponding portion of the real-time video stream. | 12-05-2013 |
20140016820 | DISTRIBUTED OBJECT TRACKING FOR AUGMENTED REALITY APPLICATION - One embodiment of the present invention provides a system for tracking and distributing annotations for a video stream. During operation, the system receives, at an annotation server, the video stream originating from a remote field computer, extracts a number of features from the received video stream, and identifies a group of features that matches a known feature group, which is associated with an annotation. The system further associates the identified group of features with the annotation, and forwards the identified group of features and the annotation to the remote field computer, thereby facilitating the remote field computer to associate the annotation with a group of locally extracted features and display the video stream with the annotation placed in a location based at least on locations of the locally extracted features. | 01-16-2014 |
Patent application number | Description | Published |
20090021749 | HIGH THROUGHPUT ACROSS-WAFER-VARIATION MAPPING - A method for characterizing a surface of a sample object, the method including dividing the surface into pixels which are characterized by a parameter variation, and defining blocks of the surface as respective groups of the pixels. The method further includes irradiating the pixels in multiple scans over the surface with radiation having different, respective types of polarization, and detecting returning radiation from the pixels in response to each of the scans. For each scan, respective block signatures of the blocks are constructed, in response to the returning radiation from the group of pixels in each block. Also for each scan, a block signature variation using the respective block signatures of the blocks is determined. In response to the block signature variation, one or more of the types of polarization for use in subsequent examination of a test object are selected. | 01-22-2009 |
20110158502 | MAPPING VARIATIONS OF A SURFACE - A method for characterizing a surface, consisting of dividing the surface into pixels which are characterized by a parameter variation and defining blocks of the surface as respective groups of the pixels. The pixels are irradiated in multiple scans over the surface with radiation having different first polarization states. At least part of the radiation returning from the pixels is analyzed using second polarization states, to generate processed returning radiation. For each scan, block signatures of the blocks are constructed using the processed returning radiation from the group of pixels in each block. Also for each scan, a block signature variation is determined using the respective block signatures of the blocks, and, in response to the block signature variation, one of the first polarization states and at least one of the second polarization states are selected for use in subsequent examination of a test object. | 06-30-2011 |
20130148114 | OPTICAL SYSTEM AND METHOD FOR INSPECTION OF PATTERNED SAMPLES - An optical inspection system for inspecting a patterned sample located in an inspection plane includes an illumination unit defining an illumination path, and a light collection unit defining a collection path, each path having a certain angular orientation with respect to the inspection plane. The illumination unit comprises an illumination mask located in a first spectral plane with respect to the inspection plane and the light collection unit comprises a collection mask located in a second spectral plane with respect to the inspection plane being conjugate to the first spectral plane. Arrangements of features of the first and second patterns are selected in accordance with a diffraction response from said patterned sample along a collection channel defined by the angular orientation of the illumination and collection paths. | 06-13-2013 |
20130148115 | OPTICAL SYSTEM AND METHOD FOR INSPECTION OF PATTERNED SAMPLES - An optical inspection system for inspecting a patterned sample located in an inspection plane includes an illumination unit defining an illumination channel of a predetermined numerical aperture and first predetermined angular orientation with respect to the inspection plane, and a light collection unit defining a collection channel of second predetermined angular orientation with respect to the inspection plane. The illumination unit comprises an illumination mask located in a first spectral plane with respect to the inspection plane and defining an illumination pupil comprising a first pattern formed by at least one elongated light transmitting region having a physical dimension along one axis larger than along a perpendicular axis. The light collection unit comprises a collection mask located in a second spectral plane with respect to the inspection plane being conjugate to the first spectral plane, the collection mask comprising a second predetermined pattern of spaced-apart light blocking regions. | 06-13-2013 |
Patent application number | Description | Published |
20080209172 | Selective hardware lock disabling - Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS. | 08-28-2008 |
20090172356 | COMPRESSED INSTRUCTION FORMAT - A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size. | 07-02-2009 |
20090172363 | MIXING INSTRUCTIONS WITH DIFFERENT REGISTER SIZES - When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers. | 07-02-2009 |
20090172365 | Instructions and logic to perform mask load and store operations - In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed. | 07-02-2009 |
20090172366 | Enabling permute operations with flexible zero control - In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed. | 07-02-2009 |
20100115014 | Instruction and logic for performing range detection - A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor. | 05-06-2010 |
20120331271 | COMPRESSED INSTRUCTION FORMAT - A technique for decoding an instruction in an a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size. | 12-27-2012 |
20130191615 | INSTRUCTIONS AND LOGIC TO PERFORM MASK LOAD AND STORE OPERATIONS - In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. Other embodiments are described and claimed. | 07-25-2013 |
Patent application number | Description | Published |
20080259804 | DEVICE AND METHODS FOR INCREASING WIRELESS CONNECTION SPEEDS - Various embodiments include wireless client device comprising an application subsystem including a processor and a storage device coupled to the processor, a communication subsystem coupled to the application subsystem, the communication subsystem including a media access control (MAC) device and a physical (PHY) device, wherein the physical device is operably coupled to the processor of the application subsystem, wherein the physical device is operable to receive a wireless signal, to analyze the wireless signal for at least one aspect of wireless performance, and to determine if the at least one aspect of wireless performance can be improved, wherein, if it is determined that the at least one aspect of wireless performance can be improved, the physical device is operable to pass the wireless signal to the processor of the application subsystem for processing of the wireless signal within the processor. | 10-23-2008 |
20090061760 | Reduced Cost Mobil Satellite Antenna System using a Plurality of Satellite Transponders - A system for utilizing circular polarized signals to perform satellite communication to mobile users. The satellite includes transponders, each transponder providing linearly polarized signals and at least two orthogonal linear polarized transponders. A plurality of mobile users with a circularly polarized antenna for receiving signals from the satellite, and singly circular or linear polarized transmit antennas for transmitting signals to the satellite. Circuits for providing a correction scheme implemented in a hub side to offset frequency error between two channels produced by the satellite transponder local oscillators mismatch. | 03-05-2009 |
20090098826 | VIRTUAL CONNECTOR BASED ON CONTACTLESS LINK - The today's mobile handheld and portable devices become slim and thin while need to communicate with other devices and accessories that are attached or at very short range. The interface (contact based physical connector) becomes a real challenge and unreliable to the consumer that needs to attached and detach its device several times a day. | 04-16-2009 |
20090262757 | VARIABLE BIT RATE COMMUNICATION SYSTEM - A method for communication over a communication channel includes processing input data, which is accepted at a first variable bit rate, so as to produce output data that is encoded with a Forward Error Correction (FEC) code and has a second bit rate that matches an available bit rate of the communication channel. The output data is transmitted over the communication channel at the available bit rate. The output data is received from the communication channel and decoded so as to reconstruct the input data. | 10-22-2009 |
20120204076 | Broadcasting of digital video to mobile terminals - A method for communication includes encoding data using at least one Error Correction Code (ECC) to generate first and second output data streams. The first output data stream is processed to generate a first output signal, which has a first acquisition time. The second output data stream is processed to generate a second output signal, which has a second acquisition time that is smaller than the first acquisition time. The first and second output signals are transmitted simultaneously over a communication channel. | 08-09-2012 |
Patent application number | Description | Published |
20100083009 | POWER MANAGEMENT FOR PROCESSING UNIT - Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed. | 04-01-2010 |
20100115293 | DETERMINISTIC MANAGEMENT OF DYNAMIC THERMAL RESPONSE OF PROCESSORS - Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed. | 05-06-2010 |
20100115304 | POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES - Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed. | 05-06-2010 |
20100146314 | Power aware software pipelining for hardware accelerators - Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings. | 06-10-2010 |
20100169609 | Method for optimizing voltage-frequency setup in multi-core processor systems - A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode. | 07-01-2010 |
20110154011 | METHODS, SYSTEMS, AND APPARATUSES TO FACILITATE CONFIGURATION OF A HARDWARE DEVICE IN A PLATFORM - Embodiments of methods, systems, and apparatuses for configuring a hardware device in a platform are described. In an exemplary method, a configuration message is received that indicates that the hardware device is to be upgraded from a first configuration to a second configuration, wherein the first and second configurations were pre-determined based on previous testing of the hardware device and are stored in the hardware device. The hardware device is then configured to the second configuration. | 06-23-2011 |
20120166854 | Controlling Current Transients In A Processor - In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed. | 06-28-2012 |
20120221873 | Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices - According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device. | 08-30-2012 |
20130061064 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 03-07-2013 |
20130080803 | Estimating Temperature Of A Processor Core In A Low Power State - In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed. | 03-28-2013 |
20130080804 | Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed. | 03-28-2013 |
20130111120 | Enabling A Non-Core Domain To Control Memory Bandwidth | 05-02-2013 |
20130111121 | Dynamically Controlling Cache Size To Maximize Energy Efficiency | 05-02-2013 |
20130111226 | Controlling A Turbo Mode Frequency Of A Processor | 05-02-2013 |
20130111236 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor | 05-02-2013 |
20130173941 | Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed. | 07-04-2013 |
20130173946 | CONTROLLING POWER CONSUMPTION THROUGH MULTIPLE POWER LIMITS OVER MULTIPLE TIME INTERVALS - Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed. | 07-04-2013 |
20130179704 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 07-11-2013 |
20130179705 | Controlling A Turbo Mode Frequency Of A Processor - In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed. | 07-11-2013 |
20130179709 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed. | 07-11-2013 |
20130219196 | POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES - Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed. | 08-22-2013 |
20140115351 | DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 04-24-2014 |
20140258760 | Controlling Operating Voltage Of A Processor - In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed. | 09-11-2014 |
20140344598 | Enabling A Non-Core Domain To Control Memory Bandwidth - In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed. | 11-20-2014 |
Patent application number | Description | Published |
20100049954 | METHOD FOR SPECULATIVE EXECUTION OF INSTRUCTIONS AND A DEVICE HAVING SPECULATIVE EXECUTION CAPABILITIES - A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends. | 02-25-2010 |
20100049958 | METHOD FOR EXECUTING AN INSTRUCTION LOOPS AND A DEVICE HAVING INSTRUCTION LOOP EXECUTION CAPABILITIES - A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit. | 02-25-2010 |
20130290686 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR CALCULATING A PREDICATE VALUE - An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value. | 10-31-2013 |
20130326200 | INTEGRATED CIRCUIT DEVICES AND METHODS FOR SCHEDULING AND EXECUTING A RESTRICTED LOAD OPERATION - An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register. | 12-05-2013 |
20140019990 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ENABLING CROSS-CONTEXT ACCESS - An integrated circuit device comprising an instruction processing module for performing operations on data in accordance with received instructions. The instruction processing module comprises a context selector unit arranged to selectively provide access to at least one process attribute(s) within a plurality of process contexts in accordance with at least one context selector value received thereby. The instruction processing module is arranged to receive an instruction comprising a context indication for a process attribute with which an operation is to be performed, provide the context selector value based at least partly on the context indication to the context selector unit, and execute the operation to be performed with the process attribute for at least one process context to which the context selector unit provides access in accordance with the context selector value. | 01-16-2014 |
20150032929 | CIRCUITRY FOR A COMPUTING SYSTEM, LSU ARRANGEMENT AND MEMORY ARRANGEMENT AS WELL AS COMPUTING SYSTEM - A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus. | 01-29-2015 |
Patent application number | Description | Published |
20090064178 | MULTIPLE, COOPERATING OPERATING SYSTEMS (OS) PLATFORM SYSTEM AND METHOD - A multiple, cooperating operating systems (OS) platform system with multi processors. Multiple operating systems, each of which may be of a different type or nature, can run on different partitions of the multi-processor platform and yet coexist and cooperate. A real time operating system (RTOS) executing on a processor can communicate with another OS executing on another processor via a portion of memory accessible by the RTOS and the OS by perform read and write operations. | 03-05-2009 |
20100333077 | Apparatus, Method, and Software for Analyzing Network Traffic in a Service Aware Network - The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided. | 12-30-2010 |
20110161703 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-30-2011 |
20110173367 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 07-14-2011 |
20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-29-2011 |
20120036293 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 02-09-2012 |
20120089750 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-12-2012 |
20130091317 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-11-2013 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-18-2013 |
20130111086 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS | 05-02-2013 |
20130132622 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132636 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132683 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |