Patent application number | Description | Published |
20100123792 | IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD AND PROGRAM - An image processing device, which includes: super-resolution processing executing section which inputs a low-resolution image and a super-resolution image and generates a difference image which represents a difference between the input images; and an adding section which adds the difference image and the super-resolution image, wherein super-resolution processing executing section includes a motion vector detecting section which detects a object-based motion vector which represents a motion between images of an object commonly included in the low-resolution image and the super-resolution image on an object basis, and generates the difference image using a motion-compensated image generated by applying the detected object-based motion vector to each object area. | 05-20-2010 |
20100157072 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM - An image processing apparatus includes: a section that detects a local motion vector for each block forming an image from a standard image and a reference image; a section that executes motion compensation on the reference image employing the local motion vector to generate a local motion-compensated image; a section that calculates a single global motion vector for the entire standard image and the entire reference image employing the local motion vector and that executes motion compensation on the reference image employing the global motion vector to generate a global motion-compensated image; and a section that calculates respective reliabilities of the local motion-compensated image and the global motion-compensated image in units of image regions and that executes a process to synthesize pixel values of the local motion-compensated image and pixel values of the global motion-compensated image in accordance with the reliabilities to generate a blended motion-compensated image. | 06-24-2010 |
20100157073 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM - An image processing apparatus includes a motion prediction processor configured to detect a motion vector that indicates inter-image motion between a current image and a reference image; a motion compensation processor configured to perform a motion compensation process for the reference image by using the motion vector and generate a motion compensated image; an addition processor configured to generate a noise reduced image in which noise of the current image is reduced by adding the current image and the motion compensated image; an addition determination unit configured to compute an addition weight in units of pixels of the motion compensated image; a down-sampling processor configured to perform a process for reducing the current image and the motion compensated image; and an up-sampling processor configured to perform a process for expanding an addition coefficient map that is an output of the addition determination unit. | 06-24-2010 |
20110194607 | Information Processing Device, Information Processing Method, and Program - An information processing device includes a bit conversion unit that performs reduction in a bit number allocated to a pixel for a criterion image and a reference image and generates a criterion image and a reference image which are hierarchized according to a bit number allocated to a pixel, and a motion vector detection unit that performs coarse detection of a motion vector by block matching using the criterion image and the reference image of which a bit number is reduced, decides a search range for fine detection of a motion vector based on the motion vector detected by the coarse detection, and performs fine detection of a motion vector using an image in the search range which belongs to a hierarchy equal to or more than an image used in the coarse detection in a bit number allocated to a pixel. | 08-11-2011 |
20110235942 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM - An image processing apparatus includes: a motion prediction processing unit detecting an inter-image motion between a standard image and a reference image; a motion compensation processing unit generating a motion-compensated image by moving the reference image so as to be aligned with the standard image in a pixel position; an addition processing unit generating a noise-reduced image from which noise of the standard image is reduced; and an addition determination unit calculating an addition weight of the motion-compensated image. The addition determination unit includes a first motion region detection unit calculating a motion region determination value, a second motion region detection unit calculating a motion region determination value, a control map generation unit selecting and outputting one of two motion region determination values, a noise determination table generation unit generating or correcting a noise determination table, and an addition determination processing execution unit determining the addition weight. | 09-29-2011 |
20110274368 | IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM - An image processing device includes: an upsampling section; a motion compensated image generating section; a blend processing section; and an output image generating section. | 11-10-2011 |
20110274370 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD AND IMAGE PROCESSING PROGRAM - Disclosed herein is an image processing apparatus including an up-sampling section configured to carry out up-sampling processing in order to generate an up-sampled image, a motion-compensated image generation section configured to generate a motion-compensated image as a result of correction processing to adjust a referenced image having the second resolution to a photographing-object position on the up-sampled image by making use of information on a difference between the up-sampled image and the referenced image, a blending processing section configured to generate a blended image as a result of blending processing to blend the up-sampled image with the referenced image, and an output-image generation section configured to receive and process the blended image as well as the up-sampled image in order to generate an output blended image obtained by blending a super-resolution processing-result image with a noise-reduction processing-result image. | 11-10-2011 |
20120269451 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM - There is provided an apparatus including: a low-bit criterion image generation unit that reduces a bit number assigned to a pixel in a criterion image and generates low-bit criterion image data; a low bit reference image generation unit that reduces a bit number of a reference mage and generates low-bit reference image data; and a motion vector information generation unit that detects a block-unit local motion vector from the low-bit criterion/reference images and calculates reliability of the detected local motion vector. By reducing the image bit number, it is possible to detect a local motion vector in a simple configuration. By calculating a global motion vector using a local motion vector according to reliability, even if a local motion vector is detected from an image of the reduced bit number, it is possible to calculate a global motion vector at higher accuracy. | 10-25-2012 |
20120328208 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, PROGRAM, AND RECORDING MEDIUM - Provided is an information processing apparatus including a low-bit basic image generating part for generating a low-bit basic image having a low bit depth, a low-bit reference image generating part for generating a low-bit reference image having a low bit depth, a feature value calculating part for calculating a feature value indicating a non-flatness of brightness information of the basic image, a cost value calculating part for calculating a cost value at each of reference block positions in a block matching between the low-bit basic image and the low-bit reference image using the feature value and an estimated motion vector, and a block matching part for calculating a motion vector at each of the reference block positions based on an evaluation value obtained by the block matching between the low-bit basic image and the low-bit reference image after correcting the evaluation value using the calculated cost value. | 12-27-2012 |
20130011081 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, PROGRAM AND RECORDING MEDIUM - There is provided an image processing apparatus including a frequency separation unit that reduces an input image, restores the reduced input image to an image size before reduction, calculates a difference from the input image before reduction, and separates the input image into a reduced image and a difference image, an image processing unit that processes at least either one of the reduced image or the difference image, and a synthesizing processing unit that synthesizes the reduced image and the difference image, at least either one of which is image-processed, at a same image size. | 01-10-2013 |
20130084017 | IMAGE PROCESSING APPARATUS AND METHOD, PROGRAM AND RECORDING MEDIUM - An image processing apparatus includes a motion estimation processing section that detects a motion vector of block units which configure an image from a standard image and a reference image; a motion compensation processing section that produces a motion compensation image by performing motion compensation of the reference image using the motion vector; a difference calculation section that calculates a difference value between pixel values of a pixels of the standard image and pixel values of pixels of the motion compensation image; and a threshold value processing section that determines whether block noise is contained in the motion compensation image of a block unit or not by performing a threshold value processing on the difference value. | 04-04-2013 |
20130084024 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, PROGRAM, AND RECORDING MEDIUM - There is provided an image processing apparatus including a local-motion-compensation-processing unit which generates a local-motion-compensation image by detecting a local motion vector, which is a motion vector for each block forming an image, from a standard image and a reference image, and performing motion compensation on the reference image using the local motion vector, a global-motion-compensation-processing unit which generates a global-motion-compensation image by calculating a global motion vector, which is a motion vector for an entire image between the standard image and the reference image, using the local motion vector, and performing motion compensation on the reference image using the global motion vector, and a blend processing unit which generates a blend-motion-compensation image by combining a pixel value of a pixel in the local-motion-compensation image and a pixel value of a pixel in the global-motion-compensation image based on a noise intensity for a luminance value of an image. | 04-04-2013 |
20140086479 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, OUTPUT APPARATUS, OUTPUT METHOD, AND PROGRAM - There is provided a signal processing apparatus including a learning unit that learns a plurality of base signals of which coefficients become sparse, using a cost function including a term showing a correspondence between the coefficients, such that signals are represented by a linear operation of the plurality of base signals. | 03-27-2014 |
20140086480 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, OUTPUT APPARATUS, OUTPUT METHOD, AND PROGRAM - There is provided a signal processing apparatus including a learning unit that learns a plurality of base signals of which coefficients become sparse, for each of features of signals, such that the signals are represented by a linear operation of the plurality of base signals. | 03-27-2014 |
Patent application number | Description | Published |
20120139047 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device, comprising a substrate, a channel region in the substrate, source/drain regions on both sides of the channel region, a gate structure on the channel region, and gate sidewall spacers formed on the sidewalls of the gate structure, characterized in that each of the source/drain regions comprises an epitaxially grown metal silicide region, and dopant segregation regions are formed at the interfaces between the epitaxially grown metal silicide source/drain regions and the channel region. By employing the semiconductor device and the method for manufacturing the same according to embodiments of the present invention, the Schottkey Barrier Height of the MOSFETs with epitaxially grown ultrathin metal silicide source/drain may be lowered, thereby improving the driving capability. | 06-07-2012 |
20120156873 | METHOD FOR RESTRICTING LATERAL ENCROACHMENT OF METAL SILICIDE INTO CHANNEL REGION - A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer. | 06-21-2012 |
20120171833 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance. | 07-05-2012 |
20120181586 | Semiconductor device and manufacturing method thereof - The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly. | 07-19-2012 |
20120205728 | Semiconductor Structure and Method for Manufacturing the Same - The present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, and forming a dummy gate stack on the substrate, sidewall spacers on sidewalls of the dummy gate stack, and source/drain regions at both sides of the dummy gate stack, wherein the dummy gate stack comprising a dummy gate; forming a first contact layer on surfaces of the source/drain regions; forming an interlayer dielectric layer to cover the first contact layer; removing the dummy gate or the dummy gate stack material to form an opening, filling the opening with a first conductive material or with a gate dielectric layer and a first conductive material to form a gate stack structure; forming through holes within the interlayer dielectric layer, so that a portion of the first contact layer or a portion of the first contact layer and the source/drain regions are exposed in the through holes; forming a second contact layer on the exposed portions of the regions; filling the through holes with a second conductive material to form contact vias. Besides, the present invention further provides a semiconductor structure, which is favorable for reducing the contact resistance. | 08-16-2012 |
20120217589 | Semiconductor structure and method for manufacturing the same - A method for manufacturing a semiconductor structure comprises: providing a substrate ( | 08-30-2012 |
20120267706 | Semiconductor device and manufacturing method thereof - The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional isolation spacer; source/drain regions located in the substrate on opposite sides of the gate stack structure; epitaxially grown metal silicide located on the source/drain regions; characterized in that, the epitaxially grown metal silicide is in direct contact with a channel region controlled by the gate stack structure, thereby eliminating the high resistance region below the conventional isolation spacer. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly. | 10-25-2012 |
20130009217 | Transistor, Method for Manufacturing Transistor, and Semiconductor Chip Comprising the Transistor - It is provided a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. A method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack, a primary spacer, and source/drain regions, wherein the primary spacer surrounds the gate stack, and the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer; forming a semiconductor spacer surrounding the primary spacer, and cutting off the ends of the semiconductor spacer in the width direction of the gate stack so as to isolate the source/drain regions from each other; and covering the surfaces of the source/drain regions and the semiconductor spacer with a layer of metal or alloy, and annealing the resulting structure, so that a metal silicide is formed on the surfaces of the source/drain regions, and so that the semiconductor spacer is transformed into a silicide spacer simultaneously. As such, the risk of transistor failure due to atoms or ions of Ni entering the channel region through the source/drain extension regions is reduced. | 01-10-2013 |
20130045588 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved. | 02-21-2013 |
20130049125 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices. | 02-28-2013 |
20130062708 | SEMICONDUCTOR DEVICE STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING FIN - A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices. | 03-14-2013 |
20130105763 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 05-02-2013 |
20130221414 | Semiconductor FET and Method for Manufacturing the Same - The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated. | 08-29-2013 |
20130302952 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a gate stack structure on a substrate; forming source and drain regions as well as a gate spacer on both sides of the gate stack structure; depositing a first metal layer on the source and drain regions; performing a first annealing such that the first metal layer reacts with the source and drain regions, to epitaxially grow a first metal silicide; depositing a second metal layer on the first metal silicide; and performing a second annealing such that the second metal layer reacts with the first metal silicide as well as the source and drain regions, to form a second metal silicide. In accordance with the method for manufacturing a semiconductor device of the present invention, by means of epitaxially growing an ultra-thin metal silicide on the source and drain regions, the grain boundaries among silicide particles are minimized or eliminated, the metal diffusion speed and direction are limited, thus the lateral growth of the metal silicide is suppressed and the device performance is further increased. | 11-14-2013 |
20140088894 | METHOD AND DEVICE FOR EXTRACTING SKELETON TOPOLOGY STRUCTURE OF ELECTRIC POWER GRID - A system and method for extracting a skeleton topology structure for an electric power grid, the method comprising: receiving a description of a topology sub-structure corresponding with user's need and a description of skeleton topology sub-structure extracted from the topology sub-structure; generating a first incidence matrix based on the description of the topology sub-structure and a second incidence matrix based on the description of the skeleton topology sub-structure; generating a third incidence matrix based on a primary topology structure of electric power grid; searching from the third incidence matrix a sub-matrix that matches the first incidence matrix; obtaining a fourth incidence matrix by using the second incidence matrix to transform the matching sub-matrix; and generating a skeleton topology structure corresponding to the primary topology structure based on the fourth incidence matrix. | 03-27-2014 |
20140302644 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved. | 10-09-2014 |
20140357027 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved. | 12-04-2014 |
20150148076 | PUSH METHOD, SYSTEM AND SERVER BASED ON LOCATION INFORMATION - The present invention proposes a pushing method based on location information, comprising: recording a plurality of areas passed by a user; obtaining a resident area of the user according to the frequencies at which the user uses an electronic map in the plurality of areas, and pushing, when it is judged that the user enters a new area from the resident area, point of interest information in the new area to the user according to the point of interest information about the user in the resident area. The method in the embodiments of the present invention fully exploits the interests of a user and performs personalized customization, may better meet and inspire the needs of the user, and is widely applicable and easy to expand. The present invention also discloses a pushing system and server based on location information. | 05-28-2015 |
20150221768 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a semiconductor structure is disclosed. The method comprises: providing a substrate, forming a gate stack on the substrate and forming source/drain regions within the substrate; etching the source/drain regions to form trenches; forming a contact layer on the surface of the source/drain regions that have been etched; forming a stress material layer within the trenches; depositing an interlayer dielectric layer and forming contact plugs in contact with the stress material. Accordingly, a semiconductor structure is also disclosed. In the present invention, trenches are formed by etching source/drain regions in order to increase exposed areas at the source/drain regions, a contact layer is formed on the surface of the source/drain regions, and a stress material is filled into the trenches, which is capable of reducing effectively contact resistance between the contact layer and source/drain regions while introducing stress into channels, and thereby enhancing carrier mobility and improving performance of semiconductor structures. | 08-06-2015 |
20150262883 | PLANARIZATION PROCESS - A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat. | 09-17-2015 |
20150287606 | METHOD OF DEPOSITING TUNGSTEN LAYER WITH IMPROVED ADHESION AND FILLING BEHAVIOR - A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH | 10-08-2015 |
20150294879 | METHOD FOR MANUFACTURING FIN STRUCTURE - Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin. | 10-15-2015 |
20150303274 | METHOD FOR MANUFACTURING FIN STRUCTURE - A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin. | 10-22-2015 |
20150325452 | PLANARIZATION PROCESS - A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer. | 11-12-2015 |