Patent application number | Description | Published |
20130174112 | METHOD OF GENERATING A BIAS-ADJUSTED LAYOUT DESIGN OF A CONDUCTIVE FEATURE AND METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS - A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule. | 07-04-2013 |
20140282341 | FLEXIBLE PATTERN-ORIENTED 3D PROFILE FOR ADVANCED PROCESS NODES - The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced. | 09-18-2014 |
20150040077 | MULTI-PATTERNING MASK DECOMPOSITION METHOD AND SYSTEM - A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost. | 02-05-2015 |
20150052493 | METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS - A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design. | 02-19-2015 |
20150205905 | RESISTIVE CAPACITANCE DETERMINATION METHOD FOR MULTIPLE-PATTERNING-MULTIPLE SPACER INTEGRATED CIRCUIT LAYOUT - A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values. | 07-23-2015 |
20160042108 | METHOD OF GENERATING MODIFIED LAYOUT FOR RC EXTRACTION - A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns. | 02-11-2016 |
20160103948 | RESISTIVE CAPACITANCE DETERMINATION METHOD FOR MULTIPLE-PATTERNING-MULTIPLE SPACER INTEGRATED CIRCUIT LAYOUT - A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values. | 04-14-2016 |
Patent application number | Description | Published |
20140103833 | ORGANIC LIGHT EMITTING DEVICE AND LIGHT ADJUSTING METHOD THEREOF - An organic light emitting device includes, a first organic light emitting diode unit, a second light emitting diode unit, and an optical component. The first organic light emitting diode unit is connected with the second organic light emitting diode unit, and an internal angle is formed between the two organic light emitting diode units. The first organic light emitting diode unit, the second organic light emitting diode unit, and the optical component are connected together to form a triangle structure. A first light emitting region of the first organic light emitting diode unit and a second light emitting region of the second organic light emitting diode unit are overlapped on the optical component and forming a third light emitting region. A uniform light can be obtained by adjusting the first organic light emitting diode unit and the second organic light emitting diode unit respectively. | 04-17-2014 |
20140222118 | LIGHT EMITTING DIODE-BASED SKIN COSMETIC DEVICE - A light emitting diode-based skin cosmetic device includes a first light emitting panel, a second light emitting panel, a first narrow band filter, a second narrow band filter and an optical window. The first light emitting panel is connected with the second light emitting panel at one side and an angle is formed between the first light emitting panel and the second light emitting panel. Two sides of the optical windows are connected with the first light emitting panel and the second light emitting panel together to form a triangle structure and the angle is faced toward the optical windows. The first and second narrow band filter is disposed on one surface of the first light to emitting panel and one surface of the second light emitting panel respectively. | 08-07-2014 |
20140293597 | DIGITAL READING DEVICE WITH COSMETIC FUNCTION - A digital reading device with cosmetic function includes a base plate, a lighting panel, a driving unit and a transparent touch panel. The base plate includes a plurality of black units. The lighting panel is disposed on the base plate and includes as plurality of lighting units for emitting a green light. The driving unit is electrically connected to the lighting panel and the base plate, wherein the driving unit is for turning on or turning off each of the lighting units respectively. The transparent touch panel is disposed on the lighting panel for displaying a message composed of the black units. The message may also be white-colored on a green background color with various saturation levels whenever the lighting panel includes a plurality of displaying units, and each of the displaying units consists of two lighting units with complimentary colors. | 10-02-2014 |
20150055335 | DAY/NIGHT SWITCHABLE LIGHT ADJUSTING DEVICE AND LIGHT ADJUSTING METHOD THEREOF - A day/night switchable light adjusting device and light adjusting method thereof are provided. The day/night switchable light adjusting device is composed of a plurality of panels; each panel includes a reflecting surface and at least one lighting unit. Each lighting unit can emit various wavelength region lights, and the various wavelength lights are mixed on a light collecting component. A control unit is provided for adjusting the various wavelength region lights corresponding to day/night variation. A light intensity of a cyan region light or a blue region light is reduced for preventing an over-inhibition on a quantity of Melatonin. | 02-26-2015 |
Patent application number | Description | Published |
20090322667 | Data driver - A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on. | 12-31-2009 |
20120030549 | DATA TRANSMISSION DETECTING DEVICE, DATA TRANSMISSION DETECTING METHOD AND ELECTRONIC DEVICE THEREOF - A data transmission detecting device including a detecting module and a detection value calculating module is provided. The detecting module has a plurality of receiving terminals and receives a first data and a second data during a first period. The detecting module calculates a total detection value according to the first data and the second data, and performs an error check comparison by comparing the total detection value with an error check code. When the detecting module again receives the first data during a second period, the detection value calculating module transmits an auxiliary detection value to the detecting module, so that the detecting module calculates a corresponding total detection value according to the auxiliary detection value, and performs the error check comparison by comparing the total detection value with the error check code. The first period and the second period are two successive periods adjacent to each other. | 02-02-2012 |
20120062546 | DATA DRIVER - A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on. | 03-15-2012 |
20120246418 | MEMORY ARCHITECTURE FOR DISPLAY DEVICE AND CONTROL METHOD THEREOF - A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters. | 09-27-2012 |
20130120352 | DATA DRIVER - A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on. | 05-16-2013 |
20140132574 | MOTION DETECTION CIRCUIT AND MOTION DETECTION METHOD - A motion detection method is adapted for an image display circuit including a motion detection circuit and an arbitration circuit. In this motion detection method, a number of motion quality observation windows are defined. Each motion quality observation window includes a start point and an ending point. In the motion quality observation windows, a write frame count value is adjusted according to a write frame command. At the end point of each motion quality observation window, if the write frame count value is equal to or bigger than a preset count value, an enable signal is outputted to the arbitration circuit to determine whether the image display circuit performs motion display. In the motion quality observation windows, the end point of the i-th motion quality observation window is located between the start point and the end point of the (i+1)-th motion quality observation window, where i is a positive integer. | 05-15-2014 |
20140164691 | MEMORY ARCHITECTURE FOR DISPLAY DEVICE AND CONTROL METHOD THEREOF - A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters. | 06-12-2014 |
20140184581 | DATA DRIVER - A data driver includes two data processing circuits for respectively providing positive and negative pixel voltages according to first and second pixel data, and a multiplexer circuit including multiplexer units. Each multiplexer unit has first and second input terminals respectively receiving the positive and negative pixel voltages, and an output terminal coupled to a data line. A first switching device has first and second switches serially coupled between the first input and output terminals. A node between the first and second switches is selectively grounded via a third switch. A second switching device has fourth and fifth switches serially coupled between the second input and output terminals. A node between the fourth and fifth switches is selectively grounded via a sixth switch. When the first and second switches turn on, the sixth switch turns on. When the fourth and fifth switches turn on, the third switch turns on. | 07-03-2014 |
20140191936 | Driving Module and Driving Method - A driving module for a liquid crystal display device is disclosed. The driving module includes a data line signal processing unit, for generating a plurality of data driving signals, a scan line signal processing unit, for generating a plurality of gate driving signals, and a control unit, for generating a display clock, to control the data line signal processing unit and the scan line signal processing unit to address a plurality of pixels of the liquid crystal display device according to the display clock. The display clock is a normal operating clock under a normal operating mode and is a blanking backlight clock under a blanking backlight mode, wherein a frequency of the normal operating clock is less than a frequency of the blanking backlight clock. | 07-10-2014 |
20150042671 | Data Compression System for Liquid Crystal Display and Related Power Saving Method - A data compression system for a liquid crystal display (LCD) includes a host and a drive circuit. The host is utilized for outputting image data in a first data format or a second data format according to an operation mode of the LCD. The drive circuit includes a bypass path, for transmitting the image data according to the operation mode; a compression unit, coupled to the host, for receiving the image data and performing a compression procedure on the image data to generate a compression data according to the operation mode; a storage unit, coupled to the compression unit, for storing the compression data and the image data; a de-compression unit, coupled to the storage unit, for receiving the compression data and performing a de-compression procedure on the compression data to recover the image data according to the operation mode; and a display unit, for displaying the image data. | 02-12-2015 |
Patent application number | Description | Published |
20120265923 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 10-18-2012 |
20140075265 | Outputting Information of ECC Corrected Bits - The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information. | 03-13-2014 |
20140269074 | MANAGEMENT OF NON-VOLATILE MEMORY - A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged. | 09-18-2014 |
20140281150 | DIFFERENCE L2P METHOD - A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory. | 09-18-2014 |
20140281175 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 09-18-2014 |
Patent application number | Description | Published |
20090151637 | MICROWAVE-EXCITED PLASMA SOURCE USING RIDGED WAVE-GUIDE LINE-TYPE MICROWAVE PLASMA REACTOR - A microwave-excited plasma source using a ridged wave-guide line-type microwave plasma reactor is disclosed. The microwave-excited plasma source comprises a reaction chamber, a ridged wave-guide and a separation plate. The ridged wave-guide is disposed on the reaction chamber, and comprises a frame portion, a ridge portion and a line-shaped slot. The line-shaped slot is disposed on a first side of the frame portion, and the ridge portion facing the line-shaped slot is disposed on a second side of the frame portion. The separation plate is disposed on the line-shaped slot. Moreover, the ridged wave-guide is suitable for concentrating microwave power, which is transmitted to the reaction chamber through the line-shaped slot in order to excite plasma. | 06-18-2009 |
20100123381 | CATHODE DISCHARGE APPARATUS - A cathode discharge device is provided. The cathode discharge apparatus includes an anode, a cathode and plural cathode chambers. The cathode is located inside the anode, where the cathode has plural flow channels and at least one flow channel hole, and the plural flow channels are connected to one another through the flow channel hole. The plural cathode chambers are located inside the cathode, wherein each of the cathode chambers has a chamber outlet and a chamber inlet connected with at least one of the flow channels. | 05-20-2010 |
20100126418 | GAS SHOWER MODULE - A gas shower module for gas deposition chamber with gas channel is disclosed, which comprises: a distributor with at least one diffusion cell positioned therein along first axial direction and a plurality of inlets respectively connecting to the gas channel and the diffusion cell; and a shower with at least one shower channel positioned therein along second axial direction, gas-inlet passages connected to the diffusion cell and the shower channel, and gas-outlet passages connected to the shower channel and gas deposition chamber; wherein the distributor is connected to the shower so that the diffusion cell will be connected to the shower channel through gas-inlet passages and the first axial direction is not be parallel to the second axial direction. | 05-27-2010 |
20110079963 | VACUUM APPARATUS OF ROTARY MOTION ENTRY - A vacuum apparatus of rotary motion entry is disclosed, which comprises: a shaft sleeve, disposed on a cavity wall of a vacuum system; a rotary shaft, ensheathed by the shaft sleeve; and a transmission set, connected to the rotary shaft for driving the same; wherein, the rotary shaft is disposed passing through a hole formed on the base of the shaft sleeve while there are a first bearing, a second bearing, a sealing ring and a shaft seal being arranged separately inside the hole. Moreover, the shaft seal has a flake-like lip flange formed extending toward the center of the hole, that is capable of being extended away from the vacuum system by the inserting of the rotary shaft into the hole, and thereby, enabling the lip flange to engage with the rotary shaft tightly by the atmospheric pressure and thus isolating the outside world from the vacuum system. | 04-07-2011 |
20120070590 | PLASMA ENHANCED ATOMIC LAYER DEPOSITION APPARATUS AND THE CONTROLLING METHOD THEREOF - This prevent disclosure provides a plasma enhanced atomic layer deposition apparatus and the controlling method thereof. The plasma enhanced atomic layer deposition apparatus includes: a plurality of reaction chambers, each of the reaction chambers having a first reaction space and a second reaction space; an adjustable partition unit controlled to separate or communicate the first and the second reaction spaces; and a plurality of heating carriers respectively disposed in the plurality of reaction chambers. The method manipulates the movement of the partition plate, leading to separation or communication between the first and second reaction spaces, so as to avoid the interference or inter-reaction between process gases and the resultant particles contaminating the substrates. | 03-22-2012 |
20120132366 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus is disclosed, which includes: a cathode module comprising a plurality of first channels which generate plasma; an anode having a chamber which contains the cathode and having at least one plasma outlet corresponding to the first channels; an electrode connected to a high-frequency electrical power and the cathode; and a plurality of second channels penetrating through the anode; wherein each first channel and each second channel are disposed alternately. A first gas is introduced into the first channels ionized under high frequency electrical power. In the first channels, the free electrons collided brings high density of plasma. The generated plasma is expelled through the plasma outlet to form a plasma diffusion region. A second gas is introduced into the plasma diffusion region through the second channels to take part in the reaction of plasma. | 05-31-2012 |
20120240855 | TRANSMISSION MECHANISM AND THE DEPOSITION APPARATUS USING THE SAME - The deposition apparatus has a plurality of said transmission mechanisms arranged therein in a symmetrical manner. Each transmission mechanism comprises: a drive shaft, formed with a tapered end; a driving wheel, configured with a shaft hole for the tapered end to bore coaxially therethrough; a plurality of slide pieces, radially mounted to the driving wheel; a first elastic member, mounted enabling the plural slide pieces to be ensheathed thereby; a second elastic member, disposed between the first elastic member and the first axial end of the drive shaft while being mounted to the periphery of the driving wheel; an enclosure, configured with an opening; wherein, the driving wheel that is moving in a reciprocating manner drives the sliding pieces to slide in radial directions, thereby, causing the outer diameter of the first elastic member to change accordingly and enabling the opening of the enclosure to open or close in consequence. | 09-27-2012 |
Patent application number | Description | Published |
20130260511 | LID ATTACH PROCESS AND APPARATUS FOR FABRICATION OF SEMICONDUCTOR PACKAGES - A semiconductor package assembly process that includes attaching one or more dies to a substrate; applying an adhesive material on a periphery of the substrate by an adhesive dispenser having a stamp-type dispensing head; applying a thermal interface material (TIM) on a top surface of the die by a TIM dispenser having a stamp-type dispensing head; and positioning a lid over the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier to encapsulate the one or more dies. | 10-03-2013 |
20150059159 | APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An apparatus for manufacturing a semiconductor device includes a holder for holding a carrier and a supporting base for receiving the holder comprising a recess for accommodating a plurality of balls mounted on a surface of the carrier. Furthermore, a method of manufacturing a semiconductor device includes providing a carrier, providing an apparatus comprising a supporting base including a recess, holding the carrier on the supporting base and accommodating a plurality of balls mounted on a surface of the carrier in the recess. | 03-05-2015 |
20150069089 | LID ATTACH PROCESS AND APPARATUS FOR FABRICATION OF SEMICONDUCTOR PACKAGES - An adhesive dispenser comprises a dispensing head. The dispensing head comprises an adhesive material applicator portion on a first level of the dispensing head. The adhesive material applicator portion corresponds to a periphery of a package. The dispensing head also comprises a thermal interface material (TIM) applicator portion on a second level of the dispensing head different from the first level. The TIM applicator portion corresponds to a die of the package. The dispensing head further comprises an adhesive material conduit configured to supply the adhesive material applicator portion with an adhesive material. The dispensing head additionally comprises a TIM conduit configured to supply the TIM applicator portion with a TIM. | 03-12-2015 |
20150093856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a WLP semiconductor structure includes several operations. One of the operations is providing a carrier and the carrier includes a top surface. One of the operations is covering a portion of the top surface with a plurality of active dies. One of the operations is disposing a protrudent band on a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier. One of the operations is forming a molding compound on the carrier to cover the plurality of active dies. | 04-02-2015 |
20150145115 | EMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier. | 05-28-2015 |
20150155221 | ADHESIVE PATTERN FOR ADVANCE PACKAGE RELIABILITY IMPROVEMENT - The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die. | 06-04-2015 |
20160071744 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a method of manufacturing a device. The method includes providing a carrier, the carrier including a top surface, covering a portion of the top surface with a plurality of active dies, disposing a protrudent band over a periphery of the carrier, wherein the protrudent band includes a rim shaped along the contour of the carrier, and forming a molding compound over the carrier to cover the plurality of active dies. A method for determining a width of the protrudent band of a device described herein is also provided. | 03-10-2016 |
Patent application number | Description | Published |
20120208129 | PROCESS FOR FORMING AN ANTI-OXIDANT METAL LAYER ON AN ELECTRONIC DEVICE - A process for forming an anti-oxidant metal layer on an electronic device comprises the steps of providing a substrate; forming a conductive metal layer on the substrate; forming a first photoresist layer on the conductive metal layer; patterning the first photoresist layer to form apertures and first grooves; forming a connecting member having a top surface and a lateral surface in the aperture and the first groove; removing the first photoresist layer to reveal the top surface and the lateral surface; forming a second photoresist layer on the conductive metal layer; patterning the second photoresist layer to form apertures and second grooves; forming an anti-oxidant metal layer in aperture and second groove, the anti-oxidant metal layer covers the top surface and the lateral surface of the connecting member; and removing the second photoresist layer to reveal the anti-oxidant metal layer and the conductive metal layer. | 08-16-2012 |
20120211257 | PYRAMID BUMP STRUCTURE - A pyramid bump structure for electrically coupling to a bond pad on a carrier comprises a conductive block disposed at the bond pad and an oblique pyramid insulation layer covered at one side of the conductive block. The oblique pyramid insulation layer comprises a bottom portion and a top portion, and outer diameter of the oblique pyramid insulation layer is tapered from the bottom portion to the top portion. When the carrier is connected with a substrate and an anisotropic conductive film disposed at the substrate, the pyramid bump structure may rapidly embed into the anisotropic conductive film to raise the flow rate of the anisotropic conductive film. Further, a short phenomenon between adjacent bumps can be avoided to raise the yield rate of package process. | 08-23-2012 |
20130181346 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130193570 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
20130196498 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
20130249070 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film. | 09-26-2013 |
20130334671 | SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREOF - A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound. | 12-19-2013 |
20130334681 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate. | 12-19-2013 |
20140008111 | CARRIER WITH THREE-DIMENSIONAL CAPACITOR - A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal. | 01-09-2014 |
20140021601 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps. | 01-23-2014 |
20140027905 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate. | 01-30-2014 |
20140035125 | SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers. | 02-06-2014 |
20140035126 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers. | 02-06-2014 |
20140117540 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers. | 05-01-2014 |
20140120715 | SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers. | 05-01-2014 |
20140141606 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps. | 05-22-2014 |
20140217578 | SEMICONDUCTOR PACKAGE PROCESS AND STRUCTURE THEREOF - A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state. | 08-07-2014 |
Patent application number | Description | Published |
20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 12-04-2008 |
20100006924 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region. | 01-14-2010 |
20100073985 | METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage. | 03-25-2010 |
Patent application number | Description | Published |
20120105784 | PIXEL STRUCTURE AND DISPLAY PANEL - A pixel structure and a display panel are provided. The pixel structure includes a first scan line, a data line, a first active device, a first pixel electrode, and a first conductive pattern. The first active device is connected to the first scan line and the data line. The first pixel electrode is electrically connected to the data line through the first active device. The first conductive pattern is located above the first scan line and connected in parallel with the first scan line. | 05-03-2012 |
20120127067 | PIXEL ARRAY SUBSTRATE AND DISPLAY PANEL - A pixel array substrate and a display panel are provided. The pixel array substrate includes a substrate, scan line groups, data lines, and pixel structures. The scan line groups are disposed on the substrate. The data lines are intersected with the scan line groups. The pixel structures are connected to the scan line groups and the data lines. Each pixel structure includes an active device group, a first pixel electrode, a second pixel electrode, and a connection electrode. The first pixel electrode is located between the second pixel electrode and the n | 05-24-2012 |
20120138963 | PIXEL STRUCTURE - A pixel structure includes a substrate, a scan line, a first data line, a second data line, a first active device, a second active device, a first pixel electrode, and a second pixel electrode. The substrate has a first unit area and a second unit area. The first pixel electrode is disposed in the first unit area and includes a first main portion and first branch portions extending from the first main portion to an edge of the first unit area. The second pixel electrode is disposed in the second unit area and includes a second main portion and second branch portions extending from the second main portion to an edge of the second unit area, wherein at least a part of the first branch portions and at least a part of the second branch portions are asymmetrically arranged at two sides of the second data line. | 06-07-2012 |
20120162591 | PIXEL STRUCTURE - A pixel structure electrically connected to a scan line and a data line is provided. The pixel structure includes an active device and a pixel electrode, wherein the active device is electrically connected to the scan line and the data line, and the pixel electrode is electrically connected to the active device. The pixel electrode has a plurality of strip-shaped slit groups. Each of the strip-shaped slit groups includes a plurality of strip-shaped slits whose extending directions are substantially parallel to each other, and contours of at least parts of the strip-shaped slits are non-isosceles trapezoids. | 06-28-2012 |
20120235986 | THREE-DIMENSIONAL DISPLAY - A three-dimensional display includes a patterned phrase retarder and a three-dimensional display panel. The patterned phrase retarder includse a plurality of first bar-shaped phrase retardation regions and a plurality of second bar-shaped phrase retardation regions arranged alternately, wherein the phrase retardation of each of the first bar-shaped phrase retardation regions is different from the phrase retardation of each of the second bar-shaped phrase retardation regions. The three-dimensional display panel includes a plurality of pixels. The pixels are arranged in a plurality of pixel rows, wherein the coverage of each of the first bar-shaped phrase retardation regions corresponds to the distribution range of two adjacent pixel rows, and the coverage of each of the second bar-shaped phrase retardation regions corresponds to the distribution range of two adjacent pixel rows. | 09-20-2012 |
20120262430 | PIXEL ARRAY, PIXEL STRUCTURE, AND DRIVING METHOD OF A PIXEL STRUCTURE - A pixel array, a pixel structure, and a driving method of a pixel structure are provided. The pixel structure includes a first scan line, a second scan line, a first common electrode line, a data line, a first active device, a second device, a first pixel electrode, and a second pixel electrode. The data line is intersected with the first scan line and the second scan line. The first active device is driven by the first scan line and connected to the data line. The second active device is driven by the second scan line and connected to the first common electrode line. The first pixel electrode is electrically connected to the data line through the first active device. The second pixel electrode is electrically connected to the data line through the first active device and electrically connected to the first common electrode line through the second active device. | 10-18-2012 |
20120281144 | VIDEO-AUDIO PLAYING SYSTEM RELATING TO 2-VIEW APPLICATION AND METHOD THEREOF - A video-audio playing system relating to 2-view application and a method thereof are provided. In the present invention, sound signals respectively corresponding to two independent image frames are captured and played in coordinating with the displaying of these two independent image frames. Accordingly, two users can respectively watch two image frames which are different and irrelevant each other in the same display, and further respectively hear sound effects of the respective image frames at the same time. | 11-08-2012 |
20150131013 | LENS STRUCUTRE AND 3D DISPLAY DEVICE HAVING THE SAME - A lens structure and a 3D display device having the same are provided. The lens structure has unit regions. Each unit region includes upper and lower substrates, an anisotropic birefringence medium, center electrodes, edge electrodes and at least one set of side electrodes. The upper and the lower substrates are disposed oppositely to each other. The anisotropic birefringence medium is located between the upper and lower substrates. The center electrodes, the edge electrodes and the at least one set of side electrodes are located on the upper and lower substrates. The edge electrodes are disposed corresponding to the center electrodes. The at least one set of side electrodes are disposed between the center electrodes and the edge electrodes. An electric field distribution is formed between the center electrodes, the edge electrodes and the at least one set of side electrodes, so that the anisotropic birefringence medium constitutes a Fresnel lens. | 05-14-2015 |
20150237339 | PIXEL ARRAY, PIXEL STRUCTURE, AND DRIVING METHOD OF A PIXEL STRUCTURE - A pixel array, a pixel structure, and a driving method of a pixel structure are provided. The pixel structure includes a first scan line, a second scan line, a first common electrode line, a data line, a first active device, a second device, a first pixel electrode, and a second pixel electrode. The data line is intersected with the first scan line and the second scan line. The first active device is driven by the first scan line and connected to the data line. The second active device is driven by the second scan line and connected to the first common electrode line. The first pixel electrode is electrically connected to the data line through the first active device. The second pixel electrode is electrically connected to the data line through the first active device and electrically connected to the first common electrode line through the second active device. | 08-20-2015 |
20150279298 | DISPLAY PANEL AND DRIVING METHOD THEREOF - A display panel and a driving method thereof are provided. The display panel includes a plurality of scan lines, a plurality of first data lines, a plurality of second data lines and a plurality of pixels. The scan lines receive a plurality of scan signals. The pixels are arranged in an array and respectively have a first sub-pixel and a second sub-pixel. In each column, the first sub-pixel of i-th odd pixel electronically connects (2i−1)-th scan line and a corresponding first data line, the second sub-pixel of i-th odd pixel electronically connects (2i−1)-th and (2i)-th scan line and the corresponding first data line, the first sub-pixel of i-th even pixel electronically connects (2i)-th scan line and a corresponding second data line, and the second sub-pixel of i-th even pixel electronically connects (2i)-th and (2i+1)-th scan line and the corresponding second data line, wherein the i is a positive integer. | 10-01-2015 |
20150346395 | LENS STRUCTURE - A lens structure includes a plurality of lens units. Each of the lens units includes upper and lower substrates, an electrode film, a center electrode, an edge electrode, and at least one set of side electrodes. The electrode film on the upper substrate has a voltage Vtop. The center electrode on the lower substrate has a voltage Vc. The edge electrode on the lower substrate and on two sides of the center electrode has a voltage Ve. Each set of side electrodes is located on the lower substrate and between the center electrode and the edge electrode, and each set of side electrodes includes a main electrode and first and second auxiliary electrodes located on two sides of the main electrode. Voltages of the main electrode, the first auxiliary electrode, and the second auxiliary electrode are Vf, Vm, and Vfm, respectively, Vf>Vc>Ve, Vf>Vtop>Ve, and Vf>Vm>Ve. | 12-03-2015 |
20160097950 | CURVED DISPLAY PANEL - A curved display panel bended along a first direction is provided. The curved display panel has a first peripheral area, a center area, and a second peripheral area sequentially arranged along the first direction. The curved display panel includes a first substrate, data lines, scan lines, pixel units, a second substrate opposite to the first substrate, and a display medium disposed between the first substrate and the second substrate. The data lines and the scan lines are crossed to define pixel regions. The pixel units are respectively located in the pixel regions. The aperture ratio of at least one of the pixel regions located in the first peripheral area and the aperture ratio of at least one of the pixel regions located in the second peripheral area are smaller than the aperture ratio of at least one of the pixel regions located in the center area. | 04-07-2016 |
Patent application number | Description | Published |
20100318687 | METHOD AND APPARATUS FOR FORMATTING NETWORK-ATTACHED STORAGE - A method for formatting a network-attached storage (NAS) includes: coupling the NAS to a user-end personal computer (PC) via an external bus which supports a plug and play function; and utilizing the user-end PC to format a storage device of the NAS via the external bus. A network-attached storage includes a storage device, and a bus interface for coupling an external bus which supports a plug and play function such that the storage device of the NAS is formatted via the external bus. | 12-16-2010 |
20110173288 | NETWORK STORAGE SYSTEM AND RELATED METHOD FOR NETWORK STORAGE - A network storage system includes a first data buffer, a second data buffer, a pre-allocating module and a control module. The first data buffer is utilized for storing a storage data received from a network-base. The second data buffer is coupled to the first data buffer and includes a plurality of data buffering units. The pre-allocating module is coupled to the second data buffer and utilized for allocating the plurality of data buffering units to the second data buffer in advance. The control module controls the first data buffer to write the stored storage data into the plurality of data buffering units. | 07-14-2011 |
20120066414 | NETWORK STORAGE SYSTEM AND NETWORK STORAGE METHOD - The present invention provides a network storage system for increasing data writing efficiency of a net storage service and a network storage method for increasing data writing efficiency of the net storage service. The network storage system comprises: a first module, a first data buffer, a second module, and a third module. The present invention can omit the standard process of the traditional operation system processing files when writing data, and the network storage system and the network storage method of the present invention can use a new file processing procedure in the second module and the third module. In this way, the present invention can shorten the file processing flow in the traditional network storage system, so as to increase data writing efficiency of the net storage service over 50%. | 03-15-2012 |
20120102230 | NETWORK STORAGE SYSTEM AND NETWORK STORAGE METHOD - The present invention provides a network storage system for increasing data reading efficiency of a net storage service and a network storage method for increasing data reading efficiency of the net storage service. The network storage system comprises: a network processing module, a first fast file transmitting module, and a second fast file transmitting module. The present invention can omit the standard process of the traditional operation system processing files when reading data, and the network storage system and the network storage method of the present invention can use a new file processing procedure in the second fast file transmitting module. In this way, the present invention can shorten the file processing flow in the traditional network storage system, so as to increase data reading efficiency of the net storage service over 250%. | 04-26-2012 |
Patent application number | Description | Published |
20080278337 | URINE DETECTION SYSTEM AND METHOD - A urine detection system is provided for detecting degree of wetness of a diaper, comprising a plane printing electrode, a sensor, and a display unit. The plane printing electrode comprises a first electrode area and a second electrode area. The sensor comprises a first sensor electrode, a second sensor electrode and a processor. Wherein the first sensor electrode and the first electrode area forms a first capacitor, and the second sensor electrode and the second electrode area forms a second capacitor. The processor, detects capacitance of the first and second capacitors, and determines a signal representing degree of wetness of the diaper. The display unit receives the signal and displays the degree of wetness corresponding to the signal. | 11-13-2008 |
20080315433 | SELF-ALIGNED WAFER OR CHIP STRUCTURE, SELF-ALIGNED STACKED STRUCTURE AND METHODS FOR FABIRCATING THE SAME - A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface. | 12-25-2008 |
20090121299 | Wafer level sensing package and manufacturing process thereof - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 05-14-2009 |
20090124074 | WAFER LEVEL SENSING PACKAGE AND MANUFACTURING PROCESS THEREOF - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 05-14-2009 |
20090161901 | ULTRA THIN PACKAGE FOR ELECTRIC ACOUSTIC SENSOR CHIP OF MICRO ELECTRO MECHANICAL SYSTEM - An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed. | 06-25-2009 |
20110150261 | CAPACITIVE TRANSDUCER AND FABRICATION METHOD - A capacitive transducer and fabrication method are disclosed. The capacitive transducer includes a substrate, a first electrode mounted on the substrate, a cap having a through-hole and a cavity beside the through-hole, a second electrode mounted on the cap across the through-hole. The second electrode is deformable in response to pressure fluctuations applied thereto via the through-hole and defines, together with the first electrode, as a capacitor. The capacitor includes a capacitance variable with the pressure fluctuations and the cavity defines a back chamber for the deformable second electrode. | 06-23-2011 |
20110297434 | VACUUM HERMETIC ORGANIC PACKAGING CARRIER - A vacuum hermetic organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier. | 12-08-2011 |
20120146163 | MICROPHONE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A microphone package structure is provided, including an integrated circuit (IC) structure and a microphone structure disposed thereover and electrically connected therewith. The IC structure includes a first semiconductor substrate with opposite first and second surfaces, and a first through hole disposed in and through the first semiconductor substrate. The microphone structure includes: a second semiconductor substrate with opposite third and fourth surfaces, wherein the third surface faces to the second surface of the first semiconductor substrate; a second through hole disposed in and through the second semiconductor substrate; an acoustic sensing device embedded in the second through hole and adjacent to the third surface; and a sealing layer disposed over the fourth surface of the second semiconductor substrate, defining a back chamber with the sealing layer, wherein the first through hole allows acoustic pressure waves to penetrate and pass therethrough to the acoustic sensing device. | 06-14-2012 |
20120241938 | ORGANIC PACKAGING CARRIER - An organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and a sealing metal layer. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and includes at least a conductive layer and a sealing ring. The sealing ring is a closed ring. The sealing metal layer is located on the sealing ring, wherein a meterial of the sealing metal layer includes AgSn and is lead-free. | 09-27-2012 |
20120260747 | SENSING DEVICE AND MANUFACTURING METHOD THEREOF - A sensing device can be provided with sealed and open-type chambers in various conditions for accommodating different types of sensing structural components by stacking multiple substrates, wherein the condition of a sealed chamber depends on condition taken in substrate bonding process. Owing to sealing a channel of the sealed chamber by the substrate, superior sealing performance is achieved as compared to those adopting solder or sealing material, and thus the condition of the sealed chamber can be finely controlled. | 10-18-2012 |