Patent application number | Description | Published |
20120099044 | LIQUID CRYSTAL DISPLAY MODULE - A liquid crystal display (LCD) module includes a back bezel, a backlight module, a frame, an LCD panel, a circuit board, an assembling element, and a gasket. The frame has a top part and a bottom part opposite to the top part, and the bottom part faces the back bezel. The circuit board is configured on the top part of the frame and has a first surface and a second surface opposite to the first surface. The second surface faces the frame, and the circuit board has a ground area on the second surface. The assembling element pierces through the frame and connects the frame to the back bezel. The gasket leans against the ground area of the circuit board and the assembling element to form a conductive path from the ground area, the gasket, the assembling element to the back bezel. | 04-26-2012 |
20140078776 | BACKLIGHT MODULE - A backlight module includes a back bezel, a light guide plate, a plurality of optical films, and a clamping device. The light guide plate is disposed in an area enclosed by a periphery structure of the back bezel, and the optical films are disposed on the light guide plate. The clamping device includes a supporting element, a clamping piece, and a cushion element. The supporting element protrudes from the back bezel. The clamping piece is disposed on the supporting element and extends from the back bezel to the optical films. The cushion element is disposed between the clamping piece and the optical films. | 03-20-2014 |
Patent application number | Description | Published |
20110163376 | HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type. | 07-07-2011 |
20110241114 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well. | 10-06-2011 |
20120126334 | BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE - The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided. | 05-24-2012 |
20140197488 | METHOD OF FORMING HIGH VOLTAGE DEVICE - A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type. | 07-17-2014 |
Patent application number | Description | Published |
20140256138 | METHOD AND EQUIPMENT FOR REMOVING PHOTORESIST RESIDUE AFTER DRY ETCH - A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid. | 09-11-2014 |
20140261176 | PUMPING LINER FOR CHEMICAL VAPOR DEPOSITION - One or more pumping liners are provided for use in chemical vapor deposition (CVD). A pumping liner encircles a deposition chamber within which a wafer is placed and into which a precursor is introduced to form a thin film on a surface of the wafer. The pumping liner regulates a rate and uniformity at which a gas is removed from the deposition chamber, which in turn affects a duration or degree to which different portions of the wafer are exposed to the precursor. Controlling exposure of the wafer to the precursor promotes uniformity of the film formed on the wafer as well an ability to regulate the thickness of the film formed on the wafer. In an embodiment, a pumping liner has at least one of relatively small liner apertures, an increased number of liner apertures or a non-uniform distribution of liner apertures within a body of the pumping liner. | 09-18-2014 |
20150111394 | MECHANISMS FOR FORMING UNIFORM FILM ON SEMICONDUCTOR SUBSTRATE - Embodiments of mechanisms for forming a film deposition tool are provided. The film deposition tool includes a plasma source and a substrate processing region connected to the plasma source. The film deposition tool also includes a pedestal for supporting a substrate in the substrate processing region, wherein the substrate is prepared to be deposited with a film. The film deposition tool further includes electrodes embedded in the pedestal and separated from each other. The film deposition tool also includes a direct current bias system having variable voltage sources. The variable voltage sources are electrically connected to the electrodes, respectively, for providing direct current voltages to the electrodes independently. | 04-23-2015 |
20150249024 | METHOD AND EQUIPMENT FOR REMOVING PHOTORESIST RESIDUE AFER DRY ETCH - A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid. | 09-03-2015 |
Patent application number | Description | Published |
20130200398 | LIGHT EMITTING DIODE WITH WAVELENGTH CONVERSION LAYER - A light-emitting device comprises a base, a light-emitting unit comprising a semiconductor stack disposed on the base, and a wavelength conversion layer covering the light-emitting unit, wherein the wavelength conversion layer does not physically contact the base. | 08-08-2013 |
20140093991 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature. | 04-03-2014 |
20150129869 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprises a semiconductor stack, a first metal layer formed above the semiconductor stack, wherein the first metal layer comprises a first major plane and a first boundary with a gradually reduced thickness, and a second metal layer formed above the first metal layer, wherein the second metal layer comprise a second major plane paralleling to the first major plane and a second boundary with a gradually reduced thickness, and the second boundary of the second metal layer exceeds the first boundary of the first metal layer. | 05-14-2015 |
20150333241 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device including a substrate having a first site, a second side opposite to the first side, and an outer boundary; a light emitting unit formed on the first side; a first electrode electrically connected to the light emitting unit; a second electrode electrically connected to the light emitting unit; and a heat dissipation pad formed between the first electrode and the second electrode and electrically insulated from the light emitting unit. | 11-19-2015 |
20160027745 | LIGHT EMITTING DEVICE - The present disclosure provides a light emitting device including a serially-connected LED array comprising a plurality of LED cells on a substrate. The serially-connected LED array includes a first LED cell, a second LED cell, and a serially-connected LED sub-array comprising at least three LED cells intervening between the first and second LED cell; and a plurality of conducting metals formed on the LED cells to electrically connect the plurality of LED cell in series; wherein among the LED sub-array which are continuously and sequentially connected by the conducting metals, each LED cell connects to a previous LED cell by a first connecting direction and connects to a next LED cell by a second connecting direction, the first connecting direction is not parallel to the second connecting direction. | 01-28-2016 |
Patent application number | Description | Published |
20090143518 | FIRE RESISTANT MATERIAL AND FORMATION THEREOF - The invention provides a fire resistant material and a formulation thereof. The formulation comprises a liquid suspension of a modified inorganic particle and an organic component. The modified inorganic particle comprises an inorganic particle with hydroxyl groups and a surface modifier coupled to the inorganic particle via a urethane linkage, wherein the surface modifier has an ethylenically unsaturated end group. The organic component comprises a monomer, oligomer, prepolymer, polymer, or combinations thereof, capable of reacting with the ethylenically unsaturated end group. | 06-04-2009 |
20090143603 | MODIFIED INORGANIC PARTICLES AND METHODS OF PREPARING THE SAME - Disclosed are modified inorganic particles and methods of preparing the same. The modified inorganic particle comprises an inorganic particle with hydroxyl groups, and a surface modifier coupled to the inorganic particle via a urethane linkage, wherein the surface modifier has an ethylenically unsaturated end group. The method comprises providing an inorganic particle with hydroxyl groups; providing a surface modifier with an isocyanate group at one end and an ethylenically unsaturated group at the other end; and mixing the inorganic particle with the surface modifier for reaction such that the surface modifier is coupled to the inorganic particle. | 06-04-2009 |
20110288203 | FIRE RESISTANT MATERIAL AND FORMULATION THEREOF - The invention provides a fire resistant material and a formulation thereof. The formulation comprises a liquid suspension of a modified inorganic particle and an organic component. The modified inorganic particle comprises an inorganic particle with hydroxyl groups and a surface modifier coupled to the inorganic particle via a urethane linkage, wherein the surface modifier has an ethylenically unsaturated end group. The organic component comprises a monomer, oligomer, prepolymer, polymer, or combinations thereof, capable of reacting with the ethylenically unsaturated end group. | 11-24-2011 |
Patent application number | Description | Published |
20100118583 | MAGETIC SHIFT REGISTER AND DATA ACCESSING METHOD - A magnetic shift register memory includes at least a magnetic memory track, in which multiple domain walls separate the memory track into multiple magnetic domains to serve as magnetic memory cells. A fixed number of the magnetic memory cells forms a memory unit to store a burst data. A read/write device is implemented between the memory units to read or write the burst data to the magnetic memory cells passing the read/write device. A flag unit records a flag value for each memory track or each memory unit to indicate whether the burst data is located at a first side or a second side of the read/write device. A current unit provides an operation current to the magnetic memory track according to the flag value to move the domain walls to pass the read/write device. After the read/write device reads or writes the burst data, the flag value is updated. | 05-13-2010 |
20110090730 | MAGNETIC MEMORY STRUCTURE AND OPERATION METHOD - A magnetic memory structure includes a memory track which has consecutive magnetic domains. Each of the magnetic domains has memory capacity of one bit. A first domain-wall injecting layer intersects and connects a terminal of the memory track and constantly stores a first binary data. A second domain-wall injecting layer against the first domain-wall injecting layer intersects and connects the terminal of the memory track and constantly stores a second binary data different from the first binary data. The memory track and one of the first domain-wall injecting layer and the second domain-wall injecting layer together form a domain wall. | 04-21-2011 |
20110157955 | MAGNETIC SHIFT REGISTER MEMORY - A magnetic shift register memory includes a magnetic track and a reference magnetic region. The magnetic track has multiple magnetic domains. Each of the magnetic domains stores one bit data. One end of the magnetic domains is set with a first data injection domain for storing a first data, and a second data injection domain is located adjacent to the first data injection domain. The reference magnetic region corresponding to the second data injection region is implemented at a side of the magnetic track for storing a second data. | 06-30-2011 |
20130033917 | READER FOR MAGNETIC SHIFT REGISTER - A reader for magnetic shift register is provided. The reader includes a magnetic reference layer, a tunneling layer, a magnetic canceling layer and an isolated layer. The magnetic reference layer and the magnetic canceling layer are respectively configured at different sides of a magnetic track for providing anti-parallel magnetic fields. The magnetic reference layer overlaps the magnetic canceling layer in a perpendicular direction of the magnetic track. The magnetic reference layer electrically connects to a readout circuit. The magnetic canceling layer is floating. The tunneling layer is configured between the magnetic reference layer and the magnetic track for providing a magnetic tunnel junction (MTJ). The isolated layer is configured between the magnetic canceling layer and the magnetic track for avoiding a current in the magnetic track from tunneling to the magnetic canceling layer. | 02-07-2013 |
20130168786 | MAGNETIC SHIFT REGISTER WITH PINNING STRUCTURE - A magnetic shift register includes a first supporting layer, a second supporting layer, a first pinning material layer, and at least one magnetic memory track. The first supporting layer has trenches on a first surface extending along a first direction. The second supporting layer is filled in the trenches, wherein the first support layer and the second support layer have at least a portion substantially equal in height. The first pinning material layer is disposed between the first supporting layer and the second supporting layer, wherein a plurality of end surfaces of the first pinning material layer are exposed on the first surface. The magnetic memory track extending along a second direction on the first surface is disposed over the first support layer, the first pinning material layer, and the second support layer, wherein the second direction is not the same or perpendicular to the first direction. | 07-04-2013 |
20130168787 | MAGNETIC SENSOR - A magnetic sensor suitable for sensing an external magnetic field includes a magnetic tunnel junction (MTJ) device. The MTJ device is used to sense an out-of-plane (Z-axis) component of the external magnetic field at a perpendicular direction to the MTJ device. The MTJ device includes a first pinned magnetic layer, a tunnel layer and a magnetic sensing layer. The first pinned magnetic layer has a pinned magnetization perpendicular to the first pinned magnetic layer. The tunnel layer is disposed on the first pinned magnetic layer. The magnetic sensing layer is disposed on the tunnel layer. The magnetic sensing layer has a critical thickness to be at a superparamagnetic range, in which an out-of-plane (Z-axis) magnetic sensitivity is larger than an in-plane (X-axis, Y-axis) magnetic sensitivity. The first pinned magnetic layer, the tunnel layer and the magnetic sensing layer are stacked in a forward sequence or a reverse sequence. | 07-04-2013 |
20130168788 | TUNNELING MAGNETO-RESISTOR REFERENCE UNIT AND MAGNETIC FIELD SENSING CIRCUIT USING THE SAME - A tunneling magneto-resistor reference unit for sensing a magnetic field includes a first MTJ (magnetic tunneling junction) device and a second MTJ device connected in parallel. The first MTJ device has a first pinned layer having a first pinned magnetization at a pinned direction, and a first free layer having a first free magnetization parallel to the pinned direction in a zero magnetic field. The second MTJ device has a second pinned layer having a second pinned magnetization at the pinned direction, and a second free layer having a second free magnetization anti-parallel to the pinned direction in a zero magnetic field. Major axes of the first and second MTJ devices have an angle of 45 degrees to a direction of an external magnetic field when sensed. | 07-04-2013 |
20130207209 | TOP-PINNED MAGNETIC TUNNEL JUNCTION DEVICE WITH PERPENDICULAR MAGNETIZATION - A top-pinned magnetic tunnel junction device with perpendicular magnetization, including a bottom electrode, a non-ferromagnetic spacer, a free layer, a tunneling barrier, a synthetic antiferromagnetic reference layer and a top electrode, is provided. The non-ferromagnetic spacer is located on the bottom electrode. The free layer is located on the non-ferromagnetic spacer. The tunnel insulator is located on the free layer. The synthetic antiferromagnetic reference layer is located on the tunneling barrier. The synthetic antiferromagnetic reference layer includes a top reference layer located on the tunneling barrier, a middle reference layer located on the bottom reference layer and a bottom reference layer located on the tunneling barrier. The magnetization of the top reference layer is larger than that of the bottom reference layer. The top electrode is located on the synthetic antiferromagnetic reference layer. | 08-15-2013 |
20140001586 | PERPENDICULARLY MAGNETIZED MAGNETIC TUNNEL JUNCTION DEVICE | 01-02-2014 |
20140048895 | Magnetic Tunnel Junction Device - A magnetic tunnel junction (MTJ) device includes a reference layer having a surface, a tunnel insulating layer formed over the surface of the reference layer, and a free layer formed over the tunnel insulating layer. A magnetization direction in each of the reference layer and the free layer is substantially perpendicular to the surface. A dimension of the reference layer in a horizontal direction substantially parallel to the surface is larger than a dimension of the free layer in the horizontal direction. | 02-20-2014 |
20140048896 | Magnetic Tunnel Junction Device And Method Of Making Same - A magnetic tunnel junction (MTJ) device includes a reference layer having a surface, a tunnel insulating layer formed over the surface of the reference layer, a free layer formed over the tunnel insulating layer, and a magnetic field providing layer formed over the free layer. A magnetization direction in each of the reference layer and the free layer is substantially perpendicular to the surface. The magnetic field providing layer is configured to provide a lateral magnetic field in the free layer, the lateral magnetic field being substantially parallel to the surface. | 02-20-2014 |
20140145277 | MAGNETIC DEVICE - A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer. | 05-29-2014 |
20140361391 | MAGNETIC TUNNEL JUNCTION DEVICE WITH PERPENDICULAR MAGNETIZATION AND METHOD OF FABRICATING THE SAME - A magnetic tunnel junction device with perpendicular magnetization including a reference layer, a tunneling dielectric layer, a free layer and a capping layer is provided. The tunneling dielectric layer covers on the reference layer. The free layer covers on the tunneling dielectric layer. The capping layer is consisted of magnesium, aluminum and oxygen, and disposed on the free layer. | 12-11-2014 |
20150076634 | MAGNETIC DEVICE WITH A SUBSTRATE, A SENSING BLOCK AND A REPAIR LAYER - A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a bottom electrode, a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer. | 03-19-2015 |
Patent application number | Description | Published |
20100283476 | Testing System and Testing Method - The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure. | 11-11-2010 |
20100289706 | WIRELESS COMMUNICATING DEVICE AND PORTABLE ELECTRONIC APPARATUS USING THE SAME - A portable electronic apparatus is provided which includes a first housing, a second housing, a control unit, a display unit, and a wireless communication device. The two housings are rotatably coupled to each other. The control unit is accommodated in the first housing. The display unit is accommodated in the second housing and is connected to the control unit. The wireless communication device is accommodated in the second housing and has a wireless communication module and an antenna. The wireless communication module is connected to the control unit and the antenna, and is configured to perform wireless communication through the antenna under control of the control unit. | 11-18-2010 |
20130201650 | MOLDED RADIO-FREQUENCY STRUCTURE WITH SELECTIVE ELECTROMAGNETIC SHIELDING AND FORMING METHOD THEREOF - A molded radio-frequency (RF) structure with electromagnetic shielding includes a substrate layer, an RF layer, a molded layer and a metal layer. The RF element is disposed on the substrate layer. The molded layer is located on the substrate layer and overlays the RF element. The metal layer is coated on the molded layer, and has an opening located above the RF element. | 08-08-2013 |
Patent application number | Description | Published |
20090026567 | Image sensor package structure and method for fabricating the same - A method for fabricating an image sensor package is disclosed, comprising: providing a wafer having a plurality of image sensor integrated circuits, each of which has a photosensitive active region and at least one first bonding pad; joining a transparent protecting material to the wafer wherein the photosensitive active region of the image sensor integrated circuit is covered by the transparent protecting material; forming a plurality of through holes in the transparent protecting material, the through holes being correspondingly to the first bonding pad of the wafer to expose the first bonding pad; and dicing the wafer to form a plurality of image sensor integrated circuit components. The method for fabricating an image sensor package of the present invention decreases the defects of the photosensitive active region and reduces the size of the package structure. | 01-29-2009 |
20090212444 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including a substrate, a circuit pattern, a chip, at least one conductive material and an adhesive is provided. The substrate has a first surface, a second surface opposite thereto, and at least one through hole which penetrates the first surface and the second surface. The circuit pattern structure is disposed on the second surface and has at least one connecting pad disposed at the through hole. The chip is disposed on the first surface of the substrate. The chip has at least one conductive post, wherein the conductive post and the conductive material are disposed inside the through hole, and the conductive post is electrically connected with the pattern circuit structure through the conductive material. The adhesive is disposed between the chip and the substrate. A manufacturing method of the semiconductor structure is also provided. | 08-27-2009 |
20100207638 | Testing System and Testing Method - The invention discloses a testing system and a testing method. The testing system includes a testing platform and a fetching device. The testing platform includes a metal base plate, a DUT board, a testing stand and a metal wall. The DUT board is disposed on the metal base plate. The testing stand is disposed on the DUT board. The metal wall is disposed on the metal base plate and surrounds the testing stand. The fetching device is movably disposed above the testing platform and used for placing a DUT on the testing stand. A metal covering plate of the fetching device corresponds to the metal wall of the testing platform. When the fetching device places the DUT on the testing stand, the metal covering plate cooperates with the metal wall and the metal base plate of the testing platform to form an isolated space, so as to isolate the DUT. | 08-19-2010 |
Patent application number | Description | Published |
20090151637 | MICROWAVE-EXCITED PLASMA SOURCE USING RIDGED WAVE-GUIDE LINE-TYPE MICROWAVE PLASMA REACTOR - A microwave-excited plasma source using a ridged wave-guide line-type microwave plasma reactor is disclosed. The microwave-excited plasma source comprises a reaction chamber, a ridged wave-guide and a separation plate. The ridged wave-guide is disposed on the reaction chamber, and comprises a frame portion, a ridge portion and a line-shaped slot. The line-shaped slot is disposed on a first side of the frame portion, and the ridge portion facing the line-shaped slot is disposed on a second side of the frame portion. The separation plate is disposed on the line-shaped slot. Moreover, the ridged wave-guide is suitable for concentrating microwave power, which is transmitted to the reaction chamber through the line-shaped slot in order to excite plasma. | 06-18-2009 |
20100123381 | CATHODE DISCHARGE APPARATUS - A cathode discharge device is provided. The cathode discharge apparatus includes an anode, a cathode and plural cathode chambers. The cathode is located inside the anode, where the cathode has plural flow channels and at least one flow channel hole, and the plural flow channels are connected to one another through the flow channel hole. The plural cathode chambers are located inside the cathode, wherein each of the cathode chambers has a chamber outlet and a chamber inlet connected with at least one of the flow channels. | 05-20-2010 |
20110073038 | GAS DISTRIBUTION PLATE AND APPARATUS USING THE SAME - The present invention provides a gas distribution plate for providing at least two gas flowing channel. In one embodiment, the gas distribution plate has a first flowing channel, at least a second flowing channel disposed around the first flowing channel, and a tapered opening communicating with the first and the second flowing channel. In another embodiment, the gas distribution plate has a first flowing channel passing through a first and a second surface of the gas distribution plate, a second flowing channel paralleling to the first surface and a third flowing channel disposed at the second surface and communicating with the second flowing channel. The ends of the first and the third flowing channel have a tapered opening respectively. Besides, the present further provides a gas distribution apparatus for allowing at least two separate gases to be delivered independently into a process chamber while enabling the gases to be mixed completely after entering the processing chamber. | 03-31-2011 |
20110079963 | VACUUM APPARATUS OF ROTARY MOTION ENTRY - A vacuum apparatus of rotary motion entry is disclosed, which comprises: a shaft sleeve, disposed on a cavity wall of a vacuum system; a rotary shaft, ensheathed by the shaft sleeve; and a transmission set, connected to the rotary shaft for driving the same; wherein, the rotary shaft is disposed passing through a hole formed on the base of the shaft sleeve while there are a first bearing, a second bearing, a sealing ring and a shaft seal being arranged separately inside the hole. Moreover, the shaft seal has a flake-like lip flange formed extending toward the center of the hole, that is capable of being extended away from the vacuum system by the inserting of the rotary shaft into the hole, and thereby, enabling the lip flange to engage with the rotary shaft tightly by the atmospheric pressure and thus isolating the outside world from the vacuum system. | 04-07-2011 |
20120070590 | PLASMA ENHANCED ATOMIC LAYER DEPOSITION APPARATUS AND THE CONTROLLING METHOD THEREOF - This prevent disclosure provides a plasma enhanced atomic layer deposition apparatus and the controlling method thereof. The plasma enhanced atomic layer deposition apparatus includes: a plurality of reaction chambers, each of the reaction chambers having a first reaction space and a second reaction space; an adjustable partition unit controlled to separate or communicate the first and the second reaction spaces; and a plurality of heating carriers respectively disposed in the plurality of reaction chambers. The method manipulates the movement of the partition plate, leading to separation or communication between the first and second reaction spaces, so as to avoid the interference or inter-reaction between process gases and the resultant particles contaminating the substrates. | 03-22-2012 |
20120132366 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus is disclosed, which includes: a cathode module comprising a plurality of first channels which generate plasma; an anode having a chamber which contains the cathode and having at least one plasma outlet corresponding to the first channels; an electrode connected to a high-frequency electrical power and the cathode; and a plurality of second channels penetrating through the anode; wherein each first channel and each second channel are disposed alternately. A first gas is introduced into the first channels ionized under high frequency electrical power. In the first channels, the free electrons collided brings high density of plasma. The generated plasma is expelled through the plasma outlet to form a plasma diffusion region. A second gas is introduced into the plasma diffusion region through the second channels to take part in the reaction of plasma. | 05-31-2012 |
20120240855 | TRANSMISSION MECHANISM AND THE DEPOSITION APPARATUS USING THE SAME - The deposition apparatus has a plurality of said transmission mechanisms arranged therein in a symmetrical manner. Each transmission mechanism comprises: a drive shaft, formed with a tapered end; a driving wheel, configured with a shaft hole for the tapered end to bore coaxially therethrough; a plurality of slide pieces, radially mounted to the driving wheel; a first elastic member, mounted enabling the plural slide pieces to be ensheathed thereby; a second elastic member, disposed between the first elastic member and the first axial end of the drive shaft while being mounted to the periphery of the driving wheel; an enclosure, configured with an opening; wherein, the driving wheel that is moving in a reciprocating manner drives the sliding pieces to slide in radial directions, thereby, causing the outer diameter of the first elastic member to change accordingly and enabling the opening of the enclosure to open or close in consequence. | 09-27-2012 |
Patent application number | Description | Published |
20100089775 | ELECTROCHEMICAL TEST STRIP, ELECTROCHEMICAL TEST SYSTEM, AND MEASUREMENT METHOD USING THE SAME - An electrochemical test strip, an electrochemical test system, and a measurement method using the same are provided. The electrochemical test strip includes an insulating substrate, an electrode system formed on the insulating substrate, and an insulating layer formed on the electrode system. The electrode system includes a set of measurement electrodes, a set of identifying electrodes, and a resistive path having a predetermined resistance value. The set of identifying electrodes is made of metal material, and the resistive path is made of non-metal material. The set of measurement electrodes includes a reference electrode and a working electrode insulated from each other, and the set of identifying electrodes includes a first identifying electrode and a second identifying electrode connected with each other through the resistive path. The insulating layer covers a part of the electrode system, wherein a part of the electrode system not covered by the insulating layer forms a reaction region with a supply port. When a sample is injected into the supply port of the reaction region, the injected sample reaches the set of measurement electrodes and the set of identifying electrodes in sequence. | 04-15-2010 |
20110104731 | REACTION CASSETTE, ASSAY DEVICE, AND ASSAY METHOD - A reaction cassette for biochemical assay, a biochemical assay device including the reaction cassette, and a biochemical assay method performed by using the biochemical assay device are provided. The reaction cassette includes a first space, a second space, a third space, and an inner wall. The first space is configured to accommodate liquid and includes a first opening facing upward. The second space includes a second opening whose direction is perpendicular to the direction of the first opening. The first space and the second space are disposed such that when the reaction cassette is rotated, liquid in the first space can flow into the second space. The third space is located under the first space and includes a third opening whose direction is the same as the direction of the first opening. The inner wall connects the second opening and the third opening, which serves as a liquid flow channel between the second space and the third space. | 05-05-2011 |
Patent application number | Description | Published |
20130113041 | SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE - Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel. | 05-09-2013 |
20130113047 | MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL - A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized. | 05-09-2013 |
20130277685 | SOI TRANSISTORS WITH IMPROVED SOURCE/DRAIN STRUCTURES WITH ENHANCED STRAIN - A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance. | 10-24-2013 |
20150162445 | CHANNEL STRAIN INDUCING ARCHITECTURE AND DOPING TECHNIQUE AT REPLACEMENT POLY GATE (RPG) STAGE - The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance. | 06-11-2015 |
20150194485 | MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL - A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized. | 07-09-2015 |
Patent application number | Description | Published |
20140096102 | SYSTEM AND METHOD FOR ACROSS-CHIP THERMAL AND POWER MANAGEMENT IN STACKED IC DESIGNS - A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time. | 04-03-2014 |
20140126274 | MEMORY CIRCUIT AND METHOD OF OPERATING THE MEMORY CIRCUI - A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals. | 05-08-2014 |
20140239427 | Integrated Antenna on Interposer Substrate - Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane. | 08-28-2014 |
20140282305 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 09-18-2014 |
20150213182 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 07-30-2015 |
Patent application number | Description | Published |
20080231618 | Method and apparatus for image processing - An overdriving apparatus is provided in the invention. The apparatus includes a receiving module, a storing module, a dynamic information generating module, and an image driving module. The receiving module receives image data relative to an image signal. The storing module is used for storing the image data. Based on the image data, the dynamic information generating module generates dynamic information corresponding to a current image. The image driving module then generates an overdriving signal and/or a standard driving signal, according to the dynamic information and the image data, to drive a display. | 09-25-2008 |
20080284914 | IMAGE ADJUSTMENT DEVICE AND METHOD THEREOF - The present invention provides a device and an image adjustment method by simultaneously adjusting the luminance and the chrominance of an image. The device comprises a luminance analysis device, a contrast adjusting device, a luminance adjusting device, a chrominance compensation device and a luminance gain adjusting device. The method comprises steps of: generating a maximum input luminance signal, an average input luminance signal and a minimum input luminance signal according to an input luminance signal; generating a contrast value according to at least one of the maximum input luminance signal and the average input luminance signal; generating an input luminance offset according to the input luminance signal and the minimum input luminance signal; generating an output chrominance signal according to the contrast value and an input chrominance signal; and generating an output luminance signal according to the input luminance offset and the contrast value. | 11-20-2008 |
20090195524 | MULTIMEDIA SYSTEM AND REMOTE CONTROL DEVICE THEREOF - A multimedia system and a remote control device are provided. The multimedia system includes a remote sensor, a wireless transmitter, and a display apparatus. The remote sensor is used for sensing an environmental luminance. The wireless transmitter is used for transmitting a control signal corresponding to the environmental luminance. The display apparatus includes a light source and a wireless receiver. The display apparatus receives the control signal via the wireless receiver and adjusts a brightness level of the light source based on the control signal. | 08-06-2009 |
20090310884 | NOISE REDUCTION METHOD AND NOISE REDUCTION APPARATUS - The present invention provides a noise reduction method for use in reducing noise of a digital image, the method comprising steps of: providing a plurality of luminance threshold values; determining a plurality of luminance feature values according to the luminance value of a target pixel and the luminance values of neighboring pixels of the target pixel; determining whether the target pixel is a noise point based on the comparison between each of the luminance feature values and each of the luminance threshold values corresponding thereto, respectively; and adjusting the luminance value, a first chrominance value and a second chrominance value of the target pixel if the target pixel is determined as a noise point. Using the noise reduction method of the present invention, not only noise of a digital image can be identified, but also the degradation caused by the noise can be reduced and thus the overall picture quality can be improved. | 12-17-2009 |
20090316023 | NOISE REDUCTION METHOD AND NOISE REDUCTION APPARATUS - The present invention provides a noise reduction method and apparatus for use in reducing noise of a digital image. The noise reduction apparatus comprises a threshold value generating unit, a determining unit, and an adjusting unit. The threshold value generating unit generates a noise threshold value according to a target window and a first chrominance value and a second chrominance value of an input pixel of the image. The determining unit determines whether the input pixel needs to be adjusted according to the noise threshold value and pixel values of neighboring pixels of the input pixel. The adjusting unit adjusts the pixel value of the input pixel when the input pixel is determined as needing to be adjusted. Using the noise reduction apparatus of the present invention, not only noise of a digital image can be identified, but also the degradation caused by the noise can be reduced and thus the overall picture quality can be improved. | 12-24-2009 |