Patent application number | Description | Published |
20090128835 | GAMUT MAPPING - A mapping technique is disclosed that maps color image data of an image displayed on a first image display device to output color image data for display on a second image display device. This mapping technique maps the color gamut of the first image display device to the color gamut of the second image display device while controlling one or more characteristics of the color image data, and generates one or more lookup tables that correspond to the gamut mapping, for example. The color image data is then mapped to the output color image data based on the lookup tables. | 05-21-2009 |
20090135279 | REDUCING IMAGING ARTIFACTS CAUSED BY DEFECTIVE IMAGING ELEMENT - A method of compensating for a defective imaging element includes measuring an actual value generated by a defective element, comparing an actual value to an image value resulting in a comparison value, and adjusting neighboring image values for at least an imaging element immediately adjacent to the defective imaging element depending upon the comparison value. An imaging system has an array of imaging elements, having at least one defective imaging element, a processor to operate the array of imaging elements, the processor to determine an actual value produced by a defective imaging element, compare the actual value to an image value for the defective imaging element resulting in a comparison value, and adjust operation of at least an imaging element immediately adjacent the defective imaging element, based upon the comparison value. | 05-28-2009 |
20090184975 | CACHING FOR COLOR MANAGEMENT SYSTEMS PERFORMING A GAMUT MAPPING FUNCTION - What is provided herein is a novel system and method which improves efficiency of a color management system performing a gamut mapping function. In one embodiment, a plurality of source colors are examined to determine whether any have changed. If not, then the source profile, the source device model, and the color appearance model have not changed. Next, the primary colors of the destination device are examined to determine whether any of these have changes. If these have not changed, then the destination device profile and the destination device model have not changed. When the source profile, device profile, color appearance model and the device models have not changed, gamut mapping does not have to be performed. The cached gamut mapping data are used instead. The gamut mapping data are used in subsequent mappings between these same two devices. The cached gamut mapping data are used to customize a color response of the destination device. | 07-23-2009 |
20090284762 | REDUCING PRINTHEAD PROCESS COLOR NON-UNIFORMITIES IN A DIRECT MARKING DEVICE - What is disclosed is a novel system and method for reducing process color banding due to printhead non-uniformities in a direct marking device. In one example, a first measurement of a printhead spatial non-uniformity is obtained along a first line in a color space which produces a spatial uniformity when a target primary color is printed alone. A first spatial tone reproduction curve is generated. A second measurement of the printhead spatial non-uniformity is obtained along a second line in color space in a coverage area of a process color which maximally changes a halftone structure of the target primary color. A second spatial TRC is generated. The first and second spatial TRCs are combined using a weighted average which balances the primary and process colors. A modified spatial TRC is generated. The printhead is adjusted at a location of the target primary color according to the modified spatial TRC. | 11-19-2009 |
20100277770 | COLOR TRAPPING ON A HALFTONED BI-LEVEL BITMAP - What is disclosed is a novel system and method for color trapping on halftoned bi-level bitmaps. Color edges are detected and edge pixels that need to be trapped are identified. The number of pixels qualified as edge pixels eligible for color trapping can be up to a pre-determined number of pixels away from the color edge. Estimates for the continuous-tone values are obtained for the dominant colors on each side of the two-color edge. The contone value of the dominant color on the opposing side of the two-color edge is assigned to the qualified edge pixels. Qualified edge pixels are re-halftoned using their assigned contone value so that halftones for one color are extended beyond the edge into the other color. The re-halftoned edge pixels are combined with the original bitmap to produce a new bitmap for the image. The new bitmap is then provided to an image output device. | 11-04-2010 |
20110051197 | BITMAPPED BASED TRAPPING METHODS, APPARATUS AND SYSTEMS - Provided are bitmap based trapping methods, apparatus and systems. According to one exemplary method, black trapping color image data is performed by estimating the continuous tone values associated with non-black pixels near a qualified black pixel and subsequently, the estimated continuous tone values are halftoned at the qualified black pixel locations and ORed with the original bitmap data. | 03-03-2011 |
20110243429 | COLOR TRAPPING ON A HALFTONED BI-LEVEL BITMAP - What is disclosed is a novel system and method for determining whether a pixel resides along a two-color edge in a halftoned bi-level bitmap. In one embodiment, a bitmap having a plurality of colored pixels is received. For each pixel in the bitmap, a window of size n×m is defined centered on the current pixel. The window is partitioned into a plurality of regions with each region having an orientation direction with each orientation direction having an associated numeric value. A number of pixels are counted for each of the first and second colors in each of the associated orientation directions. A determination is made as to the respective orientation direction having the maximum and minimum pixel counts for each of the first and second colors. Thereafter, a determination is made whether the pixel resides along a two color edge based upon the max/min counts and each associated orientation direction. | 10-06-2011 |
20120020570 | THIN LINE DETECTION AND ENHANCEMENT FOR ELECTRONIC IMAGES HAVING DIFFERENT RESOLUTIONS - A methodology for thin line detection and enhancement in electronic images is disclosed. The methodology includes associating an electronic image with at least one basic context window that is less than the size of the electronic image based on the input image resolution of the electronic image; detecting one or more predefined patterns which correspond to thin lines in the electronic image using the at least one basic context window; excluding patterns for the one or more detected patterns which are halftone patterns; and adding at least one pixel to the electronic image based on at least one of the remaining patterns so as to enhance thin line features in the electronic image. In some implementation, the methodology may be configured to handle electronic images having different resolutions. A system for thin line detection and enhancement in electronic images having different resolutions is also disclosed. | 01-26-2012 |
20120069357 | SYSTEM AND METHOD FOR ENHANCING THE DENSITY OF BLACK - A computer-implemented method and system for enhancing black density of a halftoned bitmap are provided. The method includes receiving a halftoned bitmap into computer memory, and, using a computer, identifying at least one black-only pixel in the halftoned bitmap. The method further includes for each of the identified black-only pixels, identifying at least one black-only pixel as a candidate for adding color based at least in part on the location of the black-only pixel with respect to an edge in the halftoned bitmap, modifying the halftoned bitmap by adding color to at least one of the candidate black-only pixels, and outputting the modified halftoned bitmap. | 03-22-2012 |
20120177286 | DETERMINING AN ORIENTATION DIRECTION OF A COLOR EDGE AT A PIXEL LOCATION IN A COLOR IMAGE - What is disclosed is a system and method for determining an orientation direction of a color edge at a given pixel location in a binary color image. The orientation direction of the color edge is determined from eight pixel counts with each pixel count being a total number of pixels in each of eight regions of a window centered about a candidate pixel which resides along the color edge. The eight regions are associated with 8 compass points. The orientation of the edge is determined by a 1 | 07-12-2012 |
20120189196 | DETERMINING AN ORIENTATION DIRECTION OF A COLOR EDGE AT A PIXEL LOCATION IN A COLOR IMAGE - What is disclosed is a system and method for determining an orientation direction of a color edge at a given pixel location in a binary color image. The orientation direction of the color edge is determined from eight pixel counts with each pixel count being a total number of pixels in each of eight regions of a window centered about a candidate pixel which resides along the color edge. The eight regions are associated with 8 compass points. The orientation of the edge is determined by a 1 | 07-26-2012 |
20130250363 | METHOD AND SYSTEM FOR PRESERVING IMAGE QUALITY IN AN ECONOMY PRINT MODE - A system and method converts pixels of continuous image data to pixels of binary image data using a halftone screen corresponding to a predetermined reduced coverage percentage; determines if a target pixel of binary image data is a non-white pixel; compares a window of pixels of binary image data with a predetermined pattern of pixels of binary image data corresponding to the predetermined reduced coverage percentage; determines that the target pixel is a non-edge pixel; and reduces the number of non-white pixels in the binary image data based upon the determination that the target pixel is a non-edge pixel. | 09-26-2013 |
20130311403 | CONTONE DOMAIN COLOR PIXEL COUNTING FOR COLOR AREA COVERAGE BASED BILLING - Disclosed herein are a method and a system implementing the method for billing using color pixel counting in documents or image in the contone domain. The method includes using the intensity or density levels (e.g., 0 to 255) for each color of each pixel of interest in the contone domain to calculate one or more probability values that one or more output colorants are provided at its location in the binary domain. The probabilities determined based on the contone color domain data are used to estimate an overall area coverage of color pixels in the document, which can be used to determine a billing structure or cost for outputting the document. | 11-21-2013 |
20140050269 | SYSTEMS AND METHODS FOR COMPUTATION-EFFICIENT IMAGE PROCESSING SYSTEM ARCHITECTURE - Embodiments relate to systems and methods for a computation-efficient image processing system architecture. Image data can be transmitted from a computer, online service, and/or other image source to an output device having a set of image processing modules in two or more image paths, including an edge detection module and a video decoding module. The edge detection module can produce edge tag output, and the video decoding module, operating in parallel, can generate decoded video output. The edge tag output and decoded video output can be transmitted to a set of downstream image processing modules, including modules for color trapping, edge smoothing, and other operations. Because earlier processing stages share information with downstream modules which require the same or related data, redundant processing can be reduced or eliminated. Complex image operations can therefore be carried out, and high-quality output can be generated, without sacrificing responsiveness. | 02-20-2014 |
Patent application number | Description | Published |
20110316060 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL - An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. In an embodiment, the capacitor and tunnel structure can include upper electrodes, wherein the upper electrode of the capacitor has a first conductivity type, and the upper electrode of the tunnel structure includes at least a portion that has a second conductivity type opposite the first conductivity type. In another embodiment, a process of forming the nonvolatile memory is performed using a single poly process. In a further embodiment, charge carriers can tunnel through a gate dielectric layer of the state transistor during programming and tunnel through a tunnel dielectric of the tunnel transistor during erasing. | 12-29-2011 |
20110316067 | ELECTRONIC DEVICE INCLUDING A TUNNEL STRUCTURE - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 12-29-2011 |
20110317492 | METHOD OF USING A NONVOLATILE MEMORY CELL - An electronic device can include a nonvolatile memory cell. In a particular embodiment, during an erase pulse, all unselected lines are at substantially the same voltage, and a row or segment of a row, such as a word, is erased during the erase pulse. In another embodiment, selected control gate and erase lines are at substantially the same voltage during a programming pulse. In a further embodiment, charge carriers tunnel through a dielectric layer of a component during a program pulse, and charge carriers tunnel through a different dielectric layer of a different component during an erase pulse. | 12-29-2011 |
20130062698 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY STRUCTURE HAVING AN ANTIFUSE COMPONENT AND A PROCESS OF FORMING THE SAME - An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an access transistor, a read transistor, and an antifuse component coupled to the access transistor and the read transistor. In an embodiment, the read transistor can include a gate electrode, and the antifuse component can include a first electrode and a second electrode overlying the first electrode. The gate electrode and the first electrode can be parts of the same gate member. In another embodiment, the access transistor can include a gate electrode, and the antifuse component can include a first electrode, an antifuse dielectric layer, and a second electrode. The electronic device can further include a conductive member overlying the antifuse dielectric layer and the gate electrode of the access transistor, wherein the conductive member is configured to electrically float. Processes for making the same are also disclosed. | 03-14-2013 |
20130062703 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY STRUCTURE HAVING AN ANTIFUSE COMPONENT AND A PROCESS OF FORMING THE SAME - An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process. | 03-14-2013 |
20130063999 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY STRUCTURE HAVING AN ANTIFUSE COMPONENT AND A PROCESS OF USING THE SAME - An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined. | 03-14-2013 |
20130161723 | Electronic Device Including a Tunnel Structure - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 06-27-2013 |
20130175593 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL - An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. In an embodiment, the capacitor and tunnel structure can include upper electrodes, wherein the upper electrode of the capacitor has a first conductivity type, and the upper electrode of the tunnel structure includes at least a portion that has a second conductivity type opposite the first conductivity type. In another embodiment, a process of forming the nonvolatile memory is performed using a single poly process. In a further embodiment, charge carriers can tunnel through a gate dielectric layer of the state transistor during programming and tunnel through a tunnel dielectric of the tunnel transistor during erasing. | 07-11-2013 |
20130307046 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY STRUCTURE HAVING AN ANTIFUSE COMPONENT - An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an access transistor, a read transistor, and an antifuse component coupled to the access transistor and the read transistor. In an embodiment, the read transistor can include a gate electrode, and the antifuse component can include a first electrode and a second electrode overlying the first electrode. The gate electrode and the first electrode can be parts of the same gate member. In another embodiment, the access transistor can include a gate electrode, and the antifuse component can include a first electrode, an antifuse dielectric layer, and a second electrode. The electronic device can further include a conductive member overlying the antifuse dielectric layer and the gate electrode of the access transistor, wherein the conductive member is configured to electrically float. Processes for making the same are also disclosed. | 11-21-2013 |
20140021526 | ELECTRONIC DEVICE INCLUDING A TUNNEL STRUCTURE - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 01-23-2014 |
20140022844 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL INCLUDING A TUNNEL STRUCTURE - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 01-23-2014 |
20150070992 | Process of Forming an Electronic Device Including a Nonvolatile Memory Cell - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 03-12-2015 |