Patent application number | Description | Published |
20080294868 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 11-27-2008 |
20100005464 | EFFICIENT RECORDING AND REPLAYING OF NON-DETERMINISTIC INSTRUCTIONS IN A VIRTUAL MACHINE AND CPU THEREFOR - The output of a non-deterministic instruction is handled during record and replay in a virtual machine. An output of a non-deterministic instruction is stored to a buffer during record mode and retrieved from a buffer during replay mode without exiting to the hypervisor. At least part of the contents of the buffer can be stored to a log when the buffer is full during record mode, and the buffer can be replenished from a log when the buffer is empty during replay mode. | 01-07-2010 |
20110179256 | PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD - A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at. | 07-21-2011 |
20120072697 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 03-22-2012 |
20120079257 | METHODS AND SYSTEMS THAT DEFER EXCEPTION HANDLING - Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set. | 03-29-2012 |
20120166703 | METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES - A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address. | 06-28-2012 |
20120254584 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 10-04-2012 |
20120265965 | PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD - A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at. | 10-18-2012 |
20130111184 | METHOD AND SYSTEM FOR CACHING ATTRIBUTE DATA FOR MATCHING ATTRIBUTES WITH PHYSICAL ADDRESSES | 05-02-2013 |
20130290689 | EFFICIENT RECORDING AND REPLAYING OF NON-DETERMINISTIC INSTRUCTIONS IN A VIRTUAL MACHINE AND CPU THEREFOR - The output of a non-deterministic instruction is handled during record and replay in a virtual machine. An output of a non-deterministic instruction is stored to a buffer during record mode and retrieved from a buffer during replay mode without exiting to the hypervisor. At least part of the contents of the buffer can be stored to a log when the buffer is full during record mode, and the buffer can be replenished from a log when the buffer is empty during replay mode. | 10-31-2013 |
20140082291 | SPECULATIVE PERMISSION ACQUISITION FOR SHARED MEMORY - In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed. | 03-20-2014 |
20140136891 | MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD - Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response. | 05-15-2014 |
20140164736 | LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR - Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode. | 06-12-2014 |
20140164738 | INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION - Embodiments related to methods and devices operative, in the event that execution of an instruction produces a runahead-triggering event, to cause a microprocessor to enter into and operate in a runahead without reissuing the instruction are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic for retrieving an instruction, scheduling logic for issuing the instruction retrieved by the fetch logic for execution, and runahead control logic. The example runahead control logic is operative, in the event that execution of the instruction as scheduled by the scheduling logic produces a runahead-triggering event, to cause the microprocessor to enter into and operate in a runahead mode without reissuing the instruction, and carry out runahead policies while the microprocessor is in the runahead mode that governs operation of the microprocessor and cause the microprocessor to operate differently than when not in the runahead mode. | 06-12-2014 |
20140189313 | QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD - Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic. | 07-03-2014 |
20140281259 | TRANSLATION LOOKASIDE BUFFER ENTRY SYSTEMS AND METHODS - Presented systems and methods can facilitate efficient information storage and tracking operations, including translation look aside buffer operations. In one embodiment, the systems and methods effectively allow the caching of invalid entries (with the attendant benefits e.g., regarding power, resource usage, stalls, etc), while maintaining the illusion that the TLBs do not in fact cache invalid entries (e.g., act in compliance with architectural rules). In one exemplary implementation, an “unreal” TLB entry effectively serves as a hint that the linear address in question currently has no valid mapping. In one exemplary implementation, speculative operations that hit an unreal entry are discarded; architectural operations that hit an unreal entry discard the entry and perform a normal page walk, either obtaining a valid entry, or raising an architectural fault. | 09-18-2014 |
20140281392 | PROFILING CODE PORTIONS TO GENERATE TRANSLATIONS - The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode. | 09-18-2014 |
20150149733 | SUPPORTING SPECULATIVE MODIFICATION IN A DATA CACHE - Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from a cache. The at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line. Further, the plurality of state indicators is operable to indicate a state of a corresponding cache line of the cache lines. | 05-28-2015 |
Patent application number | Description | Published |
20100122013 | DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES - A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state. | 05-13-2010 |
20100138615 | HANDLING DIRECT MEMORY ACCESSES - Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system. | 06-03-2010 |
20120131307 | DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES - A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state. | 05-24-2012 |
20150089188 | Vector Hazard Check Instruction with Reduced Source Operands - In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction. | 03-26-2015 |
Patent application number | Description | Published |
20100186131 | MOLECULAR MARKERS LINKED TO PPO INHIBITOR TOLERANCE IN SOYBEANS - This invention relates generally to the detection of genetic differences among soybeans. More particularly, the invention relates to soybean quantitative trait loci (QTL) for tolerance to protoporphyrinogen oxidase inhibitors, to soybean plants possessing these QTLs, which map to a novel chromosomal region, and to genetic markers that are indicative of phenotypes associated with protoporphyrinogen oxidase inhibitor tolerance. Methods and compositions for use of these markers in genotyping of soybean and selection are also disclosed. | 07-22-2010 |
20110185445 | HPPD-INHIBITOR HERBICIDE TOLERANCE - This invention relates generally to the detection of genetic differences among soybeans. More particularly, the invention relates to soybean quantitative trait loci (QTL) for tolerance or sensitivity to HPPD-inhibitor herbicides, such as mesotrione and isoxazole herbicides, to soybean plants possessing these QTLs, which map to a novel chromosomal region, and to genetic markers that are indicative of phenotypes associated with tolerance, improved tolerance, susceptibility, or increased susceptibility. Methods and compositions for use of these markers in genotyping of soybean and selection are also disclosed, as are methods and compositions for use of these markers in selection and use of herbicides for weed control. Also disclosed are isolated polynucleotides and polypeptides relating to such tolerance or sensitivity and methods of introgressing such tolerance into a plant by breeding or transgenically or by a combination thereof. Plant cells, plants, and seeds produced are also provided. | 07-28-2011 |
20110277173 | Soybean Sequences Associated with the FAP3 Locus - Compositions and methods for identifying soybean plants with reduced levels of saturated fatty acids are provided. Methods of making soybean plants with reduced levels of saturated fatty acids, e.g., through introgression of desired saturated fatty acid marker alleles and/or by transgenic production methods, as well as plants or germplasm made by these methods, are provided. Kits for selecting plants with reduced levels of saturated fatty acids are also provided. | 11-10-2011 |
20130047301 | MOLECULAR MARKERS ASSOCIATED WITH SOYBEAN ROOT-KNOT NEMATODE TOLERANCE AND METHODS OF THEIR USE - This invention relates to molecular markers useful for identifying and, optionally, selecting soybean plants displaying tolerance, improved tolerance, or susceptibility to root-knot nematode, methods of their use, and compositions having one or more marker loci. In certain examples, the method comprises detecting at least one marker locus. In other examples, the method comprises detecting a haplotype comprising two or more marker loci. In further examples, the method further comprises crossing a selected soybean plant with a second soybean plant. This invention further relates to primers, probes, kits, systems, etc., useful for carrying out the methods described herein. | 02-21-2013 |
20140234840 | MOLECULAR MARKERS LINKED TO PPO INHIBITOR TOLERANCE IN SOYBEANS - This invention relates generally to the detection of genetic differences among soybeans. More particularly, the invention relates to soybean quantitative trait loci (QTL) for tolerance to protoporphyrinogen oxidase inhibitors, to soybean plants possessing these QTLs, which map to a novel chromosomal region, and to genetic markers that are indicative of phenotypes associated with protoporphyrinogen oxidase inhibitor tolerance. Methods and compositions for use of these markers in genotyping of soybean and selection are also disclosed. | 08-21-2014 |