Patent application number | Description | Published |
20100120218 | METHOD FOR FABRICATING PARTIAL SOI SUBSTRATE - A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches. | 05-13-2010 |
20100248467 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - Disclosed is a method for fabricating a nonvolatile memory device having a stacked gate structure in which a floating gate, a charge blocking layer, and a control gate are sequentially stacked. The method includes forming a first conductive layer for floating gate over a substrate; forming a charge blocking layer and a second conductive layer for control gate over a resulting structure including the first conductive layer; forming an etch mask pattern over the second conductive layer; performing a primary etch process on the second conductive layer until the charge blocking layer is exposed; forming a passivation layer on a sidewall of the second conductive layer exposed by the primary etch process; and performing a secondary etch process on the charge blocking layer and the first conductive layer. | 09-30-2010 |
20110159664 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES - A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer. | 06-30-2011 |
20140306351 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts | 10-16-2014 |
Patent application number | Description | Published |
20090242971 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed. | 10-01-2009 |
20090250732 | Semiconductor device and method of fabricating the same - In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a sidewall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns. | 10-08-2009 |
20090250748 | Semiconductor device and method of fabricating the same - A semiconductor device and method of fabricating the same includes preparing a substrate, forming a plurality of conductive layer patterns on the substrate, forming a gate insulation layer on sidewalls of the conductive layer patterns, forming a pillar neck pattern between the conductive layer patterns, forming a pillar head over the pillar neck pattern and the conductive layer patterns, and forming a gate electrode surrounding the pillar neck pattern and forming a pillar head pattern by selectively etching the conductive layer patterns and the pillar head formed over the pillar neck pattern. | 10-08-2009 |
20090317954 | Method for forming vertical channel transistor of semiconductor device - A method for forming a vertical channel transistor of a semiconductor device includes forming a plurality of pillar patterns over a substrate, forming a gate insulation layer encapsulating the resultant pillar pattern structure, forming a surrounding gate electrode conduction layer surrounding the sidewalls of the pillar pattern including the gate insulation layer, filling a sacrificial layer to a predetermined height of a surrounding gate electrode in a gap region between neighboring pillar patterns having the surrounding gate electrode conduction layer, and forming the surrounding gate electrode by removing a portion of the surrounding gate electrode conduction layer exposed by the sacrificial layer. | 12-24-2009 |
20110254081 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed. | 10-20-2011 |
20130181266 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a side wall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns. | 07-18-2013 |