Patent application number | Description | Published |
20080272845 | OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) - Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA. | 11-06-2008 |
20080297234 | CURRENT MIRROR BIAS TRIMMING TECHNIQUE - A reference current is generated by a current mirror circuit. An operational amplifier of a feedback circuit generates a control voltage for control of the feedback circuit transistor. The size of the feedback circuit transistor is trimmed, and the current through the feedback circuit transistor remains relatively constant via operation of the feedback circuit. The feedback circuit transistor is scaled in size relative to the size of current reference transistor(s) (e.g., current sources or sinks), which are tied to the same control voltage. The reference current of the current reference transistors thus varies with the size of the feedback circuit transistor. Further advantageously, transistors providing reference currents for resistor ladders can also be tied to the same control voltage, but scaled proportionally with changes in size to the feedback circuit transistor, thereby maintaining relatively constant voltage from taps of the resistor ladder, even when the feedback circuit transistor is trimmed. | 12-04-2008 |
20090096904 | Method and apparatus providing column parallel architecture for imagers - An imaging apparatus and a method using column processing circuits arranged in multiple rows for processing pixels in a pixel array. | 04-16-2009 |
20090219095 | OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) - Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA. | 09-03-2009 |
20100013445 | COMPARATOR CONTROLLED CHARGE PUMP FOR NEGATIVE VOLTAGE BOOSTER - Charge pumps and methods for regulating charge pumps. The charge pump includes a voltage booster circuit and a voltage regulator circuit. The voltage booster circuit includes first and second input terminals that respectively receive a regulation voltage and an input voltage. The voltage booster circuit generates an output voltage having a polarity that is different from the input voltage. The output voltage is adjusted by the regulation voltage and provided to an output terminal. The voltage regulator circuit is coupled between the first input terminal and the output terminal of the voltage booster circuit. The voltage regulator circuit shifts the output voltage to a level shifted voltage and generates the regulation voltage responsive to the level shifted voltage. | 01-21-2010 |
Patent application number | Description | Published |
20120249851 | ECLIPSE DETECTION USING DOUBLE RESET SAMPLING FOR COLUMN PARALLEL ADC - An imager includes a column line connected to a pixel array for providing a pixel output signal. The pixel output signal is sampled during reset and readout phases. An analog-to-digital converter (ADC), which is coupled to the column line, samples the pixel output signal and provides a digital output signal. The ADC is configured to sample the pixel output signal twice, during the reset phase, in order to detect eclipse in the pixel output signal. The ADC includes a comparator, sequentially operated by a reset control, for comparing a first pixel output voltage and a second pixel output voltage, respectively, during the reset phase. The comparator is configured to provide an output bit indicating detection of an eclipse, based on a difference between the first and second pixel output voltages. | 10-04-2012 |
20130075584 | IMAGER ROW CONTROL-SIGNAL TESTER - Row-control signal monitoring system for an electronic imager includes signal processing circuitry coupled a pixel array of the electronic imager which receives at least one row control signal from the pixel array and provides an output signal corresponding to the selected row control signal. Monitoring circuitry compares the output signal to a target value to test the at least one row-control signal. | 03-28-2013 |
20130083204 | SELF TEST OF IMAGE SIGNAL CHAIN WHILE RUNNING IN STREAMING MODE - An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array. | 04-04-2013 |
20130293724 | IMAGING SYSTEMS WITH SIGNAL CHAIN VERIFICATION CIRCUITRY - An imaging system may include an array of image pixels and verification circuitry. The verification circuitry may inject a test voltage into the pixel signal chain of a test pixel. The test voltage may be output on a column line associated with the column of pixels in which the test pixel is located. The test signal may be provided to a column ADC circuit for conversion from an analog test signal to a digital test signal. Verification circuitry may compare the digital output test signal with a predetermined reference signal to determine whether the imaging system is functioning properly (e.g., to determine whether column ADC circuits or other circuit elements in the pixel signal chain are functioning properly). If the output test signals do not match the expected output signals, the imaging system may be disabled and/or a warning signal may be presented to a user of the system. | 11-07-2013 |
20140048686 | CAPACITANCE SELECTABLE CHARGE PUMP - A step-up converter includes an input coupled to receive a first voltage potential and an output coupled to output a second voltage potential higher than the first voltage potential. The step-up converter also includes an array of capacitance charge pumps. Each of the capacitance charge pumps in the array includes switches to be modulated to individually run each of the capacitance charge pumps by selectively connecting each of the capacitance charge pumps to the input and the output. The step-up converter further includes a control module coupled to the switches of each of the capacitance charge pumps and configured to modulate the switches at a substantially fixed frequency. The control module modulates the switches of selected capacitance charge pumps in the array in response to a current draw on the output. The step-up converter may be included in an image sensor. | 02-20-2014 |
20140347496 | SELF TEST OF IMAGE SIGNAL CHAIN WHILE RUNNING IN STREAMING MODE - An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to-digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array. | 11-27-2014 |
20140347498 | SELF TEST OF IMAGE SIGNAL CHAIN WHILE RUNNING IN STREAMING MODE - An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array. | 11-27-2014 |