Patent application number | Description | Published |
20100118636 | Methods and Systems Involving Electrically Reprogrammable Fuses - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 05-13-2010 |
20100294740 | Directed self-assembly of block copolymers using segmented prepatterns - An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls. | 11-25-2010 |
20100297847 | Method of forming sub-lithographic features using directed self-assembly of polymers - Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes. | 11-25-2010 |
20100327445 | STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided. | 12-30-2010 |
20100330810 | METHOD FOR REMOVING THRESHOLD VOLTAGE ADJUSTING LAYER WITH EXTERNAL ACID DIFFUSION PROCESS - The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid. | 12-30-2010 |
20110042653 | Near-Infrared Absorbing Film Compositions - A curable liquid formulation containing at least (i) one or more near-infrared absorbing triphenylamine-based dyes, and (ii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film. | 02-24-2011 |
20110042771 | Near-Infrared Absorbing Film Compositions - A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film. | 02-24-2011 |
20110262862 | NEAR-INFRARED ABSORPTIVE LAYER-FORMING COMPOSITION AND MULTILAYER FILM - A composition comprising (A) a near-infrared absorbing dye of formula (1), (B) a polymer, and (C) a solvent is used to form a near-infrared absorptive layer. In formula (1), R | 10-27-2011 |
20110262863 | NEAR-INFRARED ABSORPTIVE LAYER-FORMING COMPOSITION AND MULTILAYER FILM - A near-infrared absorptive layer is formed from a composition comprising (A) an acenaphthylene polymer, (B) a near-infrared absorbing dye, and (C) a solvent. When a multilayer film comprising the near-infrared absorptive layer and a photoresist layer is used in optical lithography, the detection accuracy of optical auto-focusing is improved, allowing the optical lithography to produce a definite projection image with an improved contrast and succeeding in forming a better photoresist pattern. | 10-27-2011 |
20120028476 | METHOD OF FORMING SEMICONDUCTOR STRUCTURES WITH CONTACT HOLES - Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes forming a set of shapes on top of a substrate; applying a layer of copolymer covering the substrate; causing the copolymer to form a plurality of cylindrical blocks both inside and outside the shapes; forming a pattern of contact holes from the plurality of cylindrical blocks; and transferring the pattern of contact holes to the substrate to form the semiconductor structure. In one embodiment, the shapes are rings and forming the set of shapes includes forming a set of rings that are equally and squarely spaced. In another embodiment, causing the copolymer to form the plurality of cylindrical blocks includes forming only one cylindrical block inside each of the rings and only one cylindrical block outside every four (4) squarely neighboring rings. | 02-02-2012 |
20120100712 | STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided. | 04-26-2012 |
20120301828 | NEAR-INFRARED ABSORPTIVE LAYER-FORMING COMPOSITION AND MULTILAYER FILM COMPRISING NEAR-INFRARED ABSORPTIVE LAYER - A composition comprising a polymer comprising repeat units selected from formulae (1) to (4), an aromatic ring-containing polymer, a near-infrared absorbing dye, and a solvent is used to form a near-infrared absorptive film. R | 11-29-2012 |
20130001484 | Near-Infrared Absorbing Film Compositions - A curable liquid formulation containing at least (i) one or more near-infrared absorbing triphenylamine-based dyes, and (ii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film. | 01-03-2013 |
20130176805 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 07-11-2013 |
20130228900 | Gate conductor with a diffusion barrier - A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. | 09-05-2013 |
20140177373 | SYSTEM INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire. | 06-26-2014 |
20140252538 | ELECTRONIC FUSE WITH RESISTIVE HEATER - A method of forming an electronic fuse including forming an M | 09-11-2014 |
20140282297 | METHOD FOR GENERATING POST-OPC LAYOUT IN CONSIDERATION OF TOP LOSS OF ETCH MASK LAYER - A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer. | 09-18-2014 |
20150048479 | SELF-ALIGNED VIA FUSE - A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches. | 02-19-2015 |
20150084193 | EMBEDDED ON-CHIP SECURITY - Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification. | 03-26-2015 |
20150130018 | VIA-FUSE WITH LOW DIELECTRIC CONSTANT - In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material. | 05-14-2015 |
20150154421 | ON-CHIP STRUCTURE FOR SECURITY APPLICATION - A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string. | 06-04-2015 |
20150194320 | METALLIC MASK PATTERNING PROCESS FOR MINIMIZING COLLATERAL ETCH OF AN UNDERLAYER - A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer. | 07-09-2015 |
20150228578 | ELECTRONIC FUSE WITH RESISTIVE HEATER - An electronic fuse structure including an M | 08-13-2015 |
20150243732 | NOVEL INTEGRATION PROCESS TO FORM MICROELECTRONIC OR MICROMECHANICAL STRUCTURES - The invention relates to transferring, in one exposure, a single-mask feature to form two features on an underlying material. Specifically, a doubled walled structure (i.e. a center opening flanked by adjacent openings) is formed. Advantageously, the openings may be sub-resolution openings. The center opening may be a line flanked by two other lines. The center opening may be circular and surrounded by an outer ring, thus forming a double wall ring structure. In an electronic fuse embodiment, the double wall ring structure is a via filled with a conductor that contacts a lower and upper level metal. In deep trench embodiment, the double wall ring structure is a deep trench in a semiconductor substrate filled with insulating material. In such a way the surface area of the trench is increased thereby increasing capacitance. | 08-27-2015 |
20150255326 | EMBEDDED ON-CHIP SECURITY - Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification. | 09-10-2015 |
20150340292 | PATTERNING PROCESS FOR FIN IMPLANTATION - After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation. | 11-26-2015 |
20150371904 | PATTERNING PROCESS FOR FIN IMPLANTATION - After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation. | 12-24-2015 |
20160049339 | BLOCK PATTERNING PROCESS FOR POST FIN - A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and fin structures in a block mask patterning process is provided. The block mask stack including an OPL, a developable antireflective coating (DARC) layer atop the OPL and a photoresist layer atop the DARC layer is employed to mask one conductivity type of FinFET while exposing the other conductivity type FinFET during source/drain ion implantation. The OPL is configured to have a minimum thickness sufficient to fill in spaces between semiconductor fins and to cover the semiconductor fins. The DARC layer is configured to planarize topography of semiconductor fins so as to provide a planar top surface for the ensuing lithography and etch processes. | 02-18-2016 |