Kim, ID
Byung Kim, Boise, ID US
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20110252512 | CANTILEVER-BASED OPTICAL INTERFACIAL FORCE MICROSCOPE - An apparatus may comprise an optical detector configured to detect an optical beam reflected from a cantilever. The apparatus may further comprise an optical fiber probe suspended from the cantilever and a piezotube configured to move a sample substance in proximity to the optical fiber probe. The cantilever may be configured to deflect in response to an interfacial force between the sample substance and the optical fiber probe. The apparatus may further comprise a feedback controller communicatively coupled to the optical detector and a semiconductive circuit element abutting the cantilever. In response to detecting movement of the optical beam reflected from the cantilever, the feedback controller may apply a voltage to the semiconductive circuit element, which may reduce deflection of the cantilever. The voltage applied by the feedback controller may indicate a strength of the interfacial force between the sample substance and the optical fiber probe. | 10-13-2011 |
Byung I. Kim, Boise, ID US
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20120047610 | CANTILEVER-BASED OPTICAL INTERFACE FORCE MICROSCOPE - A method and an apparatus for detecting a normal force component and a friction force component between a probe and a sample substance using an interfacial force microscope is disclosed herein. According to one embodiment, a method of measuring normal and friction forces with an interfacial force microscope includes positioning a sample substance on a piezotube and in proximity to a probe suspended from a cantilever such that a molecular force between the sample substance and the probe causes the cantilever to deflect. The method may include converting the deflection of the cantilever into an electrical signal comprising a normal force and a friction force component, and measuring the normal and friction force components. | 02-23-2012 |
20130298294 | SYSTEM AND METHOD FOR IMAGING SOFT MATERIALS - A method of measuring properties of a sample, the method comprising: measuring a deflection of a cantilever of a COIFM; measuring a voltage at an actuator contacting the cantilever and configured to counteract the deflection of the cantilever; measuring a voltage at a scan signal source, wherein the scan signal source is communicably coupled to the piezotube and configured to move the piezotube along an X- and a Y-axis; measuring a voltage at a feedback controller, wherein the feedback controller is communicably coupled to the piezotube and configured to move the piezotube along a Z-axis; switching a switch from a first position to a second position; switching the switch to a third position; correlating at least one of the measurements to (i) a repulsive force, and (ii) an attractive force. | 11-07-2013 |
20130312142 | SYSTEM AND METHOD FOR HIGH-SPEED ATOMIC FORCE MICROSCOPY - A high-speed atomic force microscope (HSAFM) is disclosed herein. The HSAFM includes a cantilever, a piezotube, an optical detector, a circuit element, and a feedback controller. The cantilever has a probe, and the piezotube is arranged in proximity to the probe. The optical detector is configured to detect deflection of the cantilever, and the circuit element is abutting a first end of the cantilever and is configured to exert a force on the cantilever to resist deflection of the cantilever. The circuit element is communicably connected to the optical detector by a first feedback loop. The feedback controller is communicably connected to the piezotube and configured to modulate the piezotube along the Z-axis towards and away from the probe. And the feedback controller is communicably connected to the optical detector through a second feedback loop. | 11-21-2013 |
Eung Soo Kim, Ammon, ID US
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20110131991 | METHODS AND SYSTEMS FOR THE PRODUCTION OF HYDROGEN - Methods and systems are disclosed for the production of hydrogen and the use of high-temperature heat sources in energy conversion. In one embodiment, a primary loop may include a nuclear reactor utilizing a molten salt or helium as a coolant. The nuclear reactor may provide heat energy to a power generation loop for production of electrical energy. For example, a supercritical carbon dioxide fluid may be heated by the nuclear reactor via the molten salt and then expanded in a turbine to drive a generator. An intermediate heat exchange loop may also be thermally coupled with the primary loop and provide heat energy to one or more hydrogen production facilities. A portion of the hydrogen produced by the hydrogen production facility may be diverted to a combustor to elevate the temperature of water being split into hydrogen and oxygen by the hydrogen production facility. | 06-09-2011 |
Gi-Hong Kim, Boise, ID US
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20120287732 | APPARATUS AND METHODS OF DRIVING SIGNAL - Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor. | 11-15-2012 |
20140078847 | MEMORY REFRESH METHODS, MEMORY SECTION CONTROL CIRCUITS, AND APPARATUSES - Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section an and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage. | 03-20-2014 |
20140204689 | APPARATUS AND METHODS OF DRIVING SIGNAL FOR REDUCING THE LEAKAGE CURRENT - Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor. | 07-24-2014 |
20150023121 | MEMORY REFRESH METHODS, MEMORY SECTION CONTROL CIRCUITS, AND APPARATUSES - Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage. | 01-22-2015 |
20150046738 | DATA BUFFER SYSTEM AND POWER CONTROL METHOD - A data buffer system includes a plurality of data buffer modules and a plurality of switching units. The data buffer module is configured for buffering a corresponding data signal. The data buffer module includes a plurality of buffers. The buffers are electrically coupled in series. The switching unit is configured for supplying power to the corresponding buffer in accordance with a regulated voltage. Each of the switching units is electrically coupled between the corresponding one of the buffers and the supply voltage. A power control method for a data buffer system is also provided. | 02-12-2015 |
Hyun Sik Kim, Boise, ID US
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20160005966 | Methods of Forming Structures - Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides. | 01-07-2016 |
Hyuntae Kim, Boise, ID US
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20110223761 | METHODS FOR FABRICATING CONTACTS OF SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR DESIGNING SEMICONDUCTOR DEVICE STRUCTURES - Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch. | 09-15-2011 |
Kang Y. Kim, Boise, ID US
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20090179676 | LOCAL COARSE DELAY UNITS - One delay locked loop circuit embodiment includes a delay line system configured to generate a clock output signal by adding a delay line system time delay to a clock reference signal, a phase detector, a shift register, and a control unit. The delay line system includes a coarse delay line to adjust the delay line system time delay by remote coarse-shifting, a phase selector configured to adjust the delay line system time delay by local coarse-shifting output signals from a series of local coarse delay units, and a phase mixer to adjust a particular time delay of the clock output signal by fine-shifting. The phase mixer does not receive the clock reference signal. The phase detector detects a phase difference between the clock reference signal and the clock output signal. The shift register controls the remote coarse-shifting, and the control unit controls the local coarse-shifting, based on the phase difference. | 07-16-2009 |
20100244916 | SELF-TIMED FINE TUNING CONTROL - A delay lock loop having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop. | 09-30-2010 |
Kangyong Kim, Boise, ID US
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20100118588 | VOLTAGE REFERENCE GENERATION FOR RESISTIVE SENSE MEMORY CELLS - Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor. | 05-13-2010 |
20100246250 | Pipeline Sensing Using Voltage Storage Elements to Read Non-Volatile Memory Cells - Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs. | 09-30-2010 |
Tae H. Kim, Boise, ID US
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20130039132 | LINE DRIVER CIRCUITS, METHODS, AND APPARATUSES - Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed. | 02-14-2013 |
20140313810 | SWITCHABLY COUPLED DIGIT LINE SEGMENTS IN A MEMORY DEVICE - A memory array includes segmented global and local digit lines in which the global digit line segments are switchably coupled to one of a plurality of local digit line segments at a time. A sense circuit coupled to a global digit line segment can be switched to sense memory cells coupled to one of the plurality of local digit lines at a first time and memory cells coupled to a second one of the plurality of local digit lines at a second time. Neither the global digit line segments nor the local digit line segments extend through the entire memory array. | 10-23-2014 |
20150117124 | DATA LINE CONTROL FOR SENSE AMPLIFIERS - Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described. | 04-30-2015 |
Young Pil Kim, Boise, ID US
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20100173456 | Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates - The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated. | 07-08-2010 |
20110124168 | Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates - The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated. | 05-26-2011 |