Patent application number | Description | Published |
20100055568 | TRANSITION METAL OXIDES/MULTI-WALLED CARBON NANOTUBE NANOCOMPOSITE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a transition metal oxide/multi-walled carbon nanotube nanocomposite and its preparation method, and particularly to a nanocomposite prepared in a composite form of an electron-transmitting and stress-relaxing one-dimensional multi-walled carbon nanotube (MWCNT) and a high-capacity-enabling zero-dimensional nanopowder-type transition metal oxide, where a transition metal oxide prepared by urea synthesis is uniformly dispersed in a carbon nanotube by a surfactant, and its preparation method. | 03-04-2010 |
20110165461 | ELECTRODE INCLUDING NANOCOMPOSITE ACTIVE MATERIAL, METHOD OF PREPARING THE SAME, AND ELECTROCHEMICAL DEVICE INCLUDING THE SAME - The present invention provides an electrode and a method of preparing the same. The electrode of the present invention is prepared by forming a nanostructured conductor comprising a metal or metal oxide on a substrate and forming an active material comprising metal oxide nanoparticles on the surface of the nanostructured conductor. The electrode of the present invention can be used in various electrochemical devices such as energy storage devices including secondary batteries, supercapacitors, etc., photocatalyst elements, thermoelectric elements, or composite elements thereof. Moreover, the electrode of the present invention can be applied to a lithium secondary battery, in which intercalation/deintercalation of lithium ions is performed, and especially applied to a negative electrode of the lithium secondary battery. | 07-07-2011 |
20120202675 | LOW TEMPERATURE CO-FIRED CERAMICS WITH LOW DIELECTRIC LOSS FOR MILLIMETER-WAVE APPLICATION - Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO | 08-09-2012 |
Patent application number | Description | Published |
20110123419 | METHOD FOR PREPARING MANGANESE SULFATE AND ZINC SULFATE FROM WASTE BATTERIES CONTAINING MANGANESE AND ZINC - A method for preparing manganese sulfate and zinc sulfate from waste batteries containing manganese and zinc, and more particularly to a method for preparing manganese sulfate and zinc sulfate from waste batteries containing manganese and zinc. Zinc powder and activated carbon are added to a leached solution obtained from a continuous leaching process so as to remove heavy metals and organic materials from the leached solution, and then the leached solution is spray-dried to simultaneously obtain manganese sulfate and zinc sulfate at high-purity by a simple process without generating wastewater. An environmentally friendly waste battery recycling process is thereby provided, because it is not required to use additional chemical substances for neutralization titration or impurity removal in recovering manganese sulfate and zinc sulfate by leaching a waste battery powder. | 05-26-2011 |
20120046159 | METHOD FOR RECOVERY OF COBALT AND MANGANESE FROM SPENT COBALT-MANGANESE-BROMINE (CMB) CATALYST AND METHOD FOR PRODUCING CMB CATALYST INCLUDING THE RECOVERY METHOD - Disclosed is a method for recovering cobalt and manganese from a spent cobalt-manganese-bromine (CMB) catalyst. The method includes (a) continuously leaching a spent CMB catalyst with sulfuric acid, (b) separating the leachate into a solution and a residue, (c) extracting the solution with a solvent, and (d) washing the extract with water. According to the method, high-purity cobalt and manganese can be recovered in high yield from a spent CMB catalyst while minimizing the amount of impurities. Further disclosed is a method for producing a CMB liquid catalyst from the extract containing cobalt and manganese obtained by the recovery method. | 02-23-2012 |
20130312254 | METHOD FOR MANUFACTURING A VALUABLE-METAL SULFURIC-ACID SOLUTION FROM A WASTE BATTERY, AND METHOD FOR MANUFACTURING A POSITIVE ELECTRODE ACTIVE MATERIAL - The present invention relates to a method for manufacturing a valuable-metal sulfuric-acid solution from a waste battery, and to a method for manufacturing a positive electrode active material. The method for manufacturing the valuable-metal sulfuric-acid solution includes: a step of obtaining valuable-metal powder containing lithium, nickel, cobalt, and manganese from waste batteries; a step of acid-leaching the valuable-metal powder under a reducing atmosphere in order to obtain a leaching solution; and a step of separating the lithium from the leaching solution so as to obtain a sulfuric-acid solution containing the nickel, cobalt, and manganese. | 11-28-2013 |
Patent application number | Description | Published |
20080217789 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced. | 09-11-2008 |
20090073667 | Semiconductor chip package and printed circuit board - A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip. | 03-19-2009 |
20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
20100144152 | Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer. | 06-10-2010 |
20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
20100159646 | Method of manufacturing wafer level package - The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units. | 06-24-2010 |
20110201156 | Method of manufacturing wafer level package including coating resin over the dicing lines - A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units. | 08-18-2011 |
20110309524 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced. | 12-22-2011 |
20120073861 | PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer. | 03-29-2012 |
20120086057 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors. | 04-12-2012 |
20140063968 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation. | 03-06-2014 |
20140345916 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via. | 11-27-2014 |
Patent application number | Description | Published |
20100291533 | INDOLE AND INDAZOLE DERIVATIVES HAVING A CELL-, TISSUE- AND ORGAN-PRESERVING EFFECT - The present invention relates to a composition for preserving cells, tissues and organs, comprising as an active ingredient indole and indazole compounds of formula (1), or a pharmaceutically acceptable salt or isomer thereof, which are effective for preventing injury of organs, isolated cell systems or tissues caused by cold storage, transplant operation or post-transplantation reperfusion; a preservation method; and a preparation method of the composition. | 11-18-2010 |
20120270203 | INDOLE AND INDAZOLE DERIVATIVES HAVING A CELL-, TISSUE- AND ORGAN-PRESERVING EFFECT - The present invention relates to a composition for preserving cells, tissues and organs, comprising as an active ingredient indole and indazole compounds of formula (1), or a pharmaceutically acceptable salt or isomer thereof, which are effective for preventing injury of organs, isolated cell systems or tissues caused by cold storage, transplant operation or post-transplantation reperfusion; a preservation method; and a preparation method of the composition. | 10-25-2012 |