Patent application number | Description | Published |
20110303274 | SOLAR CELLS WITH PLATED BACK SIDE SURFACE FIELD AND BACK SIDE ELECTRICAL CONTACT AND METHOD OF FABRICATING SAME - The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer. | 12-15-2011 |
20120295390 | SINGLE-CRYSTALLINE SILICON ALKALINE TEXTURING WITH GLYCEROL OR ETHYLENE GLYCOL ADDITIVES - Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed. | 11-22-2012 |
20120305066 | USE OF METAL PHOSPHORUS IN METALLIZATION OF PHOTOVOLTAIC DEVICES AND METHOD OF FABRICATING SAME - A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided. | 12-06-2012 |
20120318341 | PROCESSES FOR UNIFORM METAL SEMICONDUCTOR ALLOY FORMATION FOR FRONT SIDE CONTACT METALLIZATION AND PHOTOVOLTAIC DEVICE FORMED THEREFROM - Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided. In one embodiment, a method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate; forming a plurality of patterned antireflective coating layers on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger regions; forming a mask atop the plurality of patterned antireflective coating layers, the mask having a shape that mimics each patterned antireflective coating; electrodepositing a metal layer on the busbar region and the finger regions; removing the mask; and performing an anneal, wherein during the anneal metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy. | 12-20-2012 |
20120325312 | SOLAR CELLS WITH PLATED BACK SIDE SURFACE FIELD AND BACK SIDE ELECTRICAL CONTACT AND METHOD OF FABRICATING SAME - The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer. | 12-27-2012 |
20120329200 | SILICON SURFACE TEXTURING METHOD FOR REDUCING SURFACE REFLECTANCE - A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis. | 12-27-2012 |
20130014812 | PHOTOVOLTAIC DEVICE WITH ALUMINUM PLATED BACK SURFACE FIELD AND METHOD OF FORMING SAMEAANM Fisher; Kathryn C.AACI BrooklynAAST NYAACO USAAGP Fisher; Kathryn C. Brooklyn NY USAANM Huang; QiangAACI Sleepy HollowAAST NYAACO USAAGP Huang; Qiang Sleepy Hollow NY USAANM Papa Rao; Satyavolu S.AACI PoughkeepsieAAST NYAACO USAAGP Papa Rao; Satyavolu S. Poughkeepsie NY USAANM Yeh; Ming-LingAACI BaltimoreAAST MDAACO USAAGP Yeh; Ming-Ling Baltimore MD US - A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed. | 01-17-2013 |
20140000691 | INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING | 01-02-2014 |
20140000693 | INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING | 01-02-2014 |
20140042360 | SILICON SURFACE TEXTURING METHOD FOR REDUCING SURFACE REFLECTANCE - A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis. | 02-13-2014 |
20140051201 | SILICON SURFACE TEXTURING METHOD FOR REDUCING SURFACE REFLECTANCE - A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis. | 02-20-2014 |
20140183667 | NANOPORE SENSOR DEVICE - A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes. | 07-03-2014 |
20140183668 | NANOPORE SENSOR DEVICE - A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes. | 07-03-2014 |
20140302675 | Nanogap in-between noble metals - A nanogap of controlled width in-between noble metals is produced using sidewall techniques and chemical-mechanical-polishing. Electrical connections are provided to enable current measurements across the nanogap for analytical purposes. The nanogap in-between noble metals may also be formed inside a Damascene trench. The nanogap in-between noble metals may also be inserted into a crossed slit nanopore framework. A noble metal layer on the side of the nanogap may have sub-layers serving the purpose of multiple simultaneous electrical measurements. | 10-09-2014 |
20140374694 | MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION - A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap. | 12-25-2014 |
20140374695 | NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES - An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized. | 12-25-2014 |
20140377900 | MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION - A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap. | 12-25-2014 |
Patent application number | Description | Published |
20080290515 | PROPERTIES OF METALLIC COPPER DIFFUSION BARRIERS THROUGH SILICON SURFACE TREATMENTS - In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer. | 11-27-2008 |
20090001510 | AIR GAP IN INTEGRATED CIRCUIT INDUCTOR FABRICATION - In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via. | 01-01-2009 |
20090085197 | Method of Fabrication of On-Chip Heat Pipes and Ancillary Heat Transfer Components - The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture. | 04-02-2009 |
20090261453 | AIR GAP IN INTEGRATED CIRCUIT INDUCTOR FABRICATION - A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen. | 10-22-2009 |