Patent application number | Description | Published |
20110042685 | SUBSTRATES AND METHODS OF FABRICATING EPITAXIAL SILICON CARBIDE STRUCTURES WITH SEQUENTIAL EMPHASIS - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including epitaxial layers, by supplying sources of silicon and carbon with sequential emphasis. In at least some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer on a substrate in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source, and purging other gaseous materials subsequent to converting the layer. The presence of the silicon source can be independent of the presence of the carbon source. In some embodiments, dopants, such as n-type dopants, can be introduced during the formation of the epitaxial layer of silicon carbide. | 02-24-2011 |
20110042686 | SUBSTRATES AND METHODS OF FABRICATING DOPED EPITAXIAL SILICON CARBIDE STRUCTURES WITH SEQUENTIAL EMPHASIS - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, and methods to form silicon carbide structures, including doped epitaxial layers (e.g., P-doped silicon carbide epitaxial layers), by supplying sources of silicon and carbon with sequential emphasis. In some embodiments, a method of forming an epitaxial layer of silicon carbide can include depositing a layer in the presence of a silicon source, and purging gaseous materials subsequent to depositing the layer. Further, the method can include converting the layer into a sub-layer of silicon carbide in the presence of a carbon source and a dopant, and purging other gaseous materials. In some embodiments, the presence of the silicon source can be independent of the presence of the carbon source and/or the dopant. | 02-24-2011 |
20110272707 | SUBSTRATES AND METHODS OF FORMING FILM STRUCTURES TO FACILITATE SILICON CARBIDE EPITAXY - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form film structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate. In some embodiments, a method of preparing a substrate for silicon carbide epitaxial layer formation can include forming an ultrathin layer of oxide that is configured to inhibit contaminants from interacting with a silicon-based substrate. Further, the method can include forming a carbonized film on the silicon-based substrate that is configured to inhibit contaminants from interacting with the silicon-based substrate. The carbonized film can be configured to be transitory as fabrication parameters are modified to form an epitaxial layer of silicon carbide. | 11-10-2011 |
20120056194 | BARRIER STRUCTURES AND METHODS OF FORMING SAME TO FACILITATE SILICON CARBIDE EPITAXY AND SILICON CARBIDE-BASED MEMORY FABRICATION - Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, substrates, wafers and methods to form barrier structures to facilitate formation of silicon carbide epitaxy on a substrate, such as a silicon-based substrate, for fabricating various silicon carbide-based semiconductor devices, including silicon carbide-based memory elements and cells. In some embodiments, a semiconductor wafer includes a silicon substrate, a barrier-seed layer disposed over the silicon substrate, and a silicon carbide layer formed over the barrier-seed layer. The semiconductor wafer can be used to form a variety of SiC-based semiconductor devices. In one embodiment, a silicon carbide-based memory element is formed to include barrier-seed layer, multiple silicon carbide layers formed over the barrier-seed layer, and a dielectric layer formed over the multiple silicon carbide layers. | 03-08-2012 |
Patent application number | Description | Published |
20100096618 | DOPING OF NANOSTRUCTURES - A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 10 | 04-22-2010 |
20100327319 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 12-30-2010 |
20110045662 | LOW-TEMPERATURE FORMATION OF LAYERS OF POLYCRYSTALLINE SEMICONDUCTOR MATERIAL - The present invention provides a method for forming a layer ( | 02-24-2011 |
20120298961 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 11-29-2012 |
20130119014 | PROTECTIVE TREATMENT FOR POROUS MATERIALS - A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value T | 05-16-2013 |