Patent application number | Description | Published |
20080240325 | High-Speed Receiver Architecture - A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. | 10-02-2008 |
20080310330 | STARTUP PROTOCOL FOR HIGH THROUGHPUT COMMUNICATIONS SYSTEMS - A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase. The protocol then enters a fourth stage in which the master transceiver and the slave transceiver are ready to communicate with each other. | 12-18-2008 |
20090044070 | SYSTEM AND METHOD FOR TRELLIS DECODING IN A MULTI-PAIR TRANSCEIVER SYSTEM - A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword. | 02-12-2009 |
20090052509 | PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER - A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS. | 02-26-2009 |
20090060018 | Transmit Equalizer For Dispersive Channels - An equalizer at the transmitter reduces data-dependent jitter introduced by a non-linear device in the transmitter. In one implementation, the equalizer is T/2-spaced. In an alternate implementation, it is T-spaced. | 03-05-2009 |
20090154536 | STARTUP PROTOCOL FOR HIGH THROUGHPUT COMMUNICATIONS SYSTEMS - A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all converging at startup of the system. The operation of the startup protocol is partitioned into stages. The first stage includes the step of converging the equalizer and the timing recovery system of the slave while converging the noise reduction system of the master. Upon completion of the first stage the protocol enters a second stage which includes the step of converging the equalizer and the timing recovery system of the master, converging the noise reduction system of the slave, freezing the timing recovery system of the slave, and resetting the noise reduction system of the master. Upon completion of the second stage, the protocol enters a third stage which includes the step of reconverging the noise reduction system of the master. The protocol then enters a fourth stage in which the master transceiver and the slave transceiver are ready to communicate with each other. | 06-18-2009 |
20090185613 | High-Speed Receiver Architecture - A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. | 07-23-2009 |
20090238305 | METHOD, APPARATUS AND SYSTEM FOR HIGH-SPEED TRANSMISSION - Multi-carrier modulation systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. Multi-carrier modulation may be applied to existing channels, which may be of lower quality. An adaptive multi-carrier modulation transmitter may characterize an existing channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the channel. A series of adaptive multi-carrier modulation transmitters and receivers can be integrated on a single integrated circuit. If multiple adaptive receivers and transmitters are integrated on a single integrated circuit, they may be used to upgrade existing networks to achieve any capacity desired. Each receiver and transmitter may characterize the channel and may configure the modulation and bandpass to the channel's characteristics. | 09-24-2009 |
20090296791 | Multi-Pair Gigabit Ethernet Transceiver - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 12-03-2009 |
20100086019 | High-Speed Decoder for a Multi-Pair Gigabit Transceiver - A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder. | 04-08-2010 |
20100135371 | DYNAMIC REGULATION OF POWER CONSUMPTION OF A HIGH-SPEED COMMUNICATION SYSTEM - A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern. | 06-03-2010 |
20100135372 | Demodulator for a Multi-Pair Gigabit Transceiver - A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver. | 06-03-2010 |
20100192028 | DIAGNOSTICS OF CABLE AND LINK PERFORMANCE FOR A HIGH-SPEED COMMUNICATION SYSTEM - A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system. | 07-29-2010 |
20100202576 | Apparatus For, and Method of, Reducing Noise in a Communications System - A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal. If necessary, a skew adjuster delays the arrival of the combination signal at the device so that the combination signal and the FEXT impairment signal arrive at the device at substantially the same time. A sequential decoder operates on signals from each of the plurality of wire pairs simultaneously to produce receiver outputs. A plurality of near-end crosstalk (NEXT) cancellation systems and echo cancellers remove NEXT and echo impairment signals from the combination signal. | 08-12-2010 |
20100202775 | METHOD, APPARATUS AND SYSTEM FOR HIGH-SPEED TRANSMISSION ON FIBER OPTIC CHANNEL - Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic channel. A receiver may then receive the laser signal from the fiber optic channel and convert it into an electrical signal. Multi-carrier modulation may be applied to existing fiber channels, which may be of lower quality. Existing fiber channels may have characteristics which prevent or restrict the transmission of data using intensity modulation at certain frequencies. An adaptive multi-carrier modulation transmitter may characterize an existing fiber optic channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the fiber channel. A series of adaptive multi-carrier modulation transmitters and receivers can be integrated on a single integrated circuit. If multiple adaptive receivers and transmitters are integrated on a single integrated circuit, they may be used to upgrade existing networks by adding different wavelength lasers for the transmission of data in order to achieve any capacity desired. Each receiver and transmitter may characterize the fiber for its particular wavelength laser and may configure the modulation and bandpass to the fiber's characteristics. | 08-12-2010 |
20100290551 | METHOD, APPARATUS AND SYSTEM FOR HIGH-SPEED TRANSMISSION ON FIBER OPTIC CHANNEL - Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic channel. A receiver may then receive the laser signal from the fiber optic channel and convert it into an electrical signal. Multi-carrier modulation may be applied to existing fiber channels, which may be of lower quality. Existing fiber channels may have characteristics which prevent or restrict the transmission of data using intensity modulation at certain frequencies. An adaptive multi-carrier modulation transmitter may characterize an existing fiber optic channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the fiber channel. A series of adaptive multi-carrier modulation transmitters and receivers can be integrated on a single integrated circuit. If multiple adaptive receivers and transmitters are integrated on a single integrated circuit, they may be used to upgrade existing networks by adding different wavelength lasers for the transmission of data in order to achieve any capacity desired. Each receiver and transmitter may characterize the fiber for its particular wavelength laser and may configure the modulation and bandpass to the fiber's characteristics. | 11-18-2010 |
20100309963 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING ADAPTIVE DISABLING OF CIRCUIT ELEMENTS - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 12-09-2010 |
20110019724 | PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER - A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals, to the DSP and the PCS. | 01-27-2011 |
20110058596 | Multi-Channel Equalization to Compensate for Impairments Introduced by Interleaved Devices - A system includes a time-interleaved device. An equalizer effectively can apply different equalization to different interleaved channels. For convenience, these equalizers will be referred to as multi-channel equalizers. In one aspect, an apparatus includes an interleaved device having M interleaved channels, and a multi-channel equalizer coupled to the interleaved device. The multi-channel equalizer is capable of applying a different equalization to different interleaved channels, thus compensating for channel-dependent impairments. | 03-10-2011 |
20110064123 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 03-17-2011 |
20110081152 | High-Speed Receiver Architecture - A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. | 04-07-2011 |
20110096824 | MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER - Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized. | 04-28-2011 |
20110206109 | System and Method for High Speed Communications Using Digital Signal Processing - Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs. | 08-25-2011 |
20110211842 | High-Speed Receiver Architecture - A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. | 09-01-2011 |
20120007756 | Digital signal processing based de-serializer - A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device. | 01-12-2012 |
20120027413 | High-Speed Transmission System for Optical Channels - A method and apparatus for transmission of data on bandwidth limited fiber optic channels. A multilevel signaling alphabet having multiple levels of optical intensity are used to transmit signals on optical channels. In order to counteract the decrease in signal to noise ratio resulting from the use of a multilevel signaling alphabet over a bilevel signaling alphabet trellis encoding of the data to be transmitted is employed. To counteract intersymbol interference due to signaling faster than the Nyquist Rate, equalization methods such as Tomlinson-Harashima preceding and decision feedback equalization are employed. | 02-02-2012 |
20120106601 | System and Method for Packet Communication - A system and method for packet communication is disclosed. Echo in a received symbol stream may be reduced to produce an echo-reduced symbol stream. The echo-reduced symbol stream may be buffered according to a propagation delay of the received symbol stream to produce a deskewed symbol stream. The deskewed symbol stream may be decoded to produce a decoded packet. | 05-03-2012 |
20120251098 | Method, apparatus and system for high-speed transmission on fiber optic channel - Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic channel. A receiver may then receive the laser signal from the fiber optic channel and convert it into an electrical signal. Multi-carrier modulation may be applied to existing fiber channels, which may be of lower quality. Existing fiber channels may have characteristics which prevent or restrict the transmission of data using intensity modulation at certain frequencies. An adaptive multi-carrier modulation transmitter may characterize an existing fiber optic channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the fiber channel. A series of adaptive multi-carrier modulation transmitters and receivers can be integrated on a single integrated circuit. If multiple adaptive receivers and transmitters are integrated on a single integrated circuit, they may be used to upgrade existing networks by adding different wavelength lasers for the transmission of data in order to achieve any capacity desired. Each receiver and transmitter may characterize the fiber for its particular wavelength laser and may configure the modulation and bandpass to the fiber's characteristics. | 10-04-2012 |
20120275780 | Receivers Based on Closed-Form Parametric Estimates of the Probability Density Function for the Received Signal - A closed-form parametric approach to channel-estimation is provided. In one aspect, a specific parametric expression is presented for the received signal pdf that accurately models the behavior of the received signal in IM/DD optical channels. The corresponding parametric channel-estimation approach simplifies the design of MLSE receivers. The general technique lends itself well to the estimation of the signal pdf in situations where there are multiple sources of noise with different distributions, such as ASE noise, together with Gaussian and quantization noise, and signal-dependent noise, for example. | 11-01-2012 |