Patent application number | Description | Published |
20100027898 | IMAGE PROCESSING METHOD OF NOISE REDUCTION AND APPARATUS THEREOF - An image processing method of noise reduction and an apparatus thereof are disclosed herein. In the image processing method, a current image having a plurality of image blocks is provided. A first block of the image blocks of the current image is substrate by the first block of at least one previous image for obtaining a difference block. Next, the difference block is performed on a motion detection process for determining whether the first block of the current image is in a static state. When the first block of the current image is in the static state, the first block of the current image is performed on a temporal filtering process for reducing the noise. By analyzing the static state, occurrence of motion blur can be prevented. | 02-04-2010 |
20100321309 | TOUCH SCREEN AND TOUCH MODULE - A touch screen including a display, at least two touch units and a control unit is provided. The display has a displaying surface. The touch units are disposed beside the displaying surface. Each of the touch units includes a light source and an image sensor. The light source is adapted to emit a light beam toward a sensible space in front of the displaying surface. The image sensor is adapted to capture the bright spot in the sensible space, and generate an image signal. The control unit is electrically connected to the light sources and the image sensors. The control unit is adapted to receive the image signals from the image sensors, and determine the position of the bright spot relative to the displaying surface according to the image signals. A touch module and a control method are also provided. | 12-23-2010 |
20140362179 | IMAGE DEVICE FOR DETERMINING AN INVALID DEPTH INFORMATION OF A DEPTH IMAGE AND OPERATION METHOD THEREOF - An image device for determining an invalid depth information of a depth image includes a first sensor, a second sensor, a pre-processing module, a depth map engine, and an error determination unit. The first sensor captures first images and the second sensor captures second images. The pre-processing module generates a reference image according to each first image of the first images and a target image corresponding to the reference image according to a second image of the second images. The depth map engine generates a first depth image according to the reference image and the target image. The error determination unit sets gray level values of pixels of invalid areas of the first depth image to be a predetermined value to generate a second depth image, wherein pixels of the second depth image with the predetermined value have the invalid depth information. | 12-11-2014 |
20140363097 | IMAGE CAPTURE SYSTEM AND OPERATION METHOD THEREOF - An image capture system includes a depth information generation unit, a feature extraction unit, and a merging unit. The depth information generation unit generates a depth information corresponding to at least one object of an original image. The feature extraction unit generates a feature information corresponding to the at least one object of the original image. The merging unit is coupled to the depth information generation unit and the feature extraction unit, and merges the depth information and the feature information into a feature depth map and outputs the feature depth map to an application unit. | 12-11-2014 |
Patent application number | Description | Published |
20110141412 | COLOR SEPARATION SYSTEM - A color separation system is disclosed, which comprises: a backlight source, being highly collimated and used for providing an incident beam; a color separation module, formed with a first color separation film for separating the incident beam basing on wavelength while deflecting the optical paths of the resulting split beams; and a beam splitting module, being configured with at least one beam splitting plate and a liquid crystal layer; wherein, the at least one beam splitting plate is used for converging the beams from the color separation module while deflecting the optical paths thereof for enabling those to be discharged thereout following a normal direction of a light emitting surface of the backlight source. | 06-16-2011 |
20110242457 | COMPOSITE COLOR SEPARATION SYSTEM - A composite color separation system, comprises: a light control module, a light guide module and a light splitting module. The light control module has a lighting unit and a lens unit, in which the lighting unit includes an array of lighting elements whereas there are at least two types of lighting elements in the array for emitting at least two beams of different wavelengths. The light from the lighting unit is directed to enter the lens unit before being discharged out of the light control module. The light guide module comprises: a first light incident surface, for receiving the beams from the light control module; a first light emergence surface; and a light guide structure, for guiding the beams to the first light emergence surface where they are discharged out of the light guide module to the light splitting module. The light splitting module is used for splitting the beams. | 10-06-2011 |
20120218776 | COMPOSITE COLOR SEPARATION SYSTEM - A color separation system is disclosed, which comprises: a wavelength distribution module, a light guide module and a light splitting module. The wavelength distribution module includes at least one lighting unit and at least one lens unit, in which each lighting unit emits at least two beams of different wavelengths. The plurality of beams is directed to enter the lens unit before it is discharged out of the wavelength distribution module. After that, the plural beams from the wavelength distribution module enters the light guide module. The portion of those beams that are being absorbed, while the portion of those beams being discharged out of the light guide module and then enter the light splitting module. The light splitting module is functioned for splitting the plural beams. | 08-30-2012 |
Patent application number | Description | Published |
20100073310 | LIGHT TRANSMISSION TOUCH PANEL - A light transmission touch panel comprises a transparent substrate, a transparent conductive layer, an insulating layer, a plurality of first metal lines, and a plurality of second metal lines. The transparent conductive layer is overlaid on a surface of the transparent substrate and comprises a plurality of first cells, a plurality of second cells and a plurality of connecting lines, wherein the plurality of first cells and the plurality of second cells are arranged in a staggered manner and the plurality of connecting lines respectively connect the adjacent second cells. The insulating layer further comprises a plurality of insulating areas, each of which is overlaid on one of the first cells. The plurality of second metal lines are respectively disposed on the connecting lines. The plurality of first metal lines are respectively disposed on the plurality of insulating areas, and respectively connect the adjacent first cells. | 03-25-2010 |
20110018838 | Capacitive Type Touch Panel - A capacitive type touch panel comprises a transparent substrate, a transparent conductive layer, an insulating layer, and a plurality of first leads. The transparent conductive layer is overlaid on a surface of the transparent substrate and comprises a plurality of first electrodes, a plurality of second electrodes and a plurality of connecting lines. The plurality of first electrodes and the plurality of second electrodes are arranged in a staggered manner, and the plurality of connecting lines respectively connect two adjacent second electrodes. The insulating layer comprises a plurality of insulating areas, wherein the plurality of insulating areas are respectively overlaid on the plurality of connecting lines. The plurality of first leads are respectively disposed on the plurality of insulating areas and respectively connect two adjacent first electrodes. Each of the first electrodes and second electrodes has a pattern which is formed by transparent electrode leads. | 01-27-2011 |
Patent application number | Description | Published |
20090289908 | TOUCH DETECTING DEVICE CAPABLE OF SAVING ELECTRICITY - A touch detecting device capable of saving power for a touch panel includes a touch sensing unit, a micro control unit and a mode detecting unit. The touch sensing unit is coupled to the touch panel and used for being triggered by a first control signal to generate sensing data according to a touch state of the touch panel. The micro control unit is coupled to the touch sensing unit and used for being triggered by a second control signal to generate the first control signal. The mode detecting unit is coupled to the micro control unit and the touch panel, and used for generating the second control signal according to the touch state of the touch panel. | 11-26-2009 |
20110068709 | LIGHTING DEVICE, LIGHTING PANEL AND CIRCUIT BOARD THEREOF - A lighting device, a lighting panel and a circuit board thereof are provided. The circuit board comprises a substrate; a plurality of light sources disposed on the substrate and at least one circuit layer, being patterned onto the substrate to form a plurality of traces for electrically connecting the light sources. Therein, the circuit board is capable of being assembled with other circuit boards to construct the lighting panel. The lighting device is capable of having the lighting panel of a large size by assembling a plurality of the circuit boards and individually controlling each light source disposed on the lighting panel so as to provide the function of local dimming. | 03-24-2011 |
20130278589 | DISPLAY CONTROL SYSTEM - A display control system includes a display unit, a timing control unit. The display unit includes at least one source driving unit and a gate driving unit. The source driving unit includes an output buffer unit, a plurality of switches and a register unit. The output buffer unit is used to output image signals or high impedance signals. The switches are used to receive the image signals or high impedance signals. The gate driving unit is used to output gate driving signals. The timing control unit is used for controlling the timing of the source driving unit and the gate driving unit. | 10-24-2013 |
Patent application number | Description | Published |
20100115188 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block; and determining whether to erase a portion of the blocks according to the usage information. For example, the usage information includes a valid page count table for recording valid page counts of the blocks, respectively; and the ranking of a field of the valid page count table represents a physical block address, and the content of the field represents an associated valid page count. In another example, the usage information includes an invalid page count table for recording invalid page counts of the blocks, respectively; and the ranking of a field of the invalid page count table represents a physical block address, and the content of the field represents an associated invalid page count. | 05-06-2010 |
20100115189 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. | 05-06-2010 |
20100306455 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: sieving out at least one first block having invalid pages from the plurality of blocks; and moving data of a portion of valid pages of the first block to a second block, where data of all valid pages of the first block is not moved to the second block at a time. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. The controller that executes the program code by utilizing the microprocessor sieves out the first block from the plurality of blocks, and moves the data of the portion of valid pages of the first block to the second block. | 12-02-2010 |
20110087828 | METHOD FOR ENHANCING PERFORMANCE OF ACCESSING A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of accessing a Flash memory, which includes a plurality of blocks and is positioned in a memory device, includes: during writing data into the Flash memory, establishing/updating at least one linking table in a random access memory (RAM) of the memory device, wherein regarding the Flash memory, the linking table indicates linking relationships between logical addresses and physical addresses, or indicates linking relationships between physical addresses and logical addresses; and writing the linking table into the Flash memory only when it is detected that a flush cache command is sent from a host device. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. | 04-14-2011 |
20110093649 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: providing at least one logical-to-physical block linking table within the Flash memory, wherein regarding a plurality of logical block addresses, the logical-to-physical block linking table initially stores at least one initial value falling outside a range of respective physical block addresses of the Flash memory to prevent the logical block addresses from being initially linked to the physical block addresses; and when it is required to write data belonging to a logical block address into the Flash memory, writing a physical block address of the physical block addresses into an updated version of the logical-to-physical block linking table in order to link the logical block address to the physical block address. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM; and a microprocessor. | 04-21-2011 |
20120221782 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block, for use of managing the memory apparatus. For example, the method may further include: determining whether to erase a portion of blocks according to the usage information, where the usage information may include a valid/invalid page count table for recording valid/invalid page counts of the blocks, respectively. In another example, the method may further include: erasing at least a particular block of the blocks according to the usage information, where the usage information may include count information for representing valid/invalid page counts of the particular block, or include page count information for representing a number of effectively linked page of the particular block. Associated memory apparatus are also provided. | 08-30-2012 |
20120221829 | METHOD FOR MANAGING A MEMORY APPARATUS - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid. | 08-30-2012 |
20120331215 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table includes linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. More particularly, the step of providing the block with the local page address linking table further includes: building a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus; and temporarily storing the temporary local page address linking table in a volatile memory of the memory apparatus, and updating the temporary local page address linking table when needed. | 12-27-2012 |
20120331216 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the at least one local page address linking table includes linking relationships between at least one physical page address of the at least one block and at least one logical page address; and building a global page address linking table of the memory apparatus according to the at least one local page address linking table. | 12-27-2012 |
20120331263 | METHOD FOR MANAGING A MEMORY APPARATUS - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: building at least one local page address linking table containing a page address linking relationship between a plurality of physical page addresses and at least a logical page address, wherein the local page address linking table includes a first local page address linking table containing a first page address linking relationship of a plurality of first physical pages, and a second local page address linking table containing a second page address linking relationship of a plurality of second physical pages that are different from the first physical pages; building a global page address linking table according to the local page address linking table; and accessing the memory apparatus according to the global page address linking table. | 12-27-2012 |
20120331267 | METHOD FOR MANAGING A MEMORY APPARATUS - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: receiving a first access command from a host; analyzing the first access command to obtain a first host address; linking the first host address to a physical block; receiving a second access command from the host; and analyzing the second access command to obtain a second host address. For example, the method may further include: linking the second host address to the physical block, wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block. In another example, the method may further include: linking the first host address to at least a page of the physical block; and linking the second host address to at least a page of another physical block. | 12-27-2012 |
Patent application number | Description | Published |
20090242900 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention discloses a memory device and method thereof. The memory device comprises a substrate, an insulator layer, a first conducting layer, a CaCu | 10-01-2009 |
20120267596 | NON-VOLATILE MEMORY - An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer. | 10-25-2012 |
20140203237 | SELF-RECTIFIED DEVICE, METHOD FOR MANUFACTURING THE SAME, AND APPLICATIONS OF THE SAME - A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property. | 07-24-2014 |
Patent application number | Description | Published |
20080252236 | Method and Device Capable of Controlling Soft-start Dynamically - A back light boost converter includes an analog circuit, an enable controller, a logic device, and a digital PWM controller. The analog circuit generates a switch signal and a feedback signal based on a first pulse signal. The enable controller generates an enable signal based on an LED on ratio signal, an LED on cycle signal, a duty cycle signal, and a frequency signal. The logic device generates a second pulse signal based on the feedback signal and the enable signal. The digital PWM controller outputs the first pulse signal with increasing duty cycles in a plurality stages. | 10-16-2008 |
20080278426 | Method and Apparatus for Driving LCD Panel for Displaying Image Data - A method for driving an LCD panel for displaying image data includes generating a random code sequence including a plurality of random codes with values equal to a first value or a second value, generating a plurality of driving voltages corresponding to a plurality of pixels in the LCD panel according to the image data, adjusting polarities of the plurality of driving voltages according to the random code sequence, and driving the plurality of pixels with the plurality of driving voltages after polarity adjustment. | 11-13-2008 |
20120194532 | CONTROL METHOD FOR BI-STABLE DISPLAYING, TIMING CONTROLLER, AND BI-STABLE DISPLAY DEVICE WITH SUCH TIMING CONTROLLER - A control method for bi-stable displaying is provided, using queues for storing coordinates to achieve pipeline parallel processing on display data, thereby increasing display speed. In a preceding stage of the display process, because a plurality of queues may be used for temporarily storing part of the display data which is then reconstructed into complete display data to update a current frame buffer, comparing pixel data and generating driving data can be simultaneously preformed upon a plurality of line segments. Moreover, in a succeeding stage of the display process, a similar process may be performed to update a previous frame buffer, so access time can be reduced and errors caused by overlapping image blocks can also be avoided. Furthermore, the method may be also applied to a timing controller and a bi-stable display device. | 08-02-2012 |
20120206467 | DRIVING METHOD FOR BISTABLE DISPLAY DEVICE AND DRIVING DEVICE THEREOF - A driving method adapted to a bistable display including a display panel is provided. The driving method includes following steps. A first area data and a second area data respectively received are sequentially stored in a first queue and a second queue, respectively. A first area image corresponding to the first area data and a second area image corresponding to the second area data are sequentially calculated. The first area image is displayed on the display panel during a first frame period of a first period, and the second area image is displayed on the display panel during a second first frame period of the first period. After the first period, the first area image on the display panel is in a stable state. After a summation time of first period and the second frame period, the second area image on the display panel is in a stable state. | 08-16-2012 |
Patent application number | Description | Published |
20110140067 | RESISTANCE SWITCHING MEMORY - A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode. | 06-16-2011 |
20130105758 | MEMORY CELL OF RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF | 05-02-2013 |
20130170278 | RESISTIVE RANDOM ACCESS MEMORY CELL AND RESISTIVE RANDOM ACCESS MEMORY MODULE - A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided. | 07-04-2013 |
20140077149 | RESISTANCE MEMORY CELL, RESISTANCE MEMORY ARRAY AND METHOD OF FORMING THE SAME - A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer. | 03-20-2014 |
20150021542 | MEMORY CELL OF RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer. | 01-22-2015 |
Patent application number | Description | Published |
20090161901 | ULTRA THIN PACKAGE FOR ELECTRIC ACOUSTIC SENSOR CHIP OF MICRO ELECTRO MECHANICAL SYSTEM - An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed. | 06-25-2009 |
20100150381 | MICRO-SPEAKER AND MANUFACTURING METHOD THEREOF - A micro-speaker and a manufacturing method thereof are provided. The micro-speaker has a sandwich structure. The micro-speaker includes two piezoelectric material layers and a diaphragm disposed between the two piezoelectric material layers, where the piezoelectric material layers have a ring-shaped structure. The problem of insufficient sound pressure at low frequency is resolved, and the flexibility of the micro-speaker is improved. | 06-17-2010 |
20100166214 | ELECTRICAL APPARATUS, AUDIO-RECEIVING CIRCUIT AND METHOD FOR FILTERING NOISE - An electronic apparatus at least including an audio-receiving circuit is provided. The audio-receiving circuit includes an audio receiver and a processor. The audio receiver receives a sound wave from a sound source, and generates a first audio signal containing a plurality of noises to the processor. The processor performs a signal processing of time reversal to the first audio signal to restore a sound sent at an original sound source, so as to filter noises in the first audio signal and output a second audio signal. | 07-01-2010 |
20120146163 | MICROPHONE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A microphone package structure is provided, including an integrated circuit (IC) structure and a microphone structure disposed thereover and electrically connected therewith. The IC structure includes a first semiconductor substrate with opposite first and second surfaces, and a first through hole disposed in and through the first semiconductor substrate. The microphone structure includes: a second semiconductor substrate with opposite third and fourth surfaces, wherein the third surface faces to the second surface of the first semiconductor substrate; a second through hole disposed in and through the second semiconductor substrate; an acoustic sensing device embedded in the second through hole and adjacent to the third surface; and a sealing layer disposed over the fourth surface of the second semiconductor substrate, defining a back chamber with the sealing layer, wherein the first through hole allows acoustic pressure waves to penetrate and pass therethrough to the acoustic sensing device. | 06-14-2012 |
20130140655 | MEMS ACOUSTIC TRANSDUCER AND METHOD FOR FABRICATING THE SAME - A MEMS acoustic transducer is provided, which includes a substrate, a MEMS chip, and a housing. The substrate has a first opening area and a lower electrode layer disposed over a surface of the substrate, wherein the first opening area includes at least one hole allowing acoustic pressure to enter the MEMS acoustic transducer. The MEMS chip is disposed over the surface of the substrate, including a second opening area and an upper electrode layer partially sealing the second opening area, wherein the upper electrode layer and the lower electrode layer, which are parallel to each other and have a gap therebetween, form an induction capacitor. The housing is disposed over the MEMS chip or the surface of the substrate creating a cavity with the MEMS chip or the substrate. In addition, a method for fabricating the above MEMS acoustic transducer is also provided. | 06-06-2013 |
20130160554 | CAPACITIVE TRANSDUCER MANUFACTURING METHOD, AND MULTI-FUNCTION DEVICE - A capacitive transducer and manufacturing method thereof is provided. A multifunction device including a plurality of the capacitive transducers is also provided, where the capacitive transducers are disposed on a substrate and include at least one microphone and at least one pressure sensor or ultrasonic device. | 06-27-2013 |
Patent application number | Description | Published |
20110169801 | DRIVING APPARATUS OF DISPLAY - A driving apparatus of a display is disclosed. The driving apparatus mentioned above includes a digital-to-analog converter circuit and an output buffer circuit. The digital-to-analog converting circuit receives a display data with a digital format for generating a gray-level voltage. The output buffer circuit has an output terminal to output an output signal. The output buffer circuit receives the gray-level voltage, a pre-charge enable signal and the output signal and provides a pre-charge output signal to the output terminal of the output buffering circuit according to the pre-charge enable signal and a comparison result of the gray-level voltage and the output signal. | 07-14-2011 |
20120288046 | Signal Calibration Method and Client Circuit and Transmission System Using the Same - A signal calibration method for synchronizing a clock signal and at least one data signal in a transmission system is disclosed. The signal calibration method comprises detecting at least one transmission time difference between the clock signal and the at least one data signal transmitted in the transmission system, calculating a plurality of delay periods of the clock signal and the at least one data signal according to the at least one transmission time difference, and respectively delaying the clock signal and the at least one data signal for the plurality of delay periods to synchronize the clock signal and the at least one data signal. | 11-15-2012 |
20120294401 | METHOD OF CALIBRATING SIGNAL SKEWS IN MIPI AND RELATED TRANSMISSION SYSTEM - In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship. | 11-22-2012 |
20130285999 | DRIVING APPARATUS OF DISPLAY - A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and receives the gray level voltage. The output buffer circuit has an output terminal to output a driving output signal. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal according to the gray level voltage and a pre-charge enable signal, and outputs the pre-charge output signal to the output terminal of the output buffer circuit. | 10-31-2013 |
20150015566 | DRIVING APPARATUS OF DISPLAY - A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (DAC) circuit, an output buffer circuit and a pre-charge circuit. The DAC circuit receives a display data with a digital format for generating a gray level voltage. The output buffer circuit is coupled to the DAC circuit, and has an output terminal to output an output signal. The output buffer circuit receives the gray level voltage and the output signal, and compares the gray level voltage and the output signal to generate a comparison result. The pre-charge circuit is coupled to the output buffer circuit, and generates a pre-charge output signal to the output terminal of the output buffer circuit according to the comparison result and a pre-charge enable signal. | 01-15-2015 |
Patent application number | Description | Published |
20080209063 | SYSTEM AND GENERATION METHOD OF REMOTE OBJECTS WITH NETWORK STREAMING ABILITY - A system of remote objects with network streaming ability includes a streaming client, a plurality of streaming servers, a streaming buffer area, a plurality of first continuous buffer areas, a streaming controller, a plurality of first network connections, and a plurality of second network connections. The plurality of streaming servers is used to respond a remote procedure call from the streaming client. The streaming buffer area stores a complete data unit for the streaming client to access. A generation method of remote objects with network streaming ability is further provided. The method includes executing a link procedure, executing a streaming preparation, executing a streaming transfer procedure, and closing the link procedure. | 08-28-2008 |
20090043620 | METHOD FOR COPY PROPAGATIONS FOR A PROCESSOR - A method for copy propagations of a processor including two clusters, each cluster comprising a first function unit and a second function unit, a first local register file and a second local register file being respectively accessible by the first and second function unit only, and a global register file having a ping-pong structure to access the first and second local register files, the method comprising the steps of: (a) listing possible copy propagation paths between two nodes of a data flow graph; (b) calculating a profit of machine cycles for each of the copy propagation paths according to constraints of the processor; and (c) performing a copy propagation through the copy propagation path if the profit thereof is greater than a threshold value. | 02-12-2009 |
20110083133 | METHOD OF STREAMING REMOTE PROCEDURE INVOCATION FOR MULTI-CORE SYSTEMS - A method of streaming remote procedure invocation for multi-core systems to execute a transmitting thread and an aggregating thread of a multi-core system comprises the steps of: temporarily storing data to be transmitted; activating the aggregating thread if the amount of the temporarily stored data is equal to or greater than a threshold and the aggregating thread is at pause status; pausing the transmitting thread if there is no space to temporarily store the data to be transmitted; retrieving data to be aggregated; activating the transmitting thread if the amount of the data to be aggregated is less than a threshold and the transmitting thread is at pause status; and pausing the aggregating thread if there is no data to be retrieved. | 04-07-2011 |
Patent application number | Description | Published |
20090213952 | METHOD FOR DEINTERLEAVING OFDM SIGNALS AND APPARATUS USING THE SAME - An apparatus for deinterleaving OFDM signals comprises a block deinterleaving memory, a computing module, a processed-tone buffer and a subcarrier rotator. The block deinterleaving memory is configured to store unprocessed symbols of the OFDM signals. The computing module is configured to access the block deinterleaving memory in accordance with the order of a first interleaving action for the OFDM signals and to compute thereafter. The processed-tone buffer is configured to store processed symbols of the OFDM signals. The subcarrier rotator is configured to access the processed-tone buffer and to perform a second interleaving action for the OFDM signals. | 08-27-2009 |
20110032916 | WIRELESS COMMUNICATION APPARATUS AND METHOD USING THE SAME - The present invention discloses a wireless communication method for transceiving packets in wireless networks. The method comprises the steps of: transmitting a first packet with a first packet format, wherein a header of the first packet with the first packet format comprises information of a first communication duration; and performing a communication procedure during the first communication duration for transmitting at least one second packet with a second format, for receiving at least one third packet with the second format, or for both transmitting the at least one second packet and receiving the at least one third packet. | 02-10-2011 |
20110217938 | Wireless Transceiver Device and Control Method - A wireless transceiver device used in an electronic device for preventing wireless signal interference includes a plurality of wireless modules for processing wireless signals of a plurality of wireless communication systems, and a control module for adjusting receiving sensitivities or output powers of the plurality of wireless modules, to prevent signals outputted from a wireless module of the plurality of wireless modules from affecting operations of other wireless modules. | 09-08-2011 |
Patent application number | Description | Published |
20110179323 | Memory with Self-Test Function and Method for Testing the Same - The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources. | 07-21-2011 |
20120304032 | TEST SYSTEM - A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit. | 11-29-2012 |
20130282318 | ESTIMATION APPARATUS AND METHOD FOR ESTIMATING CLOCK SKEW - A method for estimating a clock skew between a first clock and a second clock. The method includes the steps of detecting the clock skew to generate a detection resultant signal representing the clock skew; and determining time unit of a signal processing process, and estimating the clock skew according to the time unit of the signal processing process and the detection resultant signal. | 10-24-2013 |
20140091812 | METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHINE READABLE MEDIA THEREOF - A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file. | 04-03-2014 |
20140129885 | SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF - An exemplary scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test includes: a receiving circuit, arranged for receiving an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit and arranged for generating the on-chip scan clocks according to the received off-chip scan clock; wherein clock edges of the on-chip scan clocks are staggered from each other, and the scan clock generator and the cells under test are set in a same chip. | 05-08-2014 |
20150022242 | Clock edge detection device and method - The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels. | 01-22-2015 |
Patent application number | Description | Published |
20110128796 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line. | 06-02-2011 |
20110273951 | MEMORY CIRCUIT AND METHOD FOR CONTROLLING MEMORY CIRCUIT - A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage. | 11-10-2011 |
Patent application number | Description | Published |
20090144457 | Plug and Play Device and Related Installing Method - A plug-and-play device is disposed for installing onto a computer. The plug-and-play device includes an ATA controller, a storage device, and a predetermined-function device. The ATA controller emulates a storage drive inserted in the computer to the OS of the computer. The OS continuously examines if the emulated storage drive is ready and when the emulated storage is drive ready, the OS reads the image of the emulated storage drive. The storage device stores the image of the emulated storage drive. The image includes a setup file and an auto-run file. The auto-run file includes an index indexing to the setup file. When the OS reads the auto-run file, the OS installs the setup file according to the index of the auto-run file. | 06-04-2009 |
20100023662 | BUS MASTERING METHOD - A mastering method of a bus includes the following steps: receiving a command; determining if the command is a bus master command to generate a determined result; outputting at least one break event to switch a processor from a non-snoop state into a snoop state according to the determined result; and outputting at least one bus master request to access the bus; wherein the break event is ahead of the bus master request that corresponds to the break event. | 01-28-2010 |
20100023668 | COMPUTER SYSTEM HAVING MULTI-FUNCTION CARD READER MODULE WITH PCI EXPRESS INTERFACE - A computer system includes a host, a PCI Express bus and a multi-function card reader module. The PCI Express bus is coupled to the host. The multi-function card reader module includes a plurality of card readers, a PCI Express interface and a PCI Express host controller. The plurality of card readers correspond to a plurality of memory card formats, respectively. The PCI Express interface is coupled to the PCI Express bus. The PCI Express host controller is coupled to the PCI Express interface and the plurality of card readers for controlling data transmission between the PCI Express interface and the plurality of card readers. | 01-28-2010 |
20100023669 | HOST CONTROLLER DISPOSED IN MULTI-FUNCTION CARD READER - A host controller disposed in a multi-function card reader includes: a Serial Advanced Technology Attachment (SATA) interface configured for coupling to a host computer; and a port multiplier having a control port and a plurality of peripheral device ports. The control port is coupled to the SATA interface, and the peripheral device ports are coupled to a plurality of peripheral device interfaces, respectively. The peripheral device interfaces are disposed in the multi-function card reader, and include at least one flash memory card interface. | 01-28-2010 |
20100023789 | Host device with power-saving function - A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power. | 01-28-2010 |
20100169545 | HOST SYSTEM AND OPERATING METHOD THEREOF - The prevent invention provides a host system and an operating method thereof. The host system comprises: a peripheral device control circuit, for controlling operation of at least a peripheral device, the peripheral device comprising an embedded micro processor; and a host control circuit, coupled to the peripheral device control circuit via a transmission interface, the host control circuit comprising: a storage module, at least storing a firmware of the embedded micro processor; and a control module, coupled to the storage module, for controlling operation of the host control circuit, and the control module transmitting the firmware to the peripheral device control circuit via the transmission interface. The embedded micro processor executes the firmware provided by the host control circuit to control operation of the peripheral device control circuit. | 07-01-2010 |
20110296081 | DATA ACCESSING METHOD AND RELATED CONTROL SYSTEM - A data access method and a related control system are provided according to embodiments of the present invention, which enhances the read/write performance of a data storage unit by performing pre-accessing operations upon the data storage unit. The data access method includes receiving a plurality of access requests and a plurality of corresponding addresses to access a plurality of data corresponding to the plurality of access requests from a storage unit; and performing a pre-accessing operation upon the storage unit according to the uniformity of the plurality of access requests and the continuity between the plurality of addresses. | 12-01-2011 |
Patent application number | Description | Published |
20090316391 | Lighting apparatus - The present invention provides an integrated lighting apparatus including a main frame constructed by at least a first frame wall, a second frame wall adjacent to the first frame wall and a third frame wall adjacent to the second frame wall and opposite to the first frame wall. The first, second and third frame walls define an interior space for receiving a lighting device therein. The main frame is integrated with a heat-dissipating portion extending from a first side of the first frame wall. The interior space is covered with the lampshade. Through the heat-dissipating portion, the lighting apparatus is detachably combined with the refrigerated display cabinet in a simple and convenient manner. | 12-24-2009 |
20100102752 | CONTROL CIRCUIT AND METHOD FOR BACKLIGHT SOURCES, AND IMAGE DISPLAY APPARATUS AND LIGHTING APPARATUS USING THE SAME - In light emitting diode (LED) control, a plurality of duty cycle signals corresponding to a plurality of LEDs are stored in a dual-port memory by memory mapping. By sampling, the stored duty cycle signals are outputted to generate a plurality of parallel single-bit data each having one single bit. After the single-bit data are converted by a data transmission module, each bit of the single-bit data is serially outputted to a drive module to drive the LEDs. Thus, the ON duty cycles of the LEDs are modulated by pulse width modulation (PWM), light emitted from the LEDs are mixed in time-domain, and the brightness of the LEDs can be controlled. | 04-29-2010 |
20100127155 | SOLAR-POWERED WIRELESS COMMUNICATION MODULE WITH DAYLIGHT INTENSITY MEASUREMENT - The present invention relates to a solar-powered wireless communication module with daylight intensity measurement, which comprises: a solar cell module, capable of converting solar energy into electricity; a Microcontroller Unit (MCU), coupled to the solar cell module for detecting and outputting values regarding the voltage and the current of the electricity converted from the solar cell module; and a wireless communication unit, powered by the electricity from the solar cell module and coupled to the MCU for transmitting values outputted from the MCU to a control end. | 05-27-2010 |
20100277139 | CONSTANT POWER CONTROL APPARATUS AND CONTROL METHOD THEREOF - A constant power control apparatus and a controlling method thereof are provided. The constant power control apparatus outputs output power to a load element. The constant power control apparatus includes a compensation and modification device, a constant power control device, and a power generation circuit. The compensation and modification device receives an expected output power voltage and a voltage feedback signal relating to the output power. The compensation and modification device transforms the expected output power voltage into a current reference value, and modifies the current reference value to generate a modified current reference value according to the voltage feedback signal. The constant power control device receives the modified current reference value and a current feedback signal relating to the output power, and generates a control signal for use in power modulation. The power generation circuit receives the control signal and outputs the output power. | 11-04-2010 |
20110057568 | Light Adjustment Circuit For Alternating-Current Light Emitting Diodes (AC-LED's) - A light adjustment circuit for alternating-current light emitting diodes (AC-LED's) connected to an AC power supply and a plurality of AC-LED's comprises: a light adjustment unit, being capable of modulating AC power from the AC power supply while providing the plurality of AC-LED's with the modulated AC power; and a pulse width modulation (PWM) control circuit, being capable of modulating an external voltage signal in correspondence to variation in input AC power to enable each of the AC-LED's to achieve a predetermined brightness; wherein the AC-LED's are turned off by modulating the external voltage signal to prevent the AC-LED's from being burnt out when the input AC power is too high. | 03-10-2011 |
Patent application number | Description | Published |
20100231047 | POWER SAFETY SYSTEM - A power safety system includes a first MOS, a second MOS, a switch and a body controller. The first MOS is connected between a power input and a power output. The second MOSFET is connected between the power output and a charging output. The switch has an end connected to the body of the first MOS, and the opposite end switched between the source and the drain of the first MOS. A body controller controls the switch according to the voltage at the power input and the voltage at the power output, to connect the body of the first MOS to the source or the drain of the first MOS. By switching the switch, the first MOS will have a parasitic diode effective to prevent a reverse current from the power output to the power input. | 09-16-2010 |
20110043162 | CHARGER AND PORTABLE DEVICE HAVING THE SAME - A charger for a portable device includes a USB detector connected to a data pin to detect the effective resistance on the data pin before a USB transceiver is enabled, to identify USB or adapter plug in and control a charging current for a battery accordingly. | 02-24-2011 |
20130002195 | CHARGER AND PORTABLE DEVICE HAVING THE SAME - A charger for a portable device includes a USB detector connected to a data pin to detect the effective resistance on the data pin before a USB transceiver is enabled, to identify USB or adapter plug in and control a charging current for a battery accordingly. | 01-03-2013 |
20130002196 | CHARGER AND PORTABLE DEVICE HAVING THE SAME - A charger for a portable device includes a USB detector connected to a data pin to detect the effective resistance on the data pin before a USB transceiver is enabled, to identify USB or adapter plug in and control a charging current for a battery accordingly. | 01-03-2013 |
Patent application number | Description | Published |
20080268593 | METHODS FOR FABRICATING A CAPACITOR - A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor. | 10-30-2008 |
20090026518 | DRAM CYLINDRICAL CAPACITOR - A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer. | 01-29-2009 |
20090114975 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device. | 05-07-2009 |
20140145207 | Schottky Barrier Diode and Fabricating Method Thereof - A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches. | 05-29-2014 |
Patent application number | Description | Published |
20100164018 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 07-01-2010 |
20100237439 | HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME - A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region. | 09-23-2010 |
20120032254 | ESD PROTECTION DEVICE AND METHOD FOR FABRICATING THE SAME - An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region. | 02-09-2012 |
20120168862 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 07-05-2012 |
20140103433 | HIGH-VOLTAGE METAL-DIELECTRIC-SEMICONDUCTOR DEVICE AND METHOD OF THE SAME - A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region. | 04-17-2014 |
20140199818 | METHOD FOR FABRICATING AN ESD PROTECTION DEVICE - A method for fabricating an ESD protection device . Agate electrode of a core device is formed in a non I/O region and a gate electrode of an ESD protection device is formed in a I/O region. A first photoresist film masks the I/O region and reveals the non I/O region. The first photoresist film includes at least an opening adjacent to the gate electrode of the ESD protection device in the I/O region. A core pocket implantation process using the first photoresist film as an implant mask is performed to implant dopants of a second conductivity type into the I/O region through the opening and into the non I/O region, thereby forming a core pocket doping region in the I/O region and core pocket doping regions in the non I/O region. | 07-17-2014 |
Patent application number | Description | Published |
20100020502 | Wafer-To-Wafer Stacking - a wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate. | 01-28-2010 |
20100034402 | ELECTRODE CONNECTION STRUCTURE OF SPEAKER UNIT - An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area. | 02-11-2010 |
20100158284 | ASSEMBLY STRUCTURE OF A FLAT SPEAKER - An assembly structure of flat speaker including at least two speaker units and one connecting structure is provided. Each speaker unit includes a first electrode, a vibrating film, and a second electrode. The connecting structure includes two conductive layers, and a first insulating layer. A first conductive layer is connected the first electrode through a contact area, and each has a first length and a third length parallel to the contact area. A second conductive layer is connected the second electrode through a contact area, and each has a second length and a fourth, a fifth length parallel to the contact area. The third length is less than or equal to a sum of the first lengths of the speaker units. A sum of the third, the fourth, and the fifth length is less than or equal to a sum of the first and second lengths. | 06-24-2010 |
20120321108 | ELECTRODE CONNECTION STRUCTURE OF SPEAKER UNIT - An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area. | 12-20-2012 |
Patent application number | Description | Published |
20090090616 | SYSTEM AND METHOD FOR PLASMA ENHANCED THIN FILM DEPOSITION - A system and a method for plasma enhanced thin film deposition are disclosed, in which the system comprises a plasma enhanced thin film deposition apparatus and a plasma process monitoring device. The plasma enhanced thin film deposition apparatus receives pulsed power and a reactive gas, whereby plasma discharging occurs to ionize the reactive gas into a plurality of radicals for thin film deposition. The plasma process monitoring device comprises an optical emission spectroscopy (OES) and a pulsed plasma modulation device, in which the OES detects spectrum intensities of the radicals and the pulsed plasma modulation device calculates a spectrum intensity ratio of the radicals so as to modulate the plasma duty time of pulsed power, thereby high deposition rate as well as real-time monitoring on thin film deposition quality can be achieved. | 04-09-2009 |
20110136269 | METHOD FOR DEPOSITING MICROCRYSTALLINE SILICON AND MONITOR DEVICE OF PLASMA ENHANCED DEPOSITION - A method for depositing a microcrystalline silicon film is disclosed, including performing an open loop and close loop plasma enhanced deposition process without and with modulating process parameters, respectively. A film is deposited by the open loop plasma enhanced deposition process till a required film crystallinity and then performing a closed loop plasma enhanced deposition process which monitors species plasma spectrum intensities SiH* and Hα and modulates process parameters of the plasma enhanced deposition process resulting in the species concentration stabilization which controls the intensities variation of SiH* and Hα within an allowed range of a target value for improving film depositing rate. | 06-09-2011 |
20120070590 | PLASMA ENHANCED ATOMIC LAYER DEPOSITION APPARATUS AND THE CONTROLLING METHOD THEREOF - This prevent disclosure provides a plasma enhanced atomic layer deposition apparatus and the controlling method thereof. The plasma enhanced atomic layer deposition apparatus includes: a plurality of reaction chambers, each of the reaction chambers having a first reaction space and a second reaction space; an adjustable partition unit controlled to separate or communicate the first and the second reaction spaces; and a plurality of heating carriers respectively disposed in the plurality of reaction chambers. The method manipulates the movement of the partition plate, leading to separation or communication between the first and second reaction spaces, so as to avoid the interference or inter-reaction between process gases and the resultant particles contaminating the substrates. | 03-22-2012 |
20140059836 | ROTATABLE LOCATING APPARATUS WITH DOME CARRIER AND OPERATING METHOD THEREOF - A rotatable locating apparatus including a fixing base, a rotatable rack, a first driving module, a carrier, and a second driving module is provided. The rotatable rack is pivoted on the fixing base through a first rotation axis. The first driving module is coupled to the rotatable rack to drive the rotatable rack rotating with respect to the fixing base along the first rotation axis. The carrier is provided with accommodating slots on an arc surface of the carrier, and the carrier is pivoted on the rotatable rack through a second rotation axis. The second rotation axis passes through a curvature center of the arc surface and is perpendicular to the first rotation axis. The curvature center is located on the first rotation axis. The second driving module is coupled to the carrier to drive the carrier rotating with respect to the rotatable rack along the second rotation axis. | 03-06-2014 |
20140068923 | ROTARY POSITIONING APPARATUS WITH DOME CARRIER, AUTOMATIC PICK-AND-PLACE SYSTEM, AND OPERATING METHOD THEREOF - A rotary positioning apparatus includes a fixing base, a rotation mechanism, two driving modules and a carrier. The rotation mechanism is disposed on the fixing base, the first driving module is disposed on the fixing base and coupled to the rotation mechanism to drive the rotation mechanism rotating around a first rotation axis relatively to the fixing base. The carrier has plural accommodating slots on a circular-arc surface thereof and is pivoted to the rotation mechanism through a second rotation axis passing through the curvature center of the circular-arc surface and perpendicular to the first rotation axis, on which the curvature center is located. The second driving module is disposed on the rotation mechanism and coupled to the carrier to drive the carrier rotating around the second rotation axis relatively to the rotation mechanism. An automatic pick-and-place system and an operation method using the rotary positioning apparatus are also provided. | 03-13-2014 |
Patent application number | Description | Published |
20110235454 | High-voltage selecting circuit which can generate an output voltage without a voltage drop - A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time. | 09-29-2011 |
20130248972 | ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure. | 09-26-2013 |
20130248973 | ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer. | 09-26-2013 |
Patent application number | Description | Published |
20100055873 | LED-LASER LIFT-OFF METHOD - The present invention discloses an LED-laser lift-off method, which applies to lift off a transient substrate from an epitaxial layer grown on the transient substrate after a support substrate having an adhesion metal layer is bonded to the epitaxial layer. Firstly, the epitaxial layer is etched to define separation channels around each chip section, and the epitaxial layer between two separation channels is not etched but preserved to form a separation zone. Each laser illumination area only covers one illuminated chip section, the separation channels surrounding the illuminated chip section, and the separation zones surrounding the illuminated chip section. Thus, the adhesion metal layer on the separation channels is only heated once. Further, the outward stress generated by the illuminated chip section is counterbalanced by the outward stress generated by the illuminated separation zones, and the stress-induced structural damage on the chip section is reduced. | 03-04-2010 |
20100243985 | HIGH LIGHT-EXTRACTION EFFICIENCY LIGHT-EMITTING DIODE STRUCTURE - The present invention discloses a high light-extraction efficiency LED structure, wherein metallic pads and metallic mesh wires made of an aluminum-silver alloy are formed on an LED, whereby the high-reflectivity aluminum-silver alloy makes the light incident on the metallic pads and metallic mesh wires reflected once more or repeatedly and then emitted from the surface or lateral side of the LED, wherefore the present invention can decrease the light loss and increase the light-extraction efficiency. | 09-30-2010 |
20120043522 | High-reflectivity and low-defect density LED structure - The present invention discloses a high-reflectivity and low-defect density LED structure. A patterned dielectric layer is embedded in a sapphire substrate via semiconductor processes, such as etching and deposition. The dielectric layer is formed of two materials which are alternately stacked and have different refractive indexes. An N-type semiconductor layer, an activation layer and a light emitting layer which is a P-type semiconductor layer are sequentially formed on the sapphire substrate. An N-type electrode and a P-type electrode are respectively coated on the N-type semiconductor layer and the P-type semiconductor layer. The dielectric layer can lower the defect density of the light emitting layer during the epitaxial growth process. Further, the dielectric layer can function as a high-reflectivity area to reflect light generated by the light emitting layer and the light is projected downward to be emitted from the top or the lateral. Thereby is greatly increased the light-extraction efficiency. | 02-23-2012 |
20120043567 | LED STRUCTURE WITH BRAGG FILM AND METAL LAYER - The present invention discloses an LED structure with a Bragg film and a metal layer, wherein a Bragg film and a metal layer are coated on a bottom of a sapphire substrate. The Bragg film includes two optical layers having different refractive indexes and alternately stacked. The materials and thickness of the optical layers of the Bragg film are optimized to form a high-reflectivity area via optical operation, which can effectively reflect the incident light generated by the light emitting layer from different incident angles. The Bragg film together with the metal layer can reflect the light, which is projected downward, to be emitted from the top or lateral of an LED structure. Therefore, the present invention can greatly increase the light-extraction efficiency of the LED structure. | 02-23-2012 |