Patent application number | Description | Published |
20080240266 | Arrangements for monitoring and controlling a transmission path - In one embodiment of the present disclosure, a method for improving communication between a transmitter and a receiver is disclosed. The method can include receiving a first signal having a first power level over a first path, receiving a second signal having a second power level over a second path wherein the first path is different than the second path. The method can compare the first power level with the second power and determine a difference between the first power level and the second power level. The method can also adjusting a parameter in the system to reduce the difference in power levels between the first and second signals compensating for interference cause by many sources. | 10-02-2008 |
20080240313 | Closed Loop Adaptive Clock RFI Mitigation - A method according to one embodiment for mitigating radio frequency interference by identifying system clocks, identifying active radio channels, measuring clock harmonics in or near the active radio channels, determining potential interference occurring if the clocks were moved to new fundamental frequencies, and shifting clock fundamental frequencies to reduce interference to the active radio channels based on existing interference and the potential interference of a plurality of new fundamental frequencies. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment. | 10-02-2008 |
20090002952 | Interference mitigation - In some embodiments, an electronic apparatus comprises a display assembly, a printed circuit board comprising a display driver integrated circuit, and at least one structure to alter a resonance frequency characteristic of at least one of the display assembly or the printed circuit board. Other embodiments may be disclosed. | 01-01-2009 |
20090080583 | ADAPTIVE CONTROL OF CLOCK SPREAD TO MITIGATE RADIO FREQUENCY INTERFERENCE - In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed. | 03-26-2009 |
20090325530 | Dynamic RFI detection - Provided herein are different embodiments for performing radio frequency interference (RFI) detection in electronic devices such as mobile computing systems. | 12-31-2009 |
20100003924 | RADIO FREQUENCY INTERFERENCE SENSING SYSTEM AND METHOD - A method of sensing radio frequency interference (RFI) in a wireless system is provided. The method includes receiving wireless data through a wireless receiver and evaluating received wireless data through a receiver baseband module to identify an occurrence of a signal detection failure by a physical (PHY) layer or a media access control (MAC) layer of the wireless system. The method also includes triggering a radio frequency interference sensing state in response to the occurrence of signal detection failure by the physical layer or the media access control layer of the wireless system. | 01-07-2010 |
20100158169 | Dynamic RFI mitigation - Provided herein are different embodiments for performing radio frequency interference (RFI) mitigation in electronic devices such as mobile computing systems. In some embodiments, a dynamic RFI mitigation scheme allows for monitoring of wireless channels for RFI and to adaptively shift an identified RFI source (e.g., system clock) harmonics, e.g., either out of the on-channels or to a neutral position within the on-channels such as by using cost-function analysis. | 06-24-2010 |
20100311374 | DYNAMIC RFI DETECTION USING SIGNAL STRENGTH VALUES - An apparatus may include a radio interface to receive a plurality of signal strength values of a radio. An interference module can identify a radio frequency interference impact on the radio based on the plurality of signal strength values. In one embodiment, the radio interface issues a plurality of interference calls to the radio, where each of the plurality of signal strength values corresponds to an interference call. | 12-09-2010 |
20110293054 | ADAPTIVE CONTROL OF CLOCK SPREAD TO MITIGATE RADIO FREQUENCY INTERFERENCE - In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed. | 12-01-2011 |
20130059557 | DYNAMIC RFI DETECTION - Provided herein are different embodiments for performing radio frequency interference (RFI) detection in electronic devices such as mobile computing systems. | 03-07-2013 |
20140181348 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream. | 06-26-2014 |
20140181357 | CROSSTALK AWARE ENCODING FOR A DATA BUS - Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs. | 06-26-2014 |
20140181358 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels. | 06-26-2014 |