Patent application number | Description | Published |
20100329002 | FORECASTING PROGRAM DISTURB IN MEMORY BY DETECTING NATURAL THRESHOLD VOLTAGE DISTRIBUTION - Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N | 12-30-2010 |
20110273935 | MITIGATING CHANNEL COUPLING EFFECTS DURING SENSING OF NON-VOLATILE STORAGE ELEMENTS - Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state. | 11-10-2011 |
20120167100 | MANUAL SUSPEND AND RESUME FOR NON-VOLATILE MEMORY - An external controller has greater control over control circuitry on a memory die in a non-volatile storage system. The external controller can issue a manual suspend command on a communication path which is constantly monitored by the control circuitry. In response, the control circuitry suspends a task immediately, with essentially no delay, or at a next acceptable point in the task. The external controller similarly has the ability to issue a manual resume command, which can be provided on the communication path when that path has a ready status. The control circuitry can also automatically suspend and resume a task. The external controller can cause a task to be suspended by issuing an illegal read command. The external controller can cause a suspended program task to be aborted by issuing a new program command. | 06-28-2012 |
20140219027 | Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration. | 08-07-2014 |
20140254283 | Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration. | 09-11-2014 |
Patent application number | Description | Published |
20100162036 | Self-Monitoring Cluster of Network Security Devices - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 06-24-2010 |
20100162383 | Cluster Architecture for Network Security Processing - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 06-24-2010 |
20100169446 | Cluster Architecture and Configuration for Network Security Devices - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 07-01-2010 |
20130173766 | CLUSTER ARCHITECTURE AND CONFIGURATION FOR NETWORK SECURITY DEVICES - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 07-04-2013 |
20130191881 | CLUSTER ARCHITECTURE FOR NETWORK SECURITY PROCESSING - A computing device may be joined to a cluster by discovering the device, determining whether the device is eligible to join the cluster, configuring the device, and assigning the device a cluster role. A device may be assigned to act as a cluster master, backup master, active device, standby device, or another role. The cluster master may be configured to assign tasks, such as network flow processing to the cluster devices. The cluster master and backup master may maintain global, run-time synchronization data pertaining to each of the network flows, shared resources, cluster configuration, and the like. The devices within the cluster may monitor one another. Monitoring may include transmitting status messages comprising indicators of device health to the other devices in the cluster. In the event a device satisfies failover conditions, a failover operation to replace the device with another standby device, may be performed. | 07-25-2013 |
Patent application number | Description | Published |
20080252352 | System and Method for Using a DLL for Signal Timing Control in an eDRAM - The present invention discloses an embedded dynamic random access memory (eDRAM) comprising a clock signal, at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control signals each having a predetermined delay from the clock signal, and at least one DRAM array coupled to the plurality of control signals, wherein the DRAM array operates in a plurality of steps controlled by the plurality of control signals. | 10-16-2008 |
20100214857 | MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF - An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell. | 08-26-2010 |
20100253303 | VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO - A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed. | 10-07-2010 |
20100328982 | CONTENT ADDRESSABLE MEMORY DESIGN - A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries. | 12-30-2010 |
20100329055 | MEASURING ELECTRICAL RESISTANCE - A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device. | 12-30-2010 |
20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 11-10-2011 |
20120026805 | SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION - An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level. | 02-02-2012 |
20120038410 | CIRCUIT AND METHOD FOR CHARACTERIZING THE PERFORMANCE OF A SENSE AMPLIFIER - An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current. | 02-16-2012 |
20120081165 | HIGH VOLTAGE TOLERATIVE DRIVER - A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS. | 04-05-2012 |
20120176856 | MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVNG ACCESSES THEREOF - An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell. | 07-12-2012 |
20130127433 | METHOD OF OPERATING VOLTAGE REGULATOR - A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating. | 05-23-2013 |
20130155749 | CONTENT ADDRESSABLE MEMORY - A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. | 06-20-2013 |
20130155751 | MEMORY DEVICES HAVING BREAK CELLS - A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. | 06-20-2013 |
20130223129 | MEASURING ELECTRICAL RESISTANCE - In at least one embodiment, a method includes applying an input voltage external to a semiconductor chip to a first circuit of the semiconductor chip to generate an output voltage external to the semiconductor chip. The first circuit is electrically coupled to a resistive device. A logic state of the resistive device is determined based on a logic state of the external output voltage | 08-29-2013 |
20130272080 | METHOD AND APPARATUS FOR BIT CELL REPAIR - A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell. | 10-17-2013 |
20140250416 | CONTENT ADDRESSABLE MEMORY - A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot. | 09-04-2014 |
20140266114 | METHOD OF OPERATING VOLTAGE REGULATOR - A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit. | 09-18-2014 |
20150029797 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line. | 01-29-2015 |
20150162060 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line. | 06-11-2015 |
Patent application number | Description | Published |
20090077133 | SYSTEM AND METHOD FOR EFFICIENT RULE UPDATES IN POLICY BASED DATA MANAGEMENT - A method, system, and computer program product is provided for efficient policy rule update in a data management system. A policy rule is stored along with the attributes of a data object when the application of the policy rule results in action taken on the data object. A stored policy rule, called an effective policy rule, is subsequently used to restrict the number of data objects examined when a policy rule is added, deleted, modified, or otherwise updated. | 03-19-2009 |
20090112843 | SYSTEM AND METHOD FOR PROVIDING DIFFERENTIATED SERVICE LEVELS FOR SEARCH INDEX - Programs, systems and methods for providing differentiated service levels for a search index are disclosed. Data object documents are processed by extracting terms and scoring each of the terms associated with each document according to criteria to indicate relative importance of the associated document. A plurality of posting lists are generated for each term each comprising entries identifying documents that include the term. The entries are allocated to the different posting lists for the given term depending upon the score for the term associated with particular document. The different posting lists, e.g. a high score and low score posting list, may then be stored as data objects managed according to their indicated importance. For example, the high score posting list data object may be stored in higher performance storage than the low score posting list data object. Scores may be regularly updated. | 04-30-2009 |
20090125884 | SYSTEM AND METHOD FOR WORKFLOW-DRIVEN DATA STORAGE - Programs, systems and methods are described for efficiently storing data as used under a workflow-driven model. A workflow process is defined to control the processing of data objects through different states, e.g., such as an insurance claim document passing through different stages of processing. The workflow process is modeled and employed to manage the storage system based upon predicted state changes derived from state statistics that can be applied to enhance efficiency. For example, copies of the data object may be automatically made when the data object is expected to change state. Some anticipated states implicating high access may direct a storage location with low access time. Hints or requirements for the data object may be applied upon occurrence of an expected state change. Storage management of expected state changes may be further enhanced through dynamic adjustment of the state statistics using collected historical state information to further enhance efficiency. | 05-14-2009 |
Patent application number | Description | Published |
20090049003 | SYSTEM AND METHOD FOR PROVIDING WRITE-ONCE-READ-MANY (WORM) STORAGE - Techniques for providing write-once-read-many (WORM) storage are described herein. According to one embodiment, a range of values is received to set an attribute of a file, where the received range of values is outside of an ordinary range of the attribute in accordance with a file system associated with the file. In addition, a management action is received to be associated with the received range of values of the attribute, where the management action is unrelated to an ordinary action associated with the attribute of the file in accordance with the file system. In response, the received management action is associated with the received range of values of the attribute. Other methods and apparatuses are also described. | 02-19-2009 |
20100049735 | METHOD AND APPARATUS FOR MANAGING DATA OBJECTS OF A DATA STORAGE SYSTEM - Techniques for managing data objects of a data storage system are described herein. According to one embodiment, a perfect hash function is generated for data objects stored in a data storage system. For each of the data objects, a hash operation is performed using the perfect hash function to indicate whether the respective data object is alive. Resources associated with the respective data object is reclaimed if it is determined that the respective data object is not alive based on a result of the hash operation using the perfect hash function, where the reclaimed resources are released back to the data storage system as free resources. Other methods and apparatuses are also described. | 02-25-2010 |
20100332452 | System and method for providing long-term storage for data - A system for storing files comprises a processor and a memory. The processor is configured to break a file into one or more segments; store the one or more segments in a first storage unit; and add metadata to the first storage unit so that the file can be accessed independent of a second storage unit, wherein a single namespace enables access for files stored in the first storage unit and the second storage unit. The memory is coupled to the processor and configured to provide the processor with instructions | 12-30-2010 |
20110238714 | System and Method for Providing Write-Once-Read-Many (WORM) Storage - Techniques for providing write-once-read-many (WORM) storage are described herein. According to one embodiment, in response to a command to set a time attribute of a file to a first predetermined value, it is determined whether the first predetermined value is outside of an ordinary range of values associated with the time attribute in accordance with a file system associated with the file. The file is designated as a WORM file and a WORM retention period is set for the file based on the first predetermined value, if the first predetermined value is outside of an ordinary range of values associated with the time attribute. The designation of the file as a WORM file and setting the WORM retention period are performed in response to the command. | 09-29-2011 |
20120041957 | EFFICIENTLY INDEXING AND SEARCHING SIMILAR DATA - Techniques for efficiently indexing and searching similar data are described herein. According to one embodiment, in response to a query for one or more terms received from a client, a query index is accessed to retrieve a list of one or more super files. Each super file is associated with a group of similar files. Each super file includes terms and/or sequences of terms obtained from the associated group of similar files. Thereafter, the super files representing groups of similar files are presented to the client, where each of the super files includes at least one of the queried terms. Other methods and apparatuses are also described. | 02-16-2012 |
20120254126 | SYSTEM AND METHOD FOR VERIFYING CONSISTENT POINTS IN FILE SYSTEMS - According to one embodiment, in response to a request for verifying a first prime representing a consistent point of a file system of a storage system having a plurality of storage units, each of a plurality of prime segments collectively representing the first prime is examined to determine whether the corresponding prime segment has been previously verified. Each of the prime segments is stored in one of the storage units, respectively. At least a first of the prime segments that has not been previously verified is verified, without verifying a second of the prime segments that has been previously verified. The first prime, when at least the first prime segment has been successfully verified, can be used to construct the consistent point of the file system. | 10-04-2012 |
20120254130 | SYSTEM AND METHOD FOR MAINTAINING CONSISTENT POINTS IN FILE SYSTEMS USING A PRIME DEPENDENCY LIST - According to one embodiment, a request is received for obtaining a consistent point of data stored in a file system of a storage system having a plurality of storage units. In response to the request, retrieving a prime dependency list from a first prime segment stored in a first of the storage units, where the prime dependency list includes information identifying at least a second prime segment stored in a second of the storage units. The first and second prime segments collectively form a prime segment representing a consistent view of the file system. Each of the prime segments listed in the prime dependency list is ascertained in an attempt to generate the consistent point of data. | 10-04-2012 |
20120254174 | TIME-BASED DATA PARTITIONING - According to one embodiment, a file system (FS) of a storage system is partitioned into a plurality of FS partitions, where each FS partition stores segments of data files. In response to a request for writing a file to the storage system, the file is stored in a first of the FS partitions that is selected based on a time attribute of the file, such that files having similar time attributes are stored in an identical FS partition. | 10-04-2012 |
20120254257 | RESOURCE EFFICIENT SCALE-OUT FILE SYSTEMS - According to one embodiment, a file system (FS) of a storage system is partitioned into a plurality of FS partitions, where each FS partition stores segments of data files. In response to an input and output (IO) request for accessing a first of the FS partitions, a second of the FS partitions is selected that is currently in a ready state for access. The second FS partition is then removed from the ready state for access. The first FS partition is brought into a ready state for access. | 10-04-2012 |
20120254565 | SYSTEM AND METHOD FOR MAINTAINING CONSISTENT POINTS IN FILE SYSTEMS - According to one embodiment, in response to a request to write a prime segment of a file system of a storage system having a plurality of storage units, one or more of the storage units are identified based on a prime segment write-map (PSWM). The PSWM includes information indicating which of the storage units to which a next prime should be written. The prime segment is then written in the one or more storage units identified from the PSWM, without writing the prime segment to a remainder of the storage units. The prime segment represents at least a portion of a prime that contains metadata representing a consistent point of data stored in the file system. | 10-04-2012 |
20120296922 | SYSTEM AND METHOD FOR COMMITTING DATA OBJECTS TO BE IMMUTABLE - Techniques for committing data objects to be immutable are described herein. According to one embodiment, in response to a request received through an interface of a storage system, the request being associated with a data object stored in the storage system, it is determined whether the data object should be committed to be immutable. The data object is committed to be immutable if it is determined that the data object should be committed to be immutable. Thereafter, an action associated with the request is performed, where the action is performed dependent upon whether the data object is immutable. Other methods and apparatuses are also described. | 11-22-2012 |
20130036104 | METHOD AND APPARATUS FOR MANAGING DATA OBJECTS OF A DATA STORAGE SYSTEM - Techniques for managing data objects of a data storage system are described herein. According to one embodiment, a hash function is generated for a plurality of data objects by analyzing each of the data objects stored in the data storage system. For each of the data objects, a hash operation is performed on the data object using the hash function, generating a hash value. The hash value is associated with a predetermined attribute of the data object, such that the predetermined attribute of the data object is uniquely identified using the hash function subsequently in response to a request for accessing the predetermined attribute of the data object. The data object is then stored at a persistent storage location of the data storage system, wherein the persistent storage location is identifiable based on a hash value obtained from the hash function. | 02-07-2013 |
20140095816 | SYSTEM AND METHOD FOR FULL VIRTUAL MACHINE BACKUP USING STORAGE SYSTEM FUNCTIONALITY - Techniques for virtual machine full backup are described herein. According to one embodiment, in response to a request to back up a virtual machine (VM) of a client, a request of VM backup is sent out. A consistent state of the VM is then identified via a VM application program interface (VM API). Subsequently a request is sent to a storage system associated with the client to ask for VM disk image associated with the consistent state of the VM to a target backup storage system. | 04-03-2014 |
20140095817 | SYSTEM AND METHOD FOR INCREMENTAL VIRTUAL MACHINE BACKUP USING STORAGE SYSTEM FUNCTIONALITY - Techniques for virtual machine incremental backup are described herein. According to one embodiment, a request for an incremental backing up a virtual machine (VM) is received at a storage system, the request identifying a requested VM disk image associated with a consistent state of the VM. The storage system determines a difference between the requested VM disk image and a previous VM disk image representing a previous VM backup. The changes between the requested VM disk image and a previous VM disk image are then transmitted to a target backup storage system. | 04-03-2014 |
20140181399 | SYSTEM AND METHOD FOR PROVIDING LONG-TERM STORAGE FOR DATA - A system for storing files comprises a processor and a memory. The processor is configured to break a file into one or more segments; store the one or more segments in a first storage unit; and add metadata to the first storage unit so that the file can be accessed independent of a second storage unit, wherein a single namespace enables access for files stored in the first storage unit and the second storage unit. The memory is coupled to the processor and configured to provide the processor with instructions | 06-26-2014 |
20150234616 | SYSTEM AND METHOD FOR PROVIDING LONG-TERM STORAGE FOR DATA - A system for storing files comprises a processor and a memory. The processor is configured to break a file into one or more segments; store the one or more segments in a first storage unit; and add metadata to the first storage unit so that the file can be accessed independent of a second storage unit, wherein a single namespace enables access for files stored in the first storage unit and the second storage unit. The memory is coupled to the processor and configured to provide the processor with instructions | 08-20-2015 |
20150317209 | SYSTEM AND METHOD FOR INCREMENTAL VIRTUAL MACHINE BACKUP USING STORAGE SYSTEM FUNCTIONALITY - Techniques for virtual machine incremental backup are described herein. According to one embodiment, a request for an incremental backing up a virtual machine (VM) is received at a storage system, the request identifying a requested VM disk image associated with a consistent state of the VM. The storage system determines a difference between the requested VM disk image and a previous VM disk image representing a previous VM backup. The changes between the requested VM disk image and a previous VM disk image are then transmitted to a target backup storage system. | 11-05-2015 |
20150317216 | SYSTEM AND METHOD FOR FULL VIRTUAL MACHINE BACKUP USING STORAGE SYSTEM FUNCTIONALITY - Techniques for virtual machine full backup are described herein. According to one embodiment, in response to a request to back up a virtual machine (VM) of a client, a request of VM backup is sent out. A consistent state of the VM is then identified via a VM application program interface (VM API). Subsequently a request is sent to a storage system associated with the client to ask for VM disk image associated with the consistent state of the VM to a target backup storage system. | 11-05-2015 |