Patent application number | Description | Published |
20080239849 | Semiconductor memory device with reduced sense amplification time and operation method thereof - A semiconductor memory device is capable of swiftly sensing data loaded on local I/O lines and transferring the sensed data to a global I/O line, thereby reducing an operating time of a sense amplifier by increasing the sensing and amplifying speed. The semiconductor memory device includes a sense amplifying unit, a precharging unit, a charge sharing unit, and a driving unit. The sense amplifying unit amplifies data applied to a first data line in response to an I/O strobe signal. The precharging unit precharges an output unit of the sense amplifying unit in response to a precharge signal. The charge sharing unit performs a charge sharing operation between the first data line and the output unit before a sense amplifying operation of the sense amplifying unit. The driving unit drives a second data line in response to an output signal of the sense amplifying unit. | 10-02-2008 |
20080239855 | Semiconductor memory device performing self refresh operation - The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command and therefore it is possible to implement a simple circuit for the self refresh. A semiconductor memory device includes a self refresh enable signal generator for outputting an activated self refresh enable signal when positive and negative external clock signals are in phase and a de-activated self refresh enable signal when the positive and negative external clock signals are out of phase and a self refresh block for performing a self refresh operation in response to the activated self refresh enable signal. | 10-02-2008 |
20080304344 | Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device - A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal. | 12-11-2008 |
20080304354 | Semiconductor memory device and method for reading/writing data thereof - A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal | 12-11-2008 |
20080310240 | Semiconductor memory device having I/O unit - A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality of global lines, in response to an output control signal activated after a delay time corresponding to an additive latency from entry of a read operation in a test mode. The data output unit aligns data outputted from the output data select unit and outputs the aligned data through data pads. | 12-18-2008 |
20090003089 | Semiconductor memory device having input device - A semiconductor memory device includes a pad for receiving an external signal through a first external pin, a reference voltage pad for receiving an external reference voltage through a second external pin, an internal reference voltage generator configured to generate an internal reference voltage using an external voltage in response to a reference voltage select signal, a reference voltage supply unit for generating the reference voltage select signal in response to a plurality of select signals, and selecting one reference voltage between the external reference voltage and the internal reference voltage to output the selected one as a reference voltage, a buffer for converting an output signal of the pad into an internal voltage level on the basis of the reference voltage, and a signal selector for controlling an internal signal to be inputted/outputted through the reference voltage pad in response to the plurality of select signals. | 01-01-2009 |
20090010078 | Semiconductor memory device - A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged. | 01-08-2009 |
20090059689 | Apparatus and method for transmitting/receiving signals at high speed - A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal. | 03-05-2009 |
20090067261 | Multi-port memory device - A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group. | 03-12-2009 |
20090086558 | Multi-port memory device with serial input/output interface - A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the first ports via a plurality of first data buses; and a second port for performing a parallel I/O data communication with the external devices through the parallel I/O data pads and a serial I/O data communication with the first ports via a plurality of second data buses, during a test mode. | 04-02-2009 |
20090116304 | Wordline driving circuit of semiconductor memory device - Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver. | 05-07-2009 |
20090219768 | SEMICONDUCTOR MEMORY DEVICE HAVING SHARED BIT LINE SENSE AMPLIFIER SCHEME AND DRIVING METHOD THEREOF - A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal. | 09-03-2009 |
20090219775 | Semiconductor memory device - Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level. | 09-03-2009 |
20090231933 | SEMICONDUCTOR MEMORY DEVICE WITH SIGNAL ALIGNING CIRCUIT - A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals. | 09-17-2009 |
20090237152 | INTERNAL VOLTAGE GENERATOR - An internal voltage generator includes a pull-up driver to pull-up drive a supply terminal of an internal voltage, a pull-down driver to pull-down drive the supply terminal of the internal voltage, a pull-up driving control unit to turn on the pull-up driver when a first feedback voltage corresponding to the internal voltage becomes lower than a reference voltage, and a pull-down driving control unit to turn on the pull-down driver when a second feedback voltage becomes higher than the reference voltage, the second feedback voltage having a voltage level corresponding to that of the internal voltage and lower than that of the first feedback voltage. | 09-24-2009 |
20090267684 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE - An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock. | 10-29-2009 |
20090273373 | SEMICONDUCTOR DEVICE HAVING RECEIVING CIRCUIT USING INTERNAL REFERENCE VOLTAGE - A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage. | 11-05-2009 |
20090273992 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a pad configured to receive a data strobe signal, and a path selector configured to output the data strobe signal through a corresponding input path during a normal operation, and to output the data strobe signal through a plurality of input paths in response to a path selection signal during a test operation. | 11-05-2009 |
20090290436 | TEST CIRCUIT FOR MULTI-PORT MEMORY DEVICE - A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus line and the write bus line and controlled by a test mode signal enabled during a test mode. | 11-26-2009 |
20090302913 | CIRCUIT AND METHOD FOR INITIALIZING AN INTERNAL LOGIC UNIT IN A SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal. | 12-10-2009 |
20090313513 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode. | 12-17-2009 |
20100027364 | MULTI-PORT MEMORY DEVICE HAVING SELF-REFRESH MODE - The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal. | 02-04-2010 |
20100067294 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged. | 03-18-2010 |
20100074035 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for inputting and outputting data in response to a first clock signal having a first frequency; and performing a second operation for storing and reading out the data in a core block in response to a second clock signal having a second frequency, wherein the first frequency is different from the second frequency. | 03-25-2010 |
20100103752 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR READING/WRITING DATA THEREOF - A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal | 04-29-2010 |
20100135057 | MULTI-PORT MEMORY DEVICE HAVING SERIAL INPUT/OUTPUT INTERFACE - A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged. | 06-03-2010 |
20100149891 | SEMICONDUCTOR MEMORY DEVICE INCLUDING RESET CONTROL CIRCUIT - A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal. | 06-17-2010 |
20100169583 | MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE - A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks. | 07-01-2010 |
20100171545 | HIGH VOLTAGE GENERATOR AND WORD LINE DRIVING HIGH VOLTAGE GENERATOR OF MEMORY DEVICE - A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals. | 07-08-2010 |
20100207663 | SEMICONDUCTOR DEVICE FOR RECEIVING EXTERNAL SIGNAL HAVING RECEIVING CIRCUIT USING INTERNAL REFERENCE VOLTAGE - A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage. | 08-19-2010 |
20100244923 | SEMICONDUCTOR DEVICE - A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node. | 09-30-2010 |
20100271115 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE - An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock. | 10-28-2010 |
20100320988 | INTERNAL VOLTAGE SUPPLYING DEVICE - An internal voltage supplying device. A reference voltage generator generates a first feedback voltage having a predetermined voltage ratio with respect to a core voltage. An adjusting mechanism adjusts the voltage ratio, and a voltage generator supplies a high voltage having a level higher than a level of the core voltage by the level of a threshold voltage or higher and maintains the level of the high voltage in accordance with the first feedback voltage. | 12-23-2010 |
20100327935 | DELAY CIRCUIT OF SEMICONDUCTOR DEVICE - A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage. | 12-30-2010 |
20110222359 | APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING SIGNALS AT HIGH SPEED - A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal. | 09-15-2011 |
20110231717 | SEMICONDUCTOR MEMORY DEVICE - Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level. | 09-22-2011 |
20110249517 | WORDLINE DRIVING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver. | 10-13-2011 |
20110267126 | DELAY CIRCUIT OF SEMICONDUCTOR DEVICE - A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage. | 11-03-2011 |
20120032734 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE - An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock. | 02-09-2012 |
20120033516 | WORD LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR TESTING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal. | 02-09-2012 |