Patent application number | Description | Published |
20080239833 | Readout of multi-level storage cells - A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state. | 10-02-2008 |
20080246016 | Device With Damaged Breakdown Layer - A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage. | 10-09-2008 |
20080247216 | METHOD AND APPARATUS FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES - A method of implementing a write operation for a programmable resistive random access memory array includes coupling a current source to a bit line associated with a programmable resistive memory element; prior to activating a word line associated with the memory element, precharging the bit line by passing current the bit line and through a dummy path selectively coupled to the bit line; and upon achieving a desired operating point of bit line current and bit line voltage, decoupling the dummy path from the bit line and activating the word line associated with the memory element so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state. | 10-09-2008 |
20080247218 | DESIGN STRUCTURE FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES - A design structure embodied in a machine readable medium used in a design process includes a circuit for implementing a write operation for a programmable resistive random access memory array, the circuit including a current source coupled to a bit line associated with a programmable resistive memory element; a dummy path configured for selective coupling to the bit line prior to activation of a word line associated with the memory element, wherein the passage of current through the bit line and dummy path precharges the bit line; and control circuitry for decoupling the dummy path from the bit line and for activating the word line associated with the memory element upon achieving a desired operating point of bit line current and bit line voltage, so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state. | 10-09-2008 |
20080272354 | PHASE CHANGE DIODE MEMORY - An integrated circuit having a memory includes a semiconductor line and a phase change element contacting the semiconductor line. The phase change element provides a storage location. A diode junction is formed at the interface between the semiconductor line and the phase change element. | 11-06-2008 |
20080273371 | MEMORY INCLUDING WRITE CIRCUIT FOR PROVIDING MULTIPLE RESET PULSES - An integrated circuit includes an array of resistive memory cells having varying critical dimensions and a write circuit. The write circuit is configured to reset a selected memory cell by applying a first pulse having a first amplitude and a second pulse having a second amplitude less than the first amplitude to the selected memory cell. | 11-06-2008 |
20080298121 | METHOD OF OPERATING PHASE-CHANGE MEMORY - A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction. | 12-04-2008 |
20080304311 | INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION - An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N. | 12-11-2008 |
20080315171 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a diode including a first polarity region and a second polarity region. The second polarity region contacts a bottom and sidewalls of the first polarity region. The integrated circuit includes a first electrode coupled to the diode, a second electrode, and resistivity changing material between the first electrode and the second electrode. | 12-25-2008 |
20090002119 | FUSE SENSING SCHEME - A fuse circuit includes a fuse configured for programming a configuration of an integrated circuit device and a resistive element having a known resistance value operably coupled in parallel with the fuse. The fuse and the resistive element form a parallel circuit configured for quickly sensing a state of the fuse in relation to the known value of the resistive element. In one embodiment, the device may further include a sense circuit operably coupled to the parallel circuit combination of the fuse and the resistive element. The sense circuit is configured to sense one of a FUSED state and an UNFUSED state of the fuse, for example, based on a comparison between a reference resistance and a FUSED resistance of the fuse when coupled to the known resistance. The fuse may comprise a programmable fuse, and the resistive element may comprise a MOS transistor. | 01-01-2009 |
20090003033 | QUASI-DIFFERENTIAL READ OPERATION - A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate, and to charge a second line at a second rate, the first and second charge rates based on a state of a memory cell coupled between the respective lines. The read circuit may further include a ground circuit configured to pull the respective lines to a ground potential, and a sense circuit coupled to the line pair configured to sense a differential voltage between the line pair in response to the state of the memory cell. | 01-01-2009 |
20090003035 | CONDITIONING OPERATIONS FOR MEMORY CELLS - One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed. | 01-01-2009 |
20090027943 | RESISTIVE MEMORY INCLUDING BIDIRECTIONAL WRITE OPERATION - A memory includes a first electrode, a second electrode, and a resistive memory element coupled between the first electrode and the second electrode. The memory includes a circuit configured to write a data value to the resistive memory element by sequentially applying a first signal from the first electrode to the second electrode and a second signal from the second electrode to the first electrode. | 01-29-2009 |
20090034343 | DATA RETENTION MONITOR - A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage. | 02-05-2009 |
20090101975 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD | 04-23-2009 |
20110089392 | MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS - A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node. | 04-21-2011 |