Patent application number | Description | Published |
20090212381 | WAFER LEVEL PACKAGES FOR REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS - A solid state image sensor includes a microelectronic element having a front face and a rear face remote from the front face, the rear face having a recess extending towards the front surface. A plurality of light sensing elements may be disposed adjacent to the front face so as to receive light through the part of the rear face within the recess. A solid state image sensor can include a microelectronic element having a front face and a rear face remote from the front face, a plurality of light sensing elements disposed adjacent to the front face, the light sensing elements being arranged to receive light through the rear face. Electrically conductive package contacts may directly overlie the light sensing elements and the front face and be connected to chip contacts at the front face through openings in an insulating packaging layer overlying the front face. | 08-27-2009 |
20100053407 | Wafer level compliant packages for rear-face illuminated solid state image sensors - A solid state image sensor includes a microelectronic element having a front face and a rear face remote from the front face, the rear face having a recess extending towards the front surface. A plurality of light sensing elements may be disposed adjacent to the front face so as to receive light through the part of the rear face within the recess. A solid state image sensor can include a microelectronic element, e.g., a semiconductor chip, having a front face and a rear face remote from the front face, a plurality of light sensing elements disposed adjacent to the front face, the light sensing elements being arranged to receive light through the rear face. A packaging structure, which can include a compliant layer, can be attached to a front surface of the microelectronic element. Electrically conductive package contacts may directly overlie the light sensing elements and the front face and be connected to chip contacts at the front face through openings in an insulating packaging layer overlying the front face. | 03-04-2010 |
20120068338 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 03-22-2012 |
20120068365 | METAL CAN IMPEDANCE CONTROL STRUCTURE - A microelectronic assembly includes an interconnection element, element contacts, first and second metal layers, conductive elements, and first and second microelectronic devices. The first metal layer may extend beyond at least one of the edges of the first microelectronic device. The conductive elements may respectively extend beyond at least one of the edges of the first metal layer. The first metal layer may have a surface disposed at a substantially uniform spacing from at least substantial portions of the conductive elements, such that a desired impedance may be achieved for the conductive elements. The conductive elements may be spaced a smaller distance from the metal layer than the distance of the conductive elements from the front surface of the first microelectronic device. The second metal layer may be connectable to a source of reference potential. | 03-22-2012 |
20120092832 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS - A microelectronic assembly includes a dielectric element having oppositely-facing first and second surfaces and one or more apertures extending between the surfaces, the dielectric element further having conductive elements thereon; a first microelectronic element having a rear surface and a front surface facing the first surface of the dielectric element, the first microelectronic element having a first edge and a plurality of contacts exposed at the front surface thereof; a second microelectronic element including having a rear surface and a front surface facing the rear surface of the first microelectronic element, a projecting portion of the front surface of the second microelectronic element extending beyond the first edge of the first microelectronic element, the projecting portion being spaced from the first surface of the dielectric element, the second microelectronic element having a plurality of contacts exposed at the projecting portion of the front surface; leads extending from contacts of the microelectronic elements through the at least one aperture to at least some of the conductive elements; and a heat spreader thermally coupled to at least one of the first microelectronic element or the second microelectronic element. | 04-19-2012 |
20120153435 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED GROUND OR POWER DISTRIBUTION - A microelectronic assembly includes a dielectric element having at least one aperture and electrically conductive elements thereon including terminals exposed at the second surface of the dielectric element; a first microelectronic element having a rear surface and a front surface facing the dielectric element, the first microelectronic element having a plurality of contacts exposed at the front surface thereof; a second microelectronic element having a rear surface and a front surface facing the rear surface of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at the front surface and projecting beyond an edge of the first microelectronic element; and an electrically conductive plane attached to the dielectric element and at least partially positioned between the first and second apertures, the electrically conductive plane being electrically connected with one or more of the contacts of at least one of the first or second microelectronic elements. | 06-21-2012 |
20120155042 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED GROUND OR POWER DISTRIBUTION - A microelectronic assembly includes a dielectric element, first and second microelectronic elements, signal leads, and one or more jumper leads. The dielectric element has oppositely-facing first and second surfaces and first and second apertures extend between the surfaces. A plurality of electrically conductive elements are positioned thereon. Signal leads are connected to one or more of the microelectronic elements and extend through one or more of the first or second apertures to some of the conductive elements on the dielectric element. One or more jumper leads extend through the first aperture and are connected to a contact of the first microelectronic element. The one or more jumper leads span over the second aperture and are connected to a conductive element on the dielectric element. | 06-21-2012 |
20120155049 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS - A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, first and second microelectronic elements, and leads extending from contacts exposed at respective front surfaces of the first and second microelectronic elements to central terminals exposed at the central region. The front surface of the first microelectronic element can face the second surface of the dielectric element. The front surface of the second microelectronic element can face a rear surface of the first microelectronic element. The contacts of the second microelectronic element can project beyond an edge of the first microelectronic element. At least first and second ones of the leads can electrically interconnect a first central terminal of the central terminals with each of the first and second microelectronic elements. | 06-21-2012 |
20120267796 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES - A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture. | 10-25-2012 |
20120267797 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. | 10-25-2012 |
20120267798 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly is disclosed that comprises a substrate having first and second openings, a first microelectronic element and a second microelectronic element in a face-down position. The first element has an active surface facing the front surface of the substrate and bond pads aligned with the first opening, a rear surface remote therefrom, and an edge extending between the front and rear surfaces. The second microelectronic element has a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, and bond pads at the front surface of the second microelectronic element aligned with the second opening. | 10-25-2012 |
20120313228 | IMPEDENCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces. | 12-13-2012 |
20130015586 | DE-SKEWED MULTI-DIE PACKAGES - A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. | 01-17-2013 |
20130015590 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. | 01-17-2013 |
20130015591 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, first, second, third, and fourth microelectronic elements, and a plurality of terminals exposed at the second surface. Each microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. The front surfaces of the microelectronic elements can be arranged in a single plane parallel to the first surface. Each microelectronic element can have a column of contacts exposed at the front surface and arranged along respective first, second, third, and fourth axes. The first and third axes can be parallel to one another. The second and fourth axes can be transverse to the first and third axes. The microelectronic package can also include electrical connections extending from at least some of the contacts of each microelectronic element to at least some of the terminals. | 01-17-2013 |
20130043582 | MULTIPLE DIE IN A FACE DOWN PACKAGE - A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements. | 02-21-2013 |
20130043935 | POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING - A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element. | 02-21-2013 |
20130056870 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having oppositely-facing first and second surfaces and a first aperture extending between the first and second surfaces, a first microelectronic element having a surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, signal leads connected to contacts of the second microelectronic element and extending through the first aperture to at least some of a plurality of electrically conductive elements on the substrate, and at least one power regulation component having active circuit elements therein disposed between the first surface of the substrate and the front surface of the second microelectronic element. The first microelectronic element can have another surface remote from the surface of the first microelectronic element, and an edge extending between the surfaces thereof. The contacts of the second microelectronic element can project beyond the edge of the first microelectronic element. | 03-07-2013 |
20130082374 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082375 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082380 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082381 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082389 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082390 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082391 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals. | 04-04-2013 |
20130082394 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package. | 04-04-2013 |
20130082395 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082396 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082397 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region. | 04-04-2013 |
20130082398 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130083582 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130083583 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements. | 04-04-2013 |
20130083584 | STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE - A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe. | 04-04-2013 |
20130127062 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 05-23-2013 |
20130286707 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 10-31-2013 |
20130299958 | LEAD STRUCTURES WITH VERTICAL OFFSETS - A microelectronic structure includes a first row of contacts ( | 11-14-2013 |
20130307138 | DESKEWED MULTI-DIE PACKAGES - A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. | 11-21-2013 |
20140035121 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS - A microelectronic assembly includes a dielectric element that has oppositely-facing first and second surfaces and first and second apertures extending between the surfaces. The dielectric element further includes conductive elements. First and second microelectronic elements are stacked one on top of the another. The second microelectronic element has a plurality of contacts at a surface, which is spaced from the first surface of the dielectric element. Leads extend from contacts of the first and second microelectronic elements through respective apertures to at least some of the conductive elements. A heat spreader is thermally coupled to at least one of the first microelectronic element or the second microelectronic element. | 02-06-2014 |
20140042644 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. | 02-13-2014 |
20140055941 | CO-SUPPORT SYSTEM AND MICROELECTRONIC ASSEMBLY - A system may include a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component may include a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate. | 02-27-2014 |
20140055942 | CO-SUPPORT MODULE AND MICROELECTRONIC ASSEMBLY - A module may be configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module may include a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts may include first contacts having address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate. | 02-27-2014 |
20140055970 | CO-SUPPORT COMPONENT AND MICROELECTRONIC ASSEMBLY - A component may be configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component may include a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate. | 02-27-2014 |
20140103535 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-17-2014 |
20140110832 | CO-SUPPORT CIRCUIT PANEL AND MICROELECTRONIC PACKAGES - A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package. | 04-24-2014 |
20140117516 | MULTIPLE DIE IN A FACE DOWN PACKAGE - A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements. | 05-01-2014 |
20140167278 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140167279 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140185354 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 07-03-2014 |
20140239491 | MICROELECTRONIC UNIT AND PACKAGE WITH POSITIONAL REVERSAL - A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate. | 08-28-2014 |
20140239513 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS - A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, first and second microelectronic elements, and leads extending from contacts exposed at respective front surfaces of the first and second microelectronic elements to central terminals exposed at the central region. The front surface of the first microelectronic element can face the second surface of the dielectric element. The front surface of the second microelectronic element can face a rear surface of the first microelectronic element. The contacts of the second microelectronic element can project beyond an edge of the first microelectronic element. At least first and second ones of the leads can electrically interconnect a first central terminal of the central terminals with each of the first and second microelectronic elements. | 08-28-2014 |
20140239514 | MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES - A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate. | 08-28-2014 |
20140268537 | IN-PACKAGE FLY-BY SIGNALING - In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region. | 09-18-2014 |
20140273346 | MANUFACTURE OF FACE-DOWN MICROELECTRONIC PACKAGES - In a high volume method for manufacturing a microelectronic package, a spacer element and a first die, i.e., microelectronic element, can be attached face-down to a surface of a substrate, contacts on the first die facing a first through opening of the substrate. Then, a second die can be attached face-down atop the first die and the spacer element, contacts on the second die disposed beyond an edge of the first die and facing a second through opening in the substrate. Electrical connections can then be formed between each of the first and second dies and the substrate. The first and second dies can be transferred from positions of a single diced wafer which are selected to maximize compound speed bin yield of the microelectronic package. | 09-18-2014 |
20140291871 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 10-02-2014 |
20140328015 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly ( | 11-06-2014 |
20140328016 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic assembly | 11-06-2014 |
20140333371 | POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING - A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element. | 11-13-2014 |
20140362629 | SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT - A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. | 12-11-2014 |
20140367866 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. | 12-18-2014 |
20150043181 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED GROUND OR POWER DISTRIBUTION - The present disclosure is directed to a microelectronic assembly that includes first and second microelectronic elements, signal leads, one or more jumper leads, and a dielectric element that has first and second apertures. The signal leads may be connected to one or more of the microelectronic elements and extend through the one or more of the first or second apertures to conductive elements on the dielectric element. The jumper leads may extend through the first aperture and be connected to a contact of the first microelectronic element. The one or more jumper leads may span over the second aperture and be connected to a conductive element on the dielectric element. | 02-12-2015 |
20150076714 | MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later. | 03-19-2015 |
20150115472 | CO-SUPPORT FOR XFD PACKAGING - A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements. | 04-30-2015 |
20150115477 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES - A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture. | 04-30-2015 |
20150145117 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS - A microelectronic assembly includes a dielectric element having oppositely-facing first and second surfaces and one or more apertures extending between the surfaces, the dielectric element further having conductive elements thereon; a first microelectronic element having a rear surface and a front surface facing the first surface of the dielectric element, the first microelectronic element having a first edge and a plurality of contacts exposed at the front surface thereof; a second microelectronic element including having a rear surface and a front surface facing the rear surface of the first microelectronic element, a projecting portion of the front surface of the second microelectronic element extending beyond the first edge of the first microelectronic element, the projecting portion being spaced from the first surface of the dielectric element, the second microelectronic element having a plurality of contacts exposed at the projecting portion of the front surface; leads extending from contacts of the microelectronic elements through the at least one aperture to at least some of the conductive elements; and a heat spreader thermally coupled to at least one of the first microelectronic element or the second microelectronic element. | 05-28-2015 |
20150179619 | STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE - A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe. | 06-25-2015 |
20150198971 | Stub minimization for multi-die wirebond assemblies with parallel windows - A microelectronic assembly | 07-16-2015 |
20150214178 | MICROELECTRONIC UNIT AND PACKAGE WITH POSITIONAL REVERSAL - A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip package such as a two-chip package having a first chip facing upwardly and a second chip facing downwardly towards a package substrate, disposed below the chips. The reversed connections simplify routing, particularly where corresponding contacts of the two chips are to be connected to common terminals on the package substrate. | 07-30-2015 |
20150221617 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 08-06-2015 |
20150243631 | MULTIPLE DIE IN A FACE DOWN PACKAGE - A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements. | 08-27-2015 |
20150302901 | SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT - A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements. | 10-22-2015 |
20150364450 | CO-SUPPORT FOR XFD PACKAGING - A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements. | 12-17-2015 |
20150371968 | MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES - A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate. | 12-24-2015 |
20160035656 | RECONFIGURABLE PoP - A microelectronic package ( | 02-04-2016 |
20160093339 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 03-31-2016 |