Patent application number | Description | Published |
20160054775 | METHODS AND APPARATUS TO ESTIMATE POWER PERFORMANCE OF A JOB THAT RUNS ON MULTIPLE NODES OF A DISTRIBUTED COMPUTER SYSTEM - A non-transitory computer readable storage medium having stored thereon instructions executable by one or more processors to perform operations including: receiving a plurality of input parameters including (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) a list of frequencies; responsive to receiving the plurality of workload parameters, retrieving calibration data from a calibration database; generating a power estimate based on the plurality of workload parameters and the calibration data; and providing the power estimate to a resource manager is shown. Alternatively, the input parameters may include (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) an amount of available power, wherein the estimator may provide an estimation of the frequency at which the nodes should operate to utilize as much of the available power without exceeding the available power. | 02-25-2016 |
20160054779 | MANAGING POWER PERFORMANCE OF DISTRIBUTED COMPUTING SYSTEMS - A method of managing power and performance of a High-performance computing (HPC) systems, including: determining a power budget for a HPC system, wherein the HPC system includes a plurality of interconnected HPC nodes operable to execute a job, determining a power and cooling capacity of the HPC system, allocating the power budget to the job to maintain a power consumption of the HPC system within the power budget and the power and cooling capacity of the HPC system, and executing the job on selected HPC nodes is shown. | 02-25-2016 |
20160054781 | Methods and Apparatus to Manage Jobs that can and Cannot be Suspended When there is a Change in Power Allocation to a Distributed Computer System - A non-transitory computer readable storage medium storing instructions executable by one or more processors of a distributed computer system to perform operations including determining whether a power consumed by the distributed computer system is greater than a power allocated to the distributed computer system, responsive to determining the power consumed by the distributed computer system is greater than the power allocated to the distributed computer system, determining whether all jobs being processed by the distributed computer system are processing at a lowest power state for each job, wherein a job includes one or more calculations performed by the one or more processors of the distributed computer system and responsive to determining all jobs being processed by the distributed computer system are processing at a lowest power state for each job, suspending a job having a lowest priority among all jobs being processed by the distributed computer system is shown. | 02-25-2016 |
20160054783 | METHOD AND APPARATUS TO GENERATE AND USE POWER, THERMAL AND PERFORMANCE CHARACTERISTICS OF NODES TO IMPROVE ENERGY EFFICIENCY AND REDUCING WAIT TIME FOR JOBS IN THE QUEUE - A non-transitory computer readable storage medium having stored thereon instructions, the instructions being executable by one or more processors to perform operations including: receiving, by a calibration module executed by the one or more processors, a calibration request including (i) a workload type, (ii) a list of compute nodes belonging to a distributed computer system, and (iii) one or more frequencies; responsive to identifying the workload type as a clustered workload type, instructing a plurality of compute nodes on the list of compute nodes to begin processing a workload of the workload type; and responsive to identifying the workload type as a clustered workload type, instructing a compute node on the list of compute nodes to begin processing the workload of the workload type is shown. | 02-25-2016 |
Patent application number | Description | Published |
20090158067 | SAVING POWER IN A COMPUTER SYSTEM - A power management unit (PMU) may promote a processing core from a working state to a first non-working power saving state after receiving a signal from an automatic core C-state promotion (ACCP) unit. An OS component may detect the idling of the processing core and may initiate the ACCP. The ACCP may initiate the PMU to promote the processing core to a first non-working power saving state. The ACCP may track the residency time of the processing core in the first non-working power saving state and may initiate the PMU to promote the processing core to a next non-working power saving state if residency time of the processing core in the first non-working power saving state exceeds a first value. The ACCP may initiate the PMU to demote the processing core back to the working state if a break event occurs during the residency time. | 06-18-2009 |
20090171875 | SYSTEMS, METHODS AND APPARATUSES FOR RANK COORDINATION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed. | 07-02-2009 |
20090172423 | METHOD, SYSTEM, AND APPARATUS FOR REROUTING INTERRUPTS IN A MULTI-CORE PROCESSOR - A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may be rerouted to and processed by the core in the least idle state. Cores in a multi-core system may be rated based on for example, power states or other characteristics, and interrupts may be assigned based on these ratings. Other embodiments are described and claimed. | 07-02-2009 |
20090172442 | SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING - Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described. | 07-02-2009 |
20090172681 | SYSTEMS, METHODS AND APPARATUSES FOR CLOCK ENABLE (CKE) COORDINATION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed. | 07-02-2009 |
20120331310 | Increasing Power Efficiency Of Turbo Mode Operation In A Processor - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 12-27-2012 |
20130007475 | EFFICIENT FREQUENCY BOOST OPERATION - Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value. | 01-03-2013 |
20130179703 | Increasing Power Efficiency Of Turbo Mode Operation In A Processor - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 07-11-2013 |
20130346772 | DYNAMIC LINK WIDTH MODULATION - Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed. | 12-26-2013 |
20140006761 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS | 01-02-2014 |
20140019654 | DYNAMIC LINK WIDTH ADJUSTMENT - Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein. | 01-16-2014 |
20140095801 | SYSTEM AND METHOD FOR RETAINING COHERENT CACHE CONTENTS DURING DEEP POWER-DOWN OPERATIONS - A system, method, and computer program product for retaining coherent cache contents during deep power-down operations, and reducing the low-power state entry and exit overhead to improve processor energy efficiency and performance. The embodiments flush or clean the Modified-state lines from the cache before entering a deep low-power state, and then implement a deferred snoop strategy while in the powered-down state. Upon existing the powered-down state, the embodiments process the deferred snoops. A small additional cache and a snoop filter (or other cache-tracking structure) may be used along with additional logic to retain cache contents coherently through deep power-down operations, which may span multiple low-power states. | 04-03-2014 |
20140101468 | APPARATUS, SYSTEM AND METHOD FOR GATED POWER DELIVERY TO AN I/O INTERFACE - Techniques and mechanisms for managing a delivery of power to a resource of an input/output (I/O) interface. In an embodiment, a first link of a plurality of communication links is monitored. Of the plurality of links, a first set of resources of the I/O interface is to support communication only via the first link. One or more other resources of the I/O interface are for supporting communications of another link of the plurality of links. In another embodiment, a resource of the first set of resources is decoupled from a power supply in response to detecting a total number of active lanes of the first link, decoupling. | 04-10-2014 |
20140149774 | INCREASING POWER EFFICIENCY OF TURBO MODE OPERATION IN A PROCESSOR - In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed. | 05-29-2014 |
20140181555 | MANAGING A POWER STATE OF A PROCESSOR - A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt. | 06-26-2014 |
20140281647 | MANAGING THE OPERATION OF A COMPUTING SYSTEM - A method and system for managing the operation of a computing system are described herein. The method includes determining a number of workloads on the computing system. The method also includes determining a number of performance-power states for each workload and a corresponding performance range and power consumption range for each performance-power state. The method further includes managing performance and power consumption of the computing system based on the performance-power states. | 09-18-2014 |
20150241949 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS - One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor. | 08-27-2015 |
Patent application number | Description | Published |
20140086158 | SCHEDULING ASSIGNMENT AND ACK/NACK REPORTING TO FACILITATE CENTRALIZED D2D SCHEDULING - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus receives a resource assignment from a serving base station for a device-to-device (D2D) link with a transmitter, attempts to receive a data packet from the transmitter based on the resource assignment, sends an acknowledgment (ACK) only to the serving base station when reception of the data packet succeeds, and sends a negative acknowledgment (NACK) only to the transmitter when the reception of the data packet fails. In an aspect, the apparatus receives a resource assignment from a serving base station for a D2D link with a receiver, sends a data packet to the receiver based on the resource assignment, and assumes the data packet is successfully received at the receiver unless a NACK is received from the receiver, wherein the NACK indicates a failed reception of the data packet at the receiver. | 03-27-2014 |
20140112233 | PRIORITY ASSIGNMENT IN FLASHLINQ DISTRIBUTED SCHEDULING ALGORITHM TO FINE-TUNE PERFORMANCE - A method, a computer program product, and an apparatus are provided. The apparatus determines a degree of a link based on interference observed from at least one other link, determines a priority of the link based on the determined degree, and decides whether to yield based on the determined priority. The priority of the link may further be based on a determined data rate of the link. The apparatus may transmit the priority to another device via a request to send (RTS) signal and/or a clear to send (CTS) signal. The apparatus may also determine a priority associated with an active link and decide whether to yield to the active link by comparing the determined priority of the link with the priority of the active link. | 04-24-2014 |
20140160946 | METHODS AND APPARATUS FOR IMPROVING CENTRALIZED D2D SCHEDULING - A method, an apparatus, and a computer program product for wireless communication are provided in connection with minimizing D2D overhead resource usage. In one example, a first UE is equipped to measure a first received power value from a second UE with which the first UE has a D2D link, and a received power value from each UE of one or more other UEs, determine whether the received power value from any of the one or more other UEs is greater than a relevant interferer threshold, and transmit the received power value for any of the one or more other UEs for which the received power value is determined to be greater than the relevant interferer threshold. In an aspect, the relevant interferer threshold may be based on a fractional value of the first received power value. | 06-12-2014 |
Patent application number | Description | Published |
20150085765 | CONTROL SIGNALING FOR ENABLING TWO-HOP ORTHOGONALIZATION FOR DEVICE-TO-DEVICE BROADCASTS - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus receives one or more D2D broadcasts in a set of subchannels of a channel. In addition, the apparatus broadcasts in at least one subchannel of the channel information indicating a subset of the set of subchannels. The one or more D2D broadcasts may include a first set of broadcasts that includes control information and a second set of broadcasts that includes data traffic. The broadcasted information may be control information. The apparatus may determine a signal strength of each of the one or more D2D broadcasts received in the set of subchannels. The broadcasted information may further include the determined signal strength for each subchannel in the subset of the set of subchannels. | 03-26-2015 |
20150085789 | TIME COORDINATION TO IMPROVE THROUGHPUT FOR D2D BROADCAST - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus selects a subchannel for transmitting a signal, determines a priority of the selected subchannel with respect to one or more other subchannels respectively selected by one or more neighboring transmitters, determines whether to transmit the signal on the selected subchannel based on the priority. | 03-26-2015 |
20150087350 | IBE AWARE CHANNEL SELECTION - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus (e.g., first transmitter) determines a transmission power of each of a plurality of neighboring transmitters respectively transmitting on a plurality of subchannels in a bandwidth, detects a pathloss to each of the plurality of neighboring transmitters respectively transmitting on the plurality of subchannels, and selects one of the plurality of subchannels for transmitting a signal based on the determined transmission power on each of the plurality of subchannels and the detected pathloss to each of the plurality of neighboring transmitters respectively transmitting on the plurality of subchannels. | 03-26-2015 |