Patent application number | Description | Published |
20100104249 | PLASTIC GLASS OPTICAL FIBER - A plastic glass optical fiber includes a glass core (diameter a | 04-29-2010 |
20120042696 | MEASURING METHOD OF LONGITUDINAL DISTRIBUTION OF BENDING LOSS OF OPTICAL FIBER, MEASURING METHOD OF LONGITUDINAL DISTRIBUTION OF ACTUAL BENDING LOSS VALUE OF OPTICAL FIBER, TEST METHOD OF OPTICAL LINE, MANUFACTURING METHOD OF OPTICAL FIBER CABLE, MANUFACTURING METHOD OF OPTICAL FIBER CORD, AND MANUFACTURING METHOD OF OPTICAL FIBER - A measuring method of a longitudinal distribution of bending loss of an optical fiber includes calculating an arithmetical mean value I(x) from two backscattering light intensities of two backscattering light at a position x obtained by bidirectional OTDR measurement of the optical fiber; and obtaining a bending loss value at the position x from a mode field diameter 2W(x) and a relative refractive index difference Δ(x) at the position x calculated from the arithmetical mean value. | 02-23-2012 |
20120044482 | MEASURING METHOD OF HOLE DIAMETER, HOLE POSITION, HOLE SURFACE ROUGHNESS, OR BENDING LOSS OF HOLEY OPTICAL FIBER, MANUFACTURING METHOD OF HOLEY OPTICAL FIBER, AND TEST METHOD OF OPTICAL LINE OF HOLEY OPTICAL FIBER - A measuring method of a hole diameter of a holey optical fiber includes calculating an arithmetical mean value I(x) from two backscattering light intensities at a position x of two backscattering light waveforms of the holey optical fiber, in which the two backscattering light waveforms are obtained by OTDR measurement; and obtaining the hole diameter at the position x, based on a correlation between an arithmetical mean value I(x) and an hole diameter of the holey optical fiber that is obtained in advance. | 02-23-2012 |
20120262706 | METHOD OF MEASURING CUT-OFF WAVELENGTH OF OPTICAL FIBER - A cut-off wavelength measuring method according to the present invention includes: preparing a single mode fiber as a reference fiber; preparing a measurement target fiber; adjusting the length of the single mode fiber such that the length of the single mode fiber is longer than the that of the measurement target fiber at the time of measuring power of transmission light and the reference fiber propagates only light of a base mode at a predicted cut-off wavelength of the measurement target fiber; measuring wavelength dependence of power of light transmitted through the reference fiber and wavelength dependence of power of light transmitted through the measurement target fiber; and calculating a cut-off wavelength of the measurement target fiber based on wavelength dependence represented as the ratio of the power of transmission light transmitted through the measurement target fiber to the power of light transmitted through the reference fiber. | 10-18-2012 |
20120288247 | OPTICAL FIBER - Each of a first clad region ( | 11-15-2012 |
20130243380 | OPTICAL FIBER, OPTICAL TRANSMISSION LINE, AND METHOD FOR MANUFACTURING OPTICAL FIBER - An optical fiber ( | 09-19-2013 |
20130243384 | MULTICORE FIBER - A multicore fiber includes a plurality of core elements; and a clad surrounding an outer periphery surface of each of the core elements, and each of the core elements includes a core, a first clad surrounding the outer periphery surface of the core and a second clad surrounding an outer periphery surface of the first clad, and when a refractive index of the core is n | 09-19-2013 |
20130272668 | OPTICAL FIBER - An optical fiber of the invention satisfies Δ | 10-17-2013 |
20130312899 | METHOD OF CONNECTING MULTI-CORE FIBERS - A butting step S | 11-28-2013 |
20140003807 | CROSSTALK MEASURING METHOD AND CROSSTALK MEASURING DEVICE | 01-02-2014 |
20140010507 | MULTICORE FIBER - A multicore fiber includes a cladding and a plurality of core elements which is provided in the cladding and includes a core, an inner cladding layer that surrounds the core, and a low-refractive index layer that surrounds the inner cladding layer and has a lower average refractive index than the cladding and the inner cladding layer. The plurality of core elements is arranged such that a specific core element is surrounded by three or more core elements, and a low-refractive index layer of a partial core element of the plurality of core elements is configured to have larger light confinement loss in the core than low-refractive index layers of the other partial core elements. | 01-09-2014 |
20140010508 | OPTICAL FAN-IN/FAN-OUT DEVICE - A radius of a first core | 01-09-2014 |
20140029901 | OPTICAL FIBER AND OPTICAL TRANSMISSION LINE - An optical fiber, including (i) an inner core having an α-power refractive index profile, (ii) an outer core having a refractive index of n1′, and (iii) a cladding having a refractive index of n2 (n1′01-30-2014 | |
20140178018 | MULTICORE FIBER - A multicore fiber includes a first multicore fiber member and a second multicore fiber member, one end face of the first multicore fiber member being spliced to one end face of the second multicore fiber member, wherein at least two core end faces of multiple cores in the first multicore fiber member are spliced one-to-one to core end faces of multiple cores in the second multicore fiber member, and, among the cores in the first multicore fiber member and the cores in the second multicore fiber member spliced one-to-one at the core end faces, at least one core in the first multicore fiber member and one core in the second multicore fiber member spliced thereto have different effective core areas, and an open end face of the core having the larger effective core area is a face which light enters. | 06-26-2014 |
20140178024 | MULTICORE FIBER FOR COMMUNICATION - A multicore fiber for communication | 06-26-2014 |
20140216109 | METHOD OF MANUFACTURING PREFORM FOR MULTICORE FIBER AND METHOD OF MANUFACTURING MULTICORE FIBER - A plurality of clad rods, and a clad tube, an arrangement process for arranging the plurality of core rods and the plurality of clad rods in a tube of the clad tube, in a state in which distances between center axes of the adjacent core rods become equal to each other and a state in which parts of outer circumferential surfaces in the adjacent rods contact, and an integration process for integrating the clad tube and the plurality of core rods and the plurality of clad rods arranged in the tube, wherein a ratio of a total cross-sectional area of a direction orthogonal to a length direction in the plurality of core rods and the plurality of clad rods with respect to an internal cross-sectional area of the tube of a direction orthogonal to a length direction in the clad tube is 0.84 or more. | 08-07-2014 |
20140334789 | MULTI-CORE FIBER - A multi-core fiber includes an even number of six or more of cores and a clad that surrounds the outer circumferential surfaces of the cores. The cores are formed of two types of cores and in which an effective refractive index difference in a fundamental mode is 0.002 or less in a predetermined range or more that the effective refractive index difference in the fundamental mode is varied according to a core pitch. Two types of the cores are alternately and annularly disposed at regular spacings. A difference in the mode field diameter of light propagating through the cores is 1 μm or less. | 11-13-2014 |
20150139596 | MULTICORE FIBER AND METHOD OF MANUFACTURE OF THE SAME - A multicore fiber includes a plurality of cores and a cladding that encloses the plurality of the cores. The plurality of the cores is arranged and disposed on a linear line passed through the center of the cladding. A difference in the cutoff wavelength between an outer core located at the outermost position and an inner core located next to the outer core is set at a wavelength of 100 nm or less. | 05-21-2015 |
20150139597 | MULTICORE FIBER - A multicore fiber includes a plurality of cores and a cladding surrounding the plurality of cores. The plurality of cores is arranged and disposed on a linear line passed through the center of the cladding. A pair of cores is included. The pair of the cores is located adjacent to each other, and has different core diameters in a first direction in which the plurality of cores is arranged on the linear line. A ratio of a core diameter in the first direction to a core diameter in a second direction orthogonal to the first direction is different between the pair of the cores. | 05-21-2015 |
20150147039 | MULTICORE FIBER - A multicore fiber according to an aspect of the present invention includes a plurality of cores and a cladding surrounding the plurality of the cores. In this multicore fiber, a pair of cores is arranged and disposed on a linear line passed through the center of the cladding, the pair of the cores being adjacent to each other and having refractive indexes varied differently from the cladding to the cores. | 05-28-2015 |
20150147040 | MULTICORE FIBER - A multicore fiber includes a plurality of cores, a cladding that encloses the plurality of the cores, and a marker disposed in the cladding. The plurality of the cores is arranged and disposed on a linear line passed through the center of the cladding. The marker is disposed along the length direction of the cladding on a portion on which the marker does not overlap the cores in a first direction in which the plurality of the cores is arranged on the linear line and does not overlap the core in a second direction orthogonal to the first direction. | 05-28-2015 |
20150212265 | OPTICAL FIBER AND LIGHT TRANSMISSION PATH - Optical fibers Fp, Fn, included in a light transmission path, are two-mode optical fibers for propagating an LP01 mode component and an LP11 mode component contained in signal light, and a gradient dΔτ/dλ of a mode dispersion Δτ with respect to a wavelength λ in a wavelength band of 1530 nm to 1625 nm is |0.5| ps/km/nm or less. Symbols of mode dispersions Δτ of the optical fibers Fp, Fn are opposite to each other. The light transmission path can satisfactorily compensate the mode dispersion in a wide wavelength band. | 07-30-2015 |
20150316715 | MULTI-CORE FIBER - A multicore fiber includes six or more of core elements having a core, a first clad surrounding the outer circumferential surface of the core and a second clad surrounding the outer circumferential surface of the first clad, and includes a clad surrounding the core elements. All of expressions are satisfied: n | 11-05-2015 |
20150318659 | AMPLIFYING OPTICAL FIBER AND OPTICAL AMPLIFIER - A plurality of cores | 11-05-2015 |
Patent application number | Description | Published |
20130121691 | OPTICAL TRANSMISSION SYSTEM, OPTICAL TRANSMISSION APPARATUS, SIGNAL CONDITIONING PROGRAM, AND SIGNAL CONDITIONING METHOD - An optical transmission system includes optical transmission apparatuses configured to transmit wavelength-division multiplexed light signals via lightpaths, each of a pair of optical transmission apparatuses includes a conditioning unit configured to adjust the optical intensities of channels included in the wavelength-division multiplexed light signal, and one or more first processors configured to control, based on a conditioning level notified, the conditioning unit; and a managing apparatus configured to manage the pair of the optical transmission apparatuses, the managing apparatus including one or more second processors configured to compute a conditioning level on a basis of system information for respective the pair of optical transmission apparatuses in the optical transmission system. | 05-16-2013 |
20130121693 | OPTICAL TRANSMISSION SYSTEM, PUMP-LIGHT SUPPLY CONTROL METHOD, AND PUMP LIGHT SUPPLY APPARATUS - An optical transmission system for communicating between transmission devices includes a first pump light source that supplies a first pump light, a second pump light source that supplies a second pump light, an optical transmission line that propagates an optical signal between the transmission devices, and a plurality of couplers that form a plurality of zones in the transmission line, the first pump light source and the second pump light source being optically connected to different couplers of the plurality of couplers, the second pump light Raman-amplifying the first pump light in a zone in which the second pump light is input in the transmission line. | 05-16-2013 |
20130251365 | OPTICAL POWER MONITOR, OPTICAL POWER CONTROL SYSTEM AND OPTICAL POWER MONITOR METHOD - An optical power monitor that detects optical power of respective wavelengths of a signal light in a wavelength multiplexing system, includes: a light emitter configured to superimpose a frequency modulation component on a signal light; a wavelength tunable filter configured to sweep a pass band of the signal light across a wavelength band for a signal light; and a detector configured to detect intensity changes in optical power passing through the wavelength tunable filter with a frequency modulation of the optical power, and to detect an optical power measurement value at a middle point of two points of the intensity changes of the optical power as the optical power of a wavelength to be measured. | 09-26-2013 |
20140105596 | OPTICAL TRANSMISSION SYSTEM, METHOD OF TESTING OPTICAL TRANSMISSION SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - An optical transmission system includes: an optical transmission device that has a plurality of optical transmitters configured to output at least one different wavelength and a multiplexer configured to multiplex wavelength lights output by the plurality of optical transmitters and output a multiplexed wavelength light; and a detection unit configured to detect each wavelength light that is branched before being fed into the multiplexer by sweeping an objective wavelength for detection, wherein, in a single sweeping, the detection unit selects and detects two or more wavelength lights with a wavelength interval that is wider than a wavelength interval of an output light of the multiplexer. | 04-17-2014 |
20140140692 | OPTICAL TRANSMISSION DEVICE, NODE DEVICE, OPTICAL TRANSMISSION METHOD, AND OPTICAL TRANSMISSION SYSTEM - An optical transmission device includes a transmission unit, a filter unit, a detection unit, and a control unit. The transmission unit superimposes identical superimposition signals of a frequency modulation method on a plurality of optical signals that have identical destinations and that have adjacent wavelengths, and transmits resultant signals as one communication signal. The filter unit filters part of two optical signals having adjacent wavelengths from among the plurality of optical signals included in the communication signal. The detection unit generates an electric signal of a detection level representing an optical intensity of the two optical signals that were filtered by the filter unit. The control unit controls timings of superimposing the superimposition signals on the two optical signals respectively by controlling the transmission unit so that variation in the detection level becomes smaller. | 05-22-2014 |
20140205281 | APPARATUS AND METHOD FOR MONITORING WAVELENGTH TUNABLE OPTICAL FILTER - A monitoring apparatus, that monitors a wavelength tunable optical filter for filtering an optical signal to which a frequency modulation component is added, includes: an optical filter configured to filter the optical signal output from the wavelength tunable optical filter; a detector configured to detect amplitude of the frequency modulation component included in the optical signal output from the optical filter; a generator configured to generate an output-side amplitude distribution representing a distribution of the amplitude of the frequency modulation component detected by the detector, by sweeping a transmission wavelength of the optical filter; and a monitoring unit configured to monitor arrangement of a transmission wavelength band of the wavelength tunable optical filter with respect to a spectrum of the optical signal based on the output-side amplitude distribution generated by the generator. | 07-24-2014 |
20140219662 | SIGNAL DETECTION CIRCUIT AND OPTICAL TRANSMISSION EQUIPMENT - A signal detection circuit includes: a first optical filter configured to filter an optical signal carrying a frequency modulated signal with a first transmission band; a second optical filter configured to filter the optical signal with a second transmission band; a first photo detector configured to convert the output light of the first optical filter into a first electrical signal; a second photo detector configured to convert the output light of the second optical filter into a second electrical signal; a difference circuit configured to output a signal representing a difference between the first electrical signal and the second electrical signal; and a detector configured to detect the frequency modulated signal based on the output signal of the difference circuit. | 08-07-2014 |
20140241719 | WAVELENGTH PATH SWITCHING METHOD, OPTICAL COMMUNICATION SYSTEM, OPTICAL COMMUNICATION DEVICE, OPTICAL RELAY DEVICE, AND NETWORK MANAGEMENT DEVICE - At least one of a first device, a second device, and a relay device compensates for wavelength dispersion in a first optical wavelength path. The first or second device changes a wavelength dispersion compensation amount at the first or second device so that wavelength dispersion in a second optical wavelength path is compensated. The relay device changes a wavelength dispersion compensation amount at the relay device so that a total amount of wavelength dispersion of the signal light compensated in the first optical wavelength path does not change substantially with the change in the wavelength dispersion compensation amount at the first or second device. The first optical wavelength path is switched to the second optical wavelength path after the wavelength dispersion compensation amount at the first or second device is changed to a value that can compensate for the wavelength dispersion in the second optical wavelength path. | 08-28-2014 |
20140270756 | MEASUREMENT DEVICE, MEASUREMENT METHOD, TRANSFER DEVICE, AND OPTICAL NETWORK - A measurement device includes a first obtaining unit configured to obtain a first power ratio that indicates a ratio of optical signal power of a first wavelength in a first spectrum at a reception device to optical signal power of a second wavelength different from the first wavelength in the first spectrum; a second obtaining unit configured to obtain a second power ratio that indicates a ratio of optical signal power of the first wavelength in a second spectrum at a transmission device to optical signal power of the second wavelength in the second spectrum; a calculation unit configured to calculate an OSNR of the optical signal at the reception device using the first power ratio obtained by the first obtaining unit and the second power ratio obtained by the second obtaining unit; and an output unit configured to output the OSNR calculated by the calculation unit. | 09-18-2014 |
20140270781 | OPTICAL SIGNAL DEMODULATOR, OPTICAL SIGNAL DEMODULATING METHOD, AND OPTICAL ADD-DROP MULTIPLEXER - An optical signal demodulator includes: an obtaining unit configured to obtain a spectrum of an optical signal generated by a second signal being superimposed on a first signal using frequency modulation; an identifying unit configured to identify a peak wavelength which is a wavelength corresponding to a peak position of the spectrum; and a demodulating unit configured to demodulate the second signal from the optical signal using a wavelength-variable filter to which a transmitted wavelength band has been set based on the peak wavelength. | 09-18-2014 |
20150155935 | APPARATUS AND METHOD FOR CREATING CALIBRATION COEFFICIENT USED TO MONITOR OPTICAL SIGNAL-TO-NOISE RATIO - An apparatus includes: a photodetector configured to create a first electric-signal from an optical signal; a power-measuring unit configured to measure power of the optical signal according to the first electric-signal; a noise calculating unit configured to calculate noise corresponding to a specified target optical signal-to-noise ratio (OSNR) according to the power of the optical signal, the power having been measured by the power-measuring unit, the specified target optical signal-to-noise ratio, and information representing characteristics of the photodetector; a noise generating unit configured to add the noise calculated by the noise calculating unit to the first electric-signal to generate a second electric-signal; an OSNR measuring unit configured to measure an optical signal-to-noise ratio according to the second electric-signal; and a calibration coefficient calculating unit configured to calculate a calibration coefficient used to obtain the target optical signal-to-noise ratio from the optical signal-to-noise ratio measured by the OSNR measuring unit. | 06-04-2015 |
20150280852 | TRANSMISSION DEVICE AND OPTICAL TRANSMISSION SYSTEM - A transmission device that receives an optical signal on which a frequency modulated signal is superimposed includes: an optical filter configured to filter the optical signal; a filter controller configured to control a passband of the optical filter based on a change of power of the optical signal; and a signal detection unit configured to detect the frequency modulated signal based on the change of the power of the optical signal filtered by the optical filter. | 10-01-2015 |
Patent application number | Description | Published |
20120100416 | MOLTEN SALT BATTERY CASE, AND MOLTEN SALT BATTERY - The case for a molten salt battery is used for a molten salt battery containing as an electrolyte a molten salt containing sodium ions. The case is formed of aluminum or an aluminum alloy containing 90% by mass or more of aluminum. | 04-26-2012 |
20120129056 | NEGATIVE ELECTRODE MATERIAL FOR BATTERY, NEGATIVE ELECTRODE PRECURSOR MATERIAL FOR BATTERY, AND BATTERY - In a molten salt battery | 05-24-2012 |
20120171537 | MOLTEN SALT BATTERY - Provided is a molten salt battery which can be stably charged and discharged. A separator | 07-05-2012 |
20120208068 | METHOD FOR PRODUCING SEPARATOR, METHOD FOR PRODUCING MOLTEN SALT BATTERY, SEPARATOR, AND MOLTEN SALT BATTERY - A separator of a molten salt battery made of a porous resin sheet. The separator is improved in wettability to a molten salt by giving hydrophilicity to the resin sheet. In the case of a fluororesin sheet, the sheet is impregnated with water, and irradiated with ultraviolet rays so that C—F bonds in the fluororesin are cleaved and the resultant reacts with water to generate hydrophilic groups, such as OH groups, in each surface layer thereof. The separator gains hydrophilicity through the hydrophilic groups. The separator made of the resin can be made into a bag form. In a molten salt battery having the bag-form separator, the growth of a dendrite is prevented. | 08-16-2012 |
20120237827 | POROUS METAL BODY, METHOD FOR PRODUCING THE SAME, AND MOLTEN-SALT BATTERY - A porous metal body includes a porous skeleton that forms a three-dimensional network structure and includes an aluminum layer having a thickness of 1 to 100 μm, and tin layers disposed on an internal surface and an external surface of the aluminum layer. Such a porous metal body can be produced by an internal-tin-layer formation step of forming a tin layer on a surface of a resin molded body having a three-dimensional network structure; an aluminum-skeleton formation step of forming an aluminum layer serving as an aluminum skeleton on a surface of the internal tin layer; an external-tin-layer formation step of forming a tin layer on a surface of the aluminum skeleton; and a resin removal step of removing the resin molded body, the resin removal step being performed after the aluminum-skeleton formation step or after the external-tin-layer formation step. | 09-20-2012 |
20130130124 | POROUS METAL BODY, METHOD FOR PRODUCING THE SAME, AND BATTERY USING THE SAME - A main object is to produce a porous metal body that can be used as a battery electrode, in particular, that can be used as a negative electrode of a molten-salt battery using sodium. The porous metal body includes a hollow metal skeleton composed of a metal layer containing nickel or copper as a main component, and an aluminum covering layer that covers at least an outer surface of the metal skeleton. The porous metal body further includes a tin covering layer that covers the aluminum covering layer, and is used as a battery electrode. Preferably, the porous metal body has continuous pores due to a three-dimensional network structure thereof, and has a porosity of 90% or more. | 05-23-2013 |
20130171513 | MOLTEN SALT BATTERY - Provided is a molten salt battery whose cycle life is improved by using an electrolyte that is unlikely to cause corrosion of aluminum. In the molten salt battery of the present invention, the total concentration of iron ions and nickel ions contained as impurities in the electrolyte composed of a molten salt is set to be 0.1% by weight or less, preferably 0.01% by weight or less. Because of the low total concentration of iron ions and nickel ions contained in the electrolyte, corrosion of the electrode current collector composed of aluminum is inhibited, and the cycle life of the molten salt battery is improved. | 07-04-2013 |
20130202942 | MOLTEN SALT BATTERY - A molten-salt battery is provided with rectangular plate-like negative electrodes ( | 08-08-2013 |
20130294997 | METHOD FOR PRODUCING FLUORINE COMPOUND | 11-07-2013 |
20130295003 | METHOD FOR PRODUCING SODIUM CHROMITE - According to this production method, the water content of a mixture of a chromium oxide (Cr2O3) powder and a sodium carbonate (Na2CO3) powder is brought to 1000 ppm or less, and the mixture is heated in an inert gas atmosphere at a calcination temperature (850 DEG C.) where the sodium carbonate and the chromium oxide undergo a calcination reaction. Sodium chromite is thereby obtained. | 11-07-2013 |
20130330608 | MOLTEN SALT BATTERY - The molten salt used as an electrolyte of a molten salt battery is a mixed salt between a salt in which the anion is an ion represented by [R1-SO | 12-12-2013 |
20130330618 | BATTERY ELECTRODE AND BATTERY - Provided are a battery electrode with low internal resistance and a battery with high charge and discharge efficiency. The battery electrode includes a current collector formed of a porous metal having a three-dimensional network structure and an active material, and the active material is supported in the network structure of the current collector without using a binder resin. | 12-12-2013 |
20140038011 | MOLTEN-SALT ELECTROLYTE BATTERY DEVICE - Safe molten-salt electrolyte battery device that can quickly decrease the temperature of a molten-salt electrolyte battery when abnormal heat generation occurs in the battery is provided. A molten-salt electrolyte battery device according to the present invention is provided with a molten-salt electrolyte battery which uses a molten-salt electrolyte and includes a temperature detection means which detects the temperature of the molten-salt electrolyte battery, a cooling means which cools the molten-salt electrolyte battery with a cooling medium, and a control means into which a signal from the temperature detection means is inputted and which outputs an operation instruction to the cooling means. When the molten-salt electrolyte battery device is used, in the case where abnormal heat generation occurs in the molten-salt electrolyte battery, the molten-salt electrolyte battery is cooled by the cooling medium, and therefore, the temperature of the battery can be quickly decreased to a safe temperature. | 02-06-2014 |
20140042979 | CHARGE/DISCHARGE CONTROL DEVICE FOR MOLTEN SALT BATTERY AND METHOD OF CHARGING MOLTEN SALT BATTERY - Provided is a charge/discharge control device | 02-13-2014 |
20140093757 | MANUFACTURING METHOD FOR MOLTEN SALT BATTERY AND MOLTEN SALT BATTERY - Provided is a method for manufacturing a molten salt battery. The method includes a housing step (S | 04-03-2014 |
20140106234 | MOLTEN-SALT BATTERY - There is provided with a molten-salt battery which can prevent relative positional displacement between a positive electrode or a negative electrode and a separator. Both faces of the negative electrodes are covered with the separators which are formed to bend along a lower end part of the respective positive electrodes. The separators respectively have a V-shaped or U-shaped cross section, a bent part is formed to have a valley-like (groove-like) shape, and the respective bent parts are disposed along a lower side of the positive electrodes. The positive electrodes having both faces covered with the respective separators as described above and the negative electrodes are laminated alternately. The dimension of the separators after being bent is made larger than that of the positive electrodes and the negative electrodes by 1 to 10%. | 04-17-2014 |
20140170458 | MOLTEN SALT BATTERY - A separator ( | 06-19-2014 |
20140234685 | MOLTEN SALT BATTERY - A separator for use in a molten salt battery has the problem that due to usage specific to the molten salt battery, the separator is placed under mechanical, thermal and chemical stress, so that cracking or rupture easily occurs, leading to a degradation in battery performance such as an internal short-circuit. The molten salt battery of the present invention includes a separator containing a metal oxide, particularly aluminum oxide and/or zirconium oxide in an amount of 75% or more. The separator improves mechanical, thermal and chemical resistance, and thus an internal short-circuit ascribable to the separator is hard to occur, so that the molten salt battery can be stably operated for a long period of time. The separator has high heat stability, so that the safety of the molten salt battery can be improved. | 08-21-2014 |
20140241973 | METHOD FOR PRODUCING IMIDE SALT - A mixture of sulphamic acid, a halogenated sulphonic acid and thionyl chloride is heated to allow the reaction to proceed, to thereby produce first intermediate products. The first intermediate products are then subjected to reaction with an alkali metal fluoride MF to produce second intermediate products. The second intermediate products is then subjected to reaction with the alkali metal fluoride MF in a polar solvent to obtain a desired product MN(SO | 08-28-2014 |
20140285153 | METHOD FOR OPERATING MOLTEN SALT BATTERY - Provided is a method for operating a molten salt battery having a sodium compound (NaCrO | 09-25-2014 |
20140287302 | ANODE ACTIVE MATERIAL FOR SODIUM BATTERY, ANODE, AND SODIUM BATTERY - Sodium titanium oxide is used as an anode active material for a sodium battery to improve the cycle properties of the sodium battery. For example, the anode active material is preferably a sodium titanium oxide having the following composition formula (1) or (2). Na | 09-25-2014 |
20150229004 | HEAT RESISTANT BATTERY AND METHOD FOR CHARGING AND DISCHARGING THE SAME - A heat resistant battery includes a positive electrode including a positive electrode current collector and a positive electrode active material fixed on the positive electrode current collector, wherein the positive electrode active material includes a sodium-containing transition metal compound capable of electrochemically storing and releasing a sodium ion; a negative electrode including a negative electrode current collector and a negative electrode active material fixed on the negative electrode current collector, wherein the negative electrode active material contains at least one selected from the group consisting of a sodium-containing titanium compound and a non-graphitizable carbon, each of the sodium-containing titanium compound and the non-graphitizable carbon capable of storing and releasing a sodium ion at a lower potential than a potential of the sodium-containing transition metal compound; and a sodium ion-conductive electrolyte provided at least between the positive electrode and the negative electrode, wherein the sodium ion-conductive electrolyte includes a salt of an organic cation having a pyrrolidinium skeleton and a bis(perfluoroalkyl sulfonyl)imide anion. | 08-13-2015 |
20150249272 | SODIUM SECONDARY BATTERY - The present invention relates to a sodium secondary battery comprising a positive electrode which includes a positive electrode current collector and a positive electrode material, the positive electrode material being carried on the positive electrode current collector, wherein the positive electrode material comprises a positive electrode active material reversibly containing sodium cation; a negative electrode which includes a negative electrode current collector and a negative electrode material, the negative electrode material being carried on the negative electrode current collector, wherein the negative electrode material comprises a negative electrode active material reversibly containing sodium cation; an electrolyte interposed at least between the positive electrode and the negative electrode; and a separator for retaining the electrolyte and separating the positive electrode and the negative electrode from each other; wherein the negative electrode active material is amorphous carbon, and the electrolyte is a molten salt electrolyte which is a mixture of a salt composed of sodium cation and an anion and a salt composed of an organic cation and an anion. | 09-03-2015 |
20150295279 | MOLTEN SALT BATTERY AND METHOD FOR PRODUCING SAME - A molten salt battery comprising a positive electrode, a negative electrode, a separator interposed between the positive electrode and the negative electrode, and an electrolyte, wherein the electrolyte includes a molten salt, the molten salt contains at least sodium ions, and the moisture content We1 in the molten salt is 300 ppm or less in terms of mass ratio. | 10-15-2015 |
Patent application number | Description | Published |
20140254711 | EFFICIENT N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK - A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements. | 09-11-2014 |
20140254712 | VOLTAGE MODE DRIVER CIRCUIT FOR N-PHASE SYSTEMS - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line. | 09-11-2014 |
20140254732 | TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE - A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires. | 09-11-2014 |
20140254733 | CIRCUIT TO RECOVER A CLOCK SIGNAL FROM MULTIPLE WIRE DATA SIGNALS THAT CHANGES STATE EVERY STATE CYCLE AND IS IMMUNE TO DATA INTER-LANE SKEW AS WELL AS DATA STATE TRANSITION GLITCHES - A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions while compensating for skew in the different data lines, and masking data state transition glitches. | 09-11-2014 |
20140270005 | SHARING HARDWARE RESOURCES BETWEEN D-PHY AND N-FACTORIAL TERMINATION NETWORKS - A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding. | 09-18-2014 |
20140270026 | MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols. | 09-18-2014 |
20140286466 | MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING - A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions. | 09-25-2014 |
20140348214 | COMPACT AND FAST N-FACTORIAL SINGLE DATA RATE CLOCK AND DATA RECOVERY CIRCUITS - A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces. | 11-27-2014 |
20140372642 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols. | 12-18-2014 |
20140372643 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols. | 12-18-2014 |
20140372644 | CAMERA CONTROL INTERFACE EXTENSION BUS - System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation. | 12-18-2014 |
20150058507 | METHOD TO MINIMIZE THE NUMBER OF IRQ LINES FROM PERIPHERALS TO ONE WIRE - A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan. | 02-26-2015 |
20150074305 | METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE - To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device. | 03-12-2015 |
20150095537 | CAMERA CONTROL INTERFACE SLEEP AND WAKE UP SIGNALING - A device is provided comprising a control data bus including at least a first line. A master device may be coupled to the control data bus and configured to control the control data bus. A plurality of slave devices may be coupled to the control data bus and share the first line. The master device may be configured to send a single global wake up signal on the control data bus that causes any sleeping slave devices to wake up. Alternatively, the master device may send a global wake up signal followed by a targeted sleep signal to non-targeted slave devices to implement a “targeted wake up” of specific slave devices. The master device may send the single global wake up signal by bringing the first line low for a predetermined period of time. | 04-02-2015 |
20150098536 | N FACTORIAL DUAL DATA RATE CLOCK AND DATA RECOVERY - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively. | 04-09-2015 |
20150098537 | METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods. | 04-09-2015 |
20150100711 | LOW POWER CAMERA CONTROL INTERFACE BUS AND DEVICES - System, methods and apparatus are described for extracting data and clocks from a camera control interface bus. A transmit clock may be generated while transmitting symbols on the bus, and a receive clock may be extracted when receiving symbols from the bus. A heartbeat clock may be extracted by from symbols transmitted on the bus when the apparatus is not transmitting or receiving symbols. The transmit clock may be used to encode data in a sequence of symbols for transmission on a pair of connectors of the bus. The receive clock may be extracted by detecting transitions occurring between symbols transmitted on the bus, and generating the receive clock based on the transitions. The heartbeat clock may be used to control operations of the apparatus, or synchronize one or more function of the apparatus. The heartbeat clock may be encoded in a control word transmitted on the bus. | 04-09-2015 |
20150100712 | CAMERA CONTROL INTERFACE SLAVE DEVICE TO SLAVE DEVICE COMMUNICATION - In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus. | 04-09-2015 |
20150100713 | COEXISTENCE OF I2C SLAVE DEVICES AND CAMERA CONTROL INTERFACE EXTENSION DEVICES ON A SHARED CONTROL DATA BUS - A plurality of slave devices is coupled to a control data bus along with at least one master device that is managing access of slave devices to the control data bus. At least one slave device operates in a sI2C protocol mode of operation and at least one other slave device operates in a CCIe mode of operation. At least the slave devices using sI2C protocol mode use the control data bus for interrupt requests. In order to maintain the integrity of CCIe communications, the slave devices using the sI2C protocol mode disables issuing IRQs when the control data bus operates according to the CCIe mode. | 04-09-2015 |
20150100714 | SLAVE IDENTIFIER SCANNING AND HOT-PLUG CAPABILITY OVER CCIe BUS - System, methods and apparatus are described that facilitate transmission of data, particularly between two or more devices within an electronic apparatus. Embodiments disclosed herein relate to scanning for slave identifiers (SIDs) on a CCIe bus. A disclosed method includes transmitting a first inquiry on a control data bus, where the first inquiry includes a first configuration of bits, determining presence of a slave device that has a slave identifier that includes a second configuration of bits that matches the first configuration of bits, and repetitively transmitting additional inquiries on the control data bus with different configurations of bits until all bits of the slave identifier are determined The slave device may assert a response to each inquiry that includes a configuration of bits that matches a corresponding configuration of bits in the slave identifier. | 04-09-2015 |
20150100862 | ERROR DETECTION CAPABILITY OVER CCIe PROTOCOL - A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission. | 04-09-2015 |
20150120975 | CAMERA CONTROL SLAVE DEVICES WITH MULTIPLE SLAVE DEVICE IDENTIFIERS - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. An address list may associate each of a plurality of slave devices coupled to a control data bus with a plurality of slave device identifiers. Access to the control data bus may be controlled based on the address list such that, in a first mode of operation information may be broadcast to multiple slave devices using a first group slave device identifier and, in a second mode of operation, information may be exchanged with a single slave device using an individualized slave device identifier. | 04-30-2015 |
20150195211 | LOW-VOLTAGE DIFFERENTIAL SIGNALING OR 2-WIRE DIFFERENTIAL LINK WITH SYMBOL TRANSITION CLOCKING - Systems, methods and apparatus are described for use in a communications link having a number of connectors. A method for communication using differential signaling with symbol transition clocking signaling communicates symbols over a communications link without transmitting a clock signal in a dedicated lane of the communications link. At a receiver, clock information may be extracted without using a phase-locked loop. The method includes converting data bits into a plurality of transition numbers, converting the plurality of transition numbers into a sequence of symbols, and transmitting the sequence of symbols over a plurality of signal wires. A clock signal may be embedded in transitions between consecutive symbols in the sequence of symbols. Each consecutive pair of transition numbers in the plurality of transition numbers may include two transition numbers that are different from one another. The sequence of symbols may be transmitted as a plurality of differential signals. | 07-09-2015 |
20150199287 | CAMERA CONTROL INTERFACE EXTENSION WITH IN-BAND INTERRUPT - Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus from a master device, where data bits are transcoded into symbols for transmission across two lines of the bus and a clock signal is embedded within symbol transitions of the data transmissions, and providing an interrupt period, during which one or more slave devices coupled to the bus can assert an interrupt request on a first line of the bus, within part of a heartbeat transmission by the master device over the first line and a second tine of the bus. The interrupt request may be an indicator that the asserting slave device wishes to request some action by the master device. | 07-16-2015 |
20150199295 | RECEIVE CLOCK CALIBRATION FOR A SERIAL BUS - Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock. | 07-16-2015 |
20150220472 | INCREASING THROUGHPUT ON MULTI-WIRE AND MULTI-LANE INTERFACES - Systems, methods and apparatus extract data and clocks from a multi-wire bus that includes a first lane operated in accordance with a camera control interface (CCIe) mode of operation or a first lane operated in accordance with an N! mode of operation. Timing information derived from a sequence of symbols received from the first lane may be used to deserialize data received on a second lane of the multi-wire bus or decode a sequence of symbols received on the second lane. The symbols in a pair of consecutive symbols transmitted on the first lane cause different signaling states. Data on the second lane may be deserialized using on the receive clock derived from the timing information. In a CCIe lane, the final symbol of the sequence of symbols may be suppressed or a setup condition curtailed when the final symbol produces a signaling state equivalent to the setup condition. | 08-06-2015 |
20150234773 | TECHNIQUE TO AVOID METASTABILITY CONDITION AND AVOID UNINTENTIONAL STATE CHANGES OF LEGACY I2C DEVICES ON A MULTI-MODE BUS - A device may include an interface to couple to a multi-mode bus shared with one or more I2C-compatible devices. The bus may include a first line and a second line, wherein in a first mode of operation the first line transmits data and the second line transmits a clock, while in a second mode of operation the first and second lines are both used to transmit data. The device may also include a transmitter to transmit data over the bus (SDA line | 08-20-2015 |
20150234774 | COEXISTENCE OF LEGACY AND NEXT GENERATION DEVICES OVER A SHARED MULTI-MODE BUS - A device is provided comprising a bus, a first set of devices, and a second set of devices. The first set of devices is coupled to the bus and configured to communicate over the bus according to a first communication protocol. The second set of devices is coupled to the bus and configured to communicate over the bus according to both the first communication protocol and a second communication protocol. In a first mode of operation, the first set of devices and second set of devices may concurrently communicate over the bus using the first communication protocol. In a second mode of operation, the second set of devices communicate with each other using the second communication protocol over the bus, and the first set of devices to stop operating on the bus. | 08-20-2015 |
20150248373 | BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION - Various aspects directed towards facilitating an error detection optimization over a shared bus are disclosed. A master device is coupled to a slave device, and an encoded communication of a word is facilitated between the master device and the slave device via a control data bus. The encoded communication is encoded according to a protocol that allocates a plurality of least significant bits of the encoded communication to facilitate maximizing an error detection constant. The protocol allocates the plurality of least significant bits to include at least one additional error detection bit or at least a first most significant bit of a data portion of the word. | 09-03-2015 |
20150263823 | METHOD FOR USING ERROR CORRECTION CODES WITH N FACTORIAL OR CCI EXTENSION - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A data payload may be converted to a set of transition numbers, the transition numbers may be converted to a sequence of symbols and an error correction code (ECC) may be calculated from symbols in the sequence of symbols. The ECC corresponds to the data payload and the ECC may be appended to the data payload such that the set of transition numbers includes transition numbers corresponding to the ECC. The sequence of symbols is then transmitted on a plurality of signal wires. Clock information is encoded in the sequence of symbols. The clock information may be encoded by ensuring that each pair of consecutive symbols in the sequence of symbols includes two symbols that produce different signaling states on the plurality of signal wires. | 09-17-2015 |
20150286606 | METHODS TO SEND EXTRA INFORMATION IN-BAND ON INTER-INTEGRATED CIRCUIT (I2C) BUS - System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling. | 10-08-2015 |
20150286608 | METHODS TO SEND EXTRA INFORMATION IN-BAND ON INTER-INTEGRATED CIRCUIT (I2C) BUS - System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling. | 10-08-2015 |
20150295701 | MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS - System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link. | 10-15-2015 |
20150301980 | SYNCHRONIZATION METHOD FOR MULTI-SYMBOL WORDS - System, methods and apparatus are described that offer improved performance of a camera control interface (CCIe) bus. A method of data communications includes transmitting a first synchronization code on a serial bus, establishing synchronization with a first device coupled to the serial bus in response to the first synchronization code, communicating with the first device over the serial bus in accordance with a first protocol, after establishing synchronization with the first device, transmitting a first unsynchronization code on the serial bus, where the unsynchronization code is configured to cause a loss of synchronization with the first device, transmitting a second synchronization code on the serial bus, establishing synchronization with a second device coupled to the serial bus in response to the second synchronization code, and communicating with the second device over the serial bus in accordance with a second protocol, after establishing synchronization with the second device. | 10-22-2015 |
Patent application number | Description | Published |
20110170228 | DIELECTRIC CERAMIC COMPOSITION AND MONOLITHIC CERAMIC CAPACITOR - There is provided a dielectric ceramic composition suitable for, for example, a car-mounted monolithic ceramic capacitor used in a high-temperature environment. It is represented by the composition formula: 100(Ba | 07-14-2011 |
20110235236 | DIELECTRIC CERAMIC COMPOSITION AND MONOLITHIC CERAMIC CAPACITOR - Provided are a dielectric ceramic composition suitable for use in a monolithic ceramic capacitor that is employed in high-temperature environments such cars, and a monolithic ceramic capacitor constituted by using the dielectric ceramic composition. The dielectric ceramic composition has a composition formula of 100(Ba | 09-29-2011 |
20120170169 | DIELECTRIC CERAMIC AND LAMINATED CERAMIC CAPACITOR - A dielectric ceramic which is suitable for use in a laminated ceramic capacitor under a high-temperature environment, such as encountered in, for example, automobile use has a composition represented by the composition formula: (1−x) (Ba | 07-05-2012 |
20120326558 | LAMINATED CERAMIC ELECTRONIC COMPONENT - A laminated ceramic electronic component having excellent mechanical characteristics and internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, and low defective rate includes a laminate having a plurality of laminated ceramic layers and a plurality of Al/Cu alloy-containing internal electrodes at specific interfaces between ceramic layers; where the Al/Cu ratio of the Al/Cu alloy is 80/20 or more. | 12-27-2012 |
20120326559 | LAMINATED CERAMIC ELECTRONIC COMPONENT - Provided is a laminated ceramic electronic component having excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes: a laminate which has a plurality of laminated ceramic layers and internal electrodes at a plurality of specific interfaces between the ceramic layers and having an Al/Ni alloy as a component; and an external electrode formed on the outer surface of the laminate, wherein the Al/Ni ratio of the Al/Ni alloy is 85/15 or more. | 12-27-2012 |
20120326561 | LAMINATED CERAMIC ELECTRONIC COMPONENT - Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of ceramic material design freedom, low cost, low defective rate and various properties. It includes a laminate of a plurality of laminated ceramic layers and a plurality of internal electrodes at specific interfaces between ceramic layers. The internal electrodes contain an Al/Mg alloy in which the Al/Mg ratio is 65/35 or more. | 12-27-2012 |
20120326562 | LAMINATED CERAMIC ELECTRONIC COMPONENT - Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes a laminate which has a plurality of laminated ceramic layers and internal electrodes formed along at a plurality of specific interface between the ceramic layers and having an Al/Ti alloy as a component; and an external electrode formed on the outer surface of the laminate. The Al/Ti ratio of the Al/Ti alloy is 91/9 or more. | 12-27-2012 |
20130002092 | LAMINATED CERAMIC ELECTRONIC COMPONENT - Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes: a laminate which has a plurality of laminated ceramic layers and Al/Mn alloy internal electrodes at a plurality of specific interfaces between the ceramic layers and an external electrode formed on the outer surface of the laminate, wherein the Al/Mn ratio of the Al/Mn alloy is 80/20 or more. | 01-03-2013 |
20130107418 | DIELECTRIC CERAMIC COMPOSITION AND LAMINATED CERAMIC ELECTRONIC COMPONENT | 05-02-2013 |
20130140946 | LAMINATED CERAMIC ELECTRONIC COMPONENT - Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes: a laminate which has a plurality of laminated ceramic layers and Al/Si alloy-containing internal electrodes at a plurality of specific interface between ceramic layers; and an external electrode formed on the outer surface of the laminate, wherein the Al/Si ratio of the Al/Si alloy is 85/15 or more. | 06-06-2013 |
20130148256 | LAMINATED CERAMIC ELECTRONIC COMPONENT - A laminated ceramic electronic component includes a laminated body including a plurality of stacked ceramic layers and a plurality of internal electrodes arranged along interfaces between the ceramic layers, and an external electrode located on an outer surface of the laminated body. In the laminated ceramic electronic component, the ceramic layers have a composition including a main constituent of a barium titanate-based compound and Bi | 06-13-2013 |
20130194717 | DIELECTRIC CERAMIC, STACK CERAMIC ELECTRONIC COMPONENT, AND METHOD OF MANUFACTURING THESE - A dielectric ceramic enabling low-temperature firing and exhibiting good dielectric characteristics, and a stack ceramic electronic component using the same are provided. The dielectric ceramic containing (Ba | 08-01-2013 |
20130321980 | MULTILAYER CERAMIC CAPACITOR AND METHOD FOR MANUFACTURING MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a multilayer body including a plurality of laminated dielectric layers and a plurality of internal electrodes arranged along interfaces between the dielectric layers, and a plurality of external electrodes located on an outer surface of the multilayer body and electrically connected to the internal electrodes. A main component of the internal electrodes is Ni, and the internal electrodes also contain Sn. | 12-05-2013 |
20130342958 | MULTILAYER CERAMIC CAPACITOR, DIELECTRIC CERAMIC, MULTILAYER CERAMIC ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING MULTILAYER CERAMIC CAPACITOR - A dielectric ceramic that can be sintered at a sufficiently low temperature and has a desired specific resistance at a high temperature, and a multilayer ceramic electronic component (a multilayer ceramic capacitor and the like) using the dielectric ceramic are provided. The multilayer ceramic capacitor includes a multilayer body having a plurality of laminated dielectric ceramic layers, and a plurality of internal electrodes at interfaces between the dielectric ceramic layers; and external electrodes | 12-26-2013 |
20140016243 | MULTILAYER CERAMIC CAPACITOR, DIELECTRIC CERAMIC, MULTILAYER CERAMIC ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING MULTILAYER CERAMIC CAPACITOR - Provided in a dielectric ceramic having flat capacitance characteristics and a high dielectric constant, and a multilayer ceramic electronic component (such as a multilayer ceramic capacitor) in which the dielectric ceramic is used. A multilayer ceramic capacitor includes a multilayer body having a plurality of dielectric ceramic layers and a plurality of internal electrodes, and external electrodes formed on the multilayer body. The composition of the multilayer body includes any of a bismuth layered compound containing Sr, Bi and Ti, a bismuth layered compound containing Sr, Bi and Nb, and a bismuth layered compound containing Ca, Bi and Ti as a primary ingredient, Bi and at least one of Cu, Ba, Zn and Li, and satisfies the conditions that if the Ti content is 400 molar parts or the Nb content is 200 molar parts, then (Bi content-Ti content) or (Bi content-Nb content) is equal to or greater than 1 molar part and less than 7.5 molar parts and the total content of Cu, Ba, Zn and Li is equal to or greater than 1 molar part and less than 10 molar parts. | 01-16-2014 |
20140022696 | ELECTRONIC COMPONENT - A laminate body includes a plurality of ceramic layers and capacitor conductors embedded in the laminate body so as to be opposed to each other via one of the ceramic layers. The capacitor conductors are made of an Al-based material, and the capacitor conductors include narrow portions, respectively, which function as fuse elements. The narrow portions have an average width smaller than an average width of portions of the capacitor conductors other than the narrow portions. As a result, the electronic component has an improved capability to protect its function as a capacitor when a short circuit occurs between capacitor conductors. | 01-23-2014 |
20140175942 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING MULTILAYER CERAMIC ELECTRONIC COMPONENT - A multilayer ceramic electronic component achieves a high electrostatic capacitance and includes an Al inner electrode superior in smoothness and conductivity. The multilayer ceramic electronic component includes a multilayer body including a plurality of stacked ceramic layers and a plurality of inner electrodes arranged along certain interfaces between the ceramic layers and containing Al as a main component, and an outer electrode located on an outer surface of the multilayer body. A surface of the inner electrode is covered with a layer including a noble metal or Ti as a main component. | 06-26-2014 |
20150155098 | LAMINATED CERAMIC CAPACITOR AND METHOD FOR MANUFACTURING LAMINATED CERAMIC CAPACITOR - A laminated ceramic capacitor that includes a ceramic laminated body having a stacked plurality of ceramic dielectric layers and a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween, and external electrodes on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes. The internal electrodes contain Ni and Sn, a proportion of the Sn/(Ni+Sn) ratio is 0.001 or more in molar ratio is 75% or more in a region of the internal electrode at a depth of 20 nm from a surface opposed to the ceramic dielectric layer, and the proportion of the Sn/(Ni+Sn) ratio is 0.001 or more in molar ratio is less than 40% in a central region in a thickness direction of the internal electrode. | 06-04-2015 |