Patent application number | Description | Published |
20100099245 | Methods of Forming Semiconductor Devices - Provided are a semiconductor device and a method of forming the same. The method may include forming a metal oxide layer on a substrate and forming a sacrificial oxide layer on the metal oxide layer. An annealing process is performed on the substrate. A formation-free energy of the sacrificial oxide layer is greater than a formation-free energy of the metal oxide layer at a process temperature of the annealing process. | 04-22-2010 |
20100102399 | Methods of Forming Field Effect Transistors and Devices Formed Thereby - Methods of forming field effect transistors include forming a first gate electrode on a semiconductor substrate and forming insulating spacers on sidewalls of the first gate electrode. At least a portion of the first gate electrode is then removed from between the insulating spacers to thereby expose inner sidewalls of the insulating spacers. Threshold-voltage adjusting impurities are then implanted into the semiconductor substrate, using the insulating spacers as an implant mask. These threshold-voltage adjusting impurities are selected from a group consisting of alkali metals from Group 1 of the periodic chart and halogens from Group 17 of the periodic chart. A second gate electrode is then formed between the inner sidewalls of the insulating spacers. | 04-29-2010 |
20120214296 | Methods of Forming Semiconductor Devices - Provided are a semiconductor device and a method of forming the same. The method may include forming a metal oxide layer on a substrate and forming a sacrificial oxide layer on the metal oxide layer. An annealing process is performed on the substrate. A formation-free energy of the sacrificial oxide layer is greater than a formation-free energy of the metal oxide layer at a process temperature of the annealing process. | 08-23-2012 |
20130149835 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners. | 06-13-2013 |
20150108584 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners. | 04-23-2015 |