Chian
Chan-Jui Chian, Taipei City TW
Patent application number | Description | Published |
---|---|---|
20090161660 | SYSTEM, METHOD, AND RECORDING MEDIUM FOR SCHEDULING PACKETS TO BE TRANSMITTED - A system for scheduling packets to be transmitted is provided. The system includes a soft delay bound calculator module and a frame determination module. The soft delay bound calculator module calculates a soft delay bound for a non-real-time packet based on a packet size of the non-real-time packet and a minimum reserved traffic rate of a channel. The frame determination module determines whether a real-time packet must be transmitted at a current frame according to a delay bound, a transmission time, and a possible retransmission time thereof, and whether a non-real-time packet must be transmitted at a current frame according to a soft delay bound, a transmission time, and a possible retransmission time thereof. Thus, it is possible to improve the performance of the system while keeping the QoS thereof in a mixed service environment. | 06-25-2009 |
Ian-Wei Chian, Kaohsiung TW
Patent application number | Description | Published |
---|---|---|
20110089025 | METHOD FOR MANUFACTURING A CHIP RESISTOR HAVING A LOW RESISTANCE - The present invention relates to a method for manufacturing a chip resistor having a low resistance. The method includes the following steps: (a) providing a substrate having a top surface; (b) sputtering a conducting layer directly on the top surface of the substrate, so that the conducting layer and the substrate contact each other, wherein the material of the conducting layer comprises nickel or copper; and (c) plating at least one metal layer directly on the conducting layer, so that the metal layer and the conducting layer contact each other, wherein the material of the metal layer comprises nickel or copper, and the conducting layer and the metal layer provide a resistive layer. As a result, the resistive layer has a precise pattern, and the duration of sputtering is reduced, so the yield rate and the efficiency are improved and the manufacturing cost is cut down. | 04-21-2011 |
20110234365 | CHIP RESISTOR HAVING LOW RESISTANCE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a chip resistor having low resistance and a method for manufacturing the same. The chip resistor includes a substrate, a resistive layer, a pair of conducting layers and at least one protective layer. The substrate has a first surface. The resistive layer is disposed on the first surface of the substrate. The conducting layers are disposed adjacent to the first surface of the substrate. The at least one protective layer is disposed on the resistive layer or the conducting layers. As a result, the resistive layer has a precise pattern, and the duration of sputtering is reduced, thereby improving yield rate and efficiency while reducing manufacturing cost. | 09-29-2011 |
Kerm Sin Chian, Singapore SG
Patent application number | Description | Published |
---|---|---|
20100093093 | MANUFACTURING THREE-DIMENSIONAL SCAFFOLDS USING ELECTROSPINNING AT LOW TEMPERATURES - The present invention refers to an apparatus and a method for the manufacture of a three-dimensional scaffold at low temperatures and the respective use of this method and apparatus. | 04-15-2010 |
20100190254 | THREE-DIMENSIONAL POROUS HYBRID SCAFFOLD AND MANUFACTURE THEREOF - The present invention refers to a three-dimensional porous hybrid scaffold for tissue engineering and methods of its manufacture and use. | 07-29-2010 |
20100291176 | MANUFACTURING THREE-DIMENSIONAL SCAFFOLDS USING CRYOGENIC PROTOTYPING - The present invention refers to a method of fabricating a three dimensional scaffold suitable for tissue-engineering having a controlled micro- and macroporous structure using cryogenic prototyping. The present invention also refers to scaffolds obtained by the method of the present invention and to their use. | 11-18-2010 |
Martin Chian, Menlo Park, CA US
Patent application number | Description | Published |
---|---|---|
20150268227 | QUANTITATIVE MEASUREMENT OF HUMAN BLASTOCYST AND MORULA MORPHOLOGY DEVELOPMENTAL KINETICS - Methods, compositions and kits for determining the developmental potential of one or more embryos are provided. These methods, compositions and kits find use in identifying embryos in vitro that are most useful in treating infertility in humans. | 09-24-2015 |
Martin Tsupon Chian, Los Altos, CA US
Patent application number | Description | Published |
---|---|---|
20110028859 | Methods, Systems and Devices for Monitoring a Target in a Neural System and Facilitating or Controlling a Cell Therapy - Methods, systems and devices for monitoring a target in a neural system involve delivering inputs to and recording output responses from the neural system and obtaining I/O characterizations of the neural system both before and during or after a change is introduced to the system, for example, a change associated with a stem cell therapy. Baseline and therapeutic I/O characterizations are compared, and interpretations of the results of the comparison may be used to adjust some aspect of the therapy to facilitate it or control it. An implantable neurostimulator with the capability of delivering electrical stimulation to an electrode and of measuring and recording responses sensed from electrodes, where the electrodes are strategically positioned at or near the target, can be used to deliver an electrical stimulation input and record the output responses for the I/O characterizations. An implantable neurostimulator also may be used to affect a cell therapy by delivering electrical stimulation to the neural system to encourage stem cell differentiation. | 02-03-2011 |
Ming-Chung Chian, Changhua County TW
Patent application number | Description | Published |
---|---|---|
20100283146 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure. | 11-11-2010 |
Mojy Curtis Chian, Laguna Niguel, CA US
Patent application number | Description | Published |
---|---|---|
20100123213 | METAL-INSULATOR-METAL CAPACITORS - Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field. | 05-20-2010 |