Patent application number | Description | Published |
20080232157 | RANDOM ACCESS MEMORIES WITH AN INCREASED STABILITY OF THE MOS MEMORY CELL - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM and NVM devices. | 09-25-2008 |
20080233685 | METHOD OF MANUFACTURE OF AN APPARATUS FOR INCREASING STABILITY OF MOS MEMORY CELLS - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method of manufacture of a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices. | 09-25-2008 |
20080238519 | Signaling circuit and method for integrated circuit devices and systems - Integrate circuit systems and semiconductor devices for generating, transmitting, receiving, and manipulating clock and/or data signals. A semiconductor device including a clock circuit having field effect transistors and a clock driver circuit having bipolar junction transistors is disclosed. The clock circuit may provide a first clock output having a first voltage swing. The clock driver circuit may receive the first clock output and provide a second clock output having a second voltage swing substantially less than the first voltage swing. The field effect transistors can be junction field effect transistors or insulated gate field effect transistors, or the like. The system/devices further including a translator circuit, for translating signals with a lower voltage swing into signals with a higher voltage swing, and a circuit block, for operating at such higher voltage swing. Further included are global and local wiring networks for communicating the signals between and among the individual circuits or system components. | 10-02-2008 |
20080272394 | JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING - Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact. | 11-06-2008 |
20090011710 | Common data line signaling and method - A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit. | 01-08-2009 |
20090017585 | Self Aligned Gate JFET Structure and Method - A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed. | 01-15-2009 |
20090142889 | Oxide Isolated Metal Silicon-Gate JFET - A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer. | 06-04-2009 |
20090174464 | APPARATUS AND METHOD FOR IMPROVED LEAKAGE CURRENT OF SILICON ON INSULATOR TRANSISTORS USING A FORWARD BIASED DIODE - Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection. | 07-09-2009 |
20090184734 | Method of Producing and Operating a Low Power Junction Field Effect Transistor - A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter. | 07-23-2009 |
20100046312 | Dynamic and Non-Volatile Random Access Memories with an Increased Stability of the MOS Memory Cells - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices. | 02-25-2010 |
20100134182 | Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors - An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown. | 06-03-2010 |
20100315128 | CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL DEVICES - Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode. | 12-16-2010 |
20140270621 | PHOTONIC MULTI-CHIP MODULE - The subject matter disclosed herein relates to a photonic module comprising: a plurality of metal pads to receive CMOS integrated circuit (IC) chips to be mounted on a silicon-on-insulator (SOI) wafer; electrical interface circuits to receive electrical signals from the CMOS IC chips and to modify the electrical signals; optical drivers to receive the modified electrical signals and to convert the modified electrical signals to optical signals; and a photonic layer on the SOI wafer comprising silicon optical waveguides and silica optical waveguides to transmit or receive the optical signals for communication among the CMOS IC chips. | 09-18-2014 |
20140270629 | OPTICAL WAVEGUIDE NETWORK OF AN INTERCONNECTING IC MODULE - The subject matter disclosed herein relates to a photonic module comprising: a silicon-on-insulator (SOI) wafer; one or more photonic components on the SOI wafer; a plurality of metal pads to receive integrated circuit (IC) chips to be mounted on the SOI wafer; silicon optical waveguides to transfer optical signals among terminals of individual the IC chips, wherein the silicon optical waveguides comprise portions of the SOI wafer; and silica optical waveguides to transfer optical signals among terminals of different the IC chips. | 09-18-2014 |