Patent application number | Description | Published |
20090144347 | STORAGE VOLUME SPANNING WITH INTELLIGENT FILE PLACEMENT AND/OR REARRANGEMENT - In some embodiments a determination is made as to whether a file is to be placed on a slower drive of a logical storage volume span or a faster drive of the logical storage volume span. The file is placed on the slower drive or the faster drive based on the determining, and a user does not need to be aware of whether the file has been placed on the slower drive or the faster drive. Other embodiments are described and claimed. | 06-04-2009 |
20100082995 | Methods to communicate a timestamp to a storage system - Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed. | 04-01-2010 |
20100299670 | SELECTIVE I/O PRIORITIZATION BY SYSTEM PROCESS/THREAD - Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and processes associated with each application executing on a system, apply one or more priority rules to the identified applications and processes to generate priority information, and transmit the priority information to a subsystem. The subsystem then matches received requests with the priority information and services the processes according to the priority information. | 11-25-2010 |
20150095737 | APPARATUS AND METHOD TO MANAGE HIGH CAPACITY STORAGE DEVICES - Apparatus, systems, and methods to manage high capacity memory devices are described. In one example, a controller comprises logic to receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA), compute a first system cyclic redundancy check (CRC) using a payload CRC, the namespace ID and the first extended LBA, store the first system CRC in association with the first extended LBA in a local memory, and write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a memory. Other examples are also disclosed and claimed. | 04-02-2015 |
20150199127 | SELECTIVE I/O PRIORITIZATION BY SYSTEM PROCESS/THREAD - Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and processes associated with each application executing on a system, apply one or more priority rules to the identified applications and processes to generate priority information, and transmit the priority information to a subsystem. The subsystem then matches received requests with the priority information and services the processes according to the priority information. | 07-16-2015 |
Patent application number | Description | Published |
20090003092 | DEVICE SELECTION CIRCUIT AND METHOD - Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals). | 01-01-2009 |
20090164719 | Storage performance improvement using data replication on a disk - In some embodiments, disk accesses made during normal operation of a disk drive are monitored. One or more data blocks on the disk drive are identified as candidates for replication on the disk drive in response to the monitoring. Each of the identified data blocks are replicated in at least one other place on the disk drive. Other embodiments are described and claimed. | 06-25-2009 |
20100146187 | ENDURANCE MANAGEMENT TECHNIQUE - According to embodiments of the present invention, endurance management techniques are disclosures. Adherence to endurance and data retention ratings are ensured by managing write accesses to a memory device. | 06-10-2010 |
20110145306 | METHOD FOR TRIMMING DATA ON NON-VOLATILE FLASH MEDIA - A method for trimming data on non-volatile flash media is generally presented. In this regard, in one embodiment, a method is introduced comprising allocating a temporary file that occupies free space on a flash memory, determining specific blocks of the flash memory that the temporary file occupies, generating TRIM commands for the specific blocks, and deleting the temporary file. Other embodiments are described and claimed. | 06-16-2011 |
20130262877 | APPARATUS, SYSTEM, AND METHOD FOR PROVIDING MEMORY ACCESS CONTROL - Described herein are apparatus, system, and method for providing memory access control to protect software (e.g., firmware backup) and other data. The method comprises providing, by a processor, a protected storage area in a memory for storing backup image of software; detecting corruption in the software; accessing the backup image of the software from the protected storage area; and updating the corrupted software using the backup image, wherein the protected storage area is a reserved storage area of the memory. | 10-03-2013 |
20130304978 | HIGH-PERFORMANCE STORAGE STRUCTURES AND SYSTEMS FEATURING MULTIPLE NON-VOLATILE MEMORIES - A memory storage system that includes at least a storage controller, a first non-volatile, solid-state memory and a second non-volatile, solid-state memory. The storage controller has an interface to receive commands from a host system. The first non-volatile, solid-state memory device is coupled with the storage controller to at least store data received from the host system. The second non-volatile, solid-state memory is coupled with the storage controller to store context information corresponding to the data stored in the first non-volatile, solid-state memory device. | 11-14-2013 |
20140003145 | ARCHITECTURES AND TECHNIQUES FOR PROVIDING LOW-POWER STORAGE MECHANISMS | 01-02-2014 |
20140173242 | METHOD AND APPARATUS FOR CONTROLLING A STORAGE DEVICE - A mass storage device such as a disk drive or SSD (solid state drive) employs optimization logic for reduced power consumption in a host personal electronic device that identifies and prioritizes performance and power trade-offs by considering user expectations, user presence and application responsiveness. The storage device receives commands and information from the host device indicative of user expectations about application invocation, data freshness, and usage patterns, and determines a operational state indicative of behavior settings for reducing power consumption while maintaining the performance constraints required by the user expectations. The granularity of performance considerations communicated from the host device to the mass storage device is expanded to permit the storage device to determine, based on performance constraints from user expectations, appropriate and specific power reduction measures for maintaining the user experience. | 06-19-2014 |
20140281599 | NAND PAGE BUFFER BASED VOLATILE STATE STORE - Apparatus and methods of reducing power consumption in solid-state storage devices such as solid-state disks (SSDs) that can reduce idle power levels in an SSD, while maintaining low resume latency upon exiting a reduced power state. By arranging a storage controller and at least one NAND flash package of the SSD in separate power islands, storing context information for the SSD in at least one page buffer of NAND flash memory within the NAND flash package on one power island upon entering the reduced power state, and, once the context information is stored in the page buffer, allowing the NAND flash memory to enter a standby mode, placing the storage controller on the other power island in a predefined low power mode, and removing power from any unneeded components on the same power island as the storage controller, a scalable approach to reducing idle power levels in the SSD can be achieved. | 09-18-2014 |
20150095550 | GENERATING RANDOM NUMBERS UTILIZING ENTROPIC NATURE OF NAND FLASH MEMORY MEDIUM - Methods and apparatus related to generating random numbers utilizing the entropic nature of NAND flash memory medium are described. In one embodiment, a data pattern is written to a portion of a non-volatile memory device and is subsequently read multiple times. Based on the read operations, at least one bit is marked for random number generation based at least partially on comparison of a number of flips by the at least one bit and a threshold value. Other embodiments are also disclosed and claimed. | 04-02-2015 |
20150149695 | SYSTEM AND METHOD FOR COMPUTING MESSAGE DIGESTS - A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage. | 05-28-2015 |
20150154066 | ERROR CORRECTION IN SOLID STATE DRIVES (SSD) - A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation. | 06-04-2015 |
20150186257 | MANAGING A TRANSFER BUFFER FOR A NON-VOLATILE MEMORY - Embodiments include apparatuses, method, and systems for managing a transfer buffer associated with a non-volatile memory. In one embodiment, controller logic may be coupled to a non-volatile memory and a transfer buffer. The controller logic may read a plurality of sectors of data from the non-volatile memory and store the read sectors in the transfer buffer. The controller logic may further allocate individual sectors to pages according to a completion time of the read of individual sectors of the plurality of sectors, the individual pages including a plurality of the sectors. The controller logic may further write the pages of sectors to the non-volatile memory responsive to a determination that all sectors of the page have been read. | 07-02-2015 |
20150355704 | METHOD FOR REDUCING POWER CONSUMPTION IN SOLID-STATE STORAGE DEVICE - Apparatus and methods of reducing power consumption in solid-state storage devices such as solid-state disks (SSDs) that can reduce idle power levels in an SSD, while maintaining low resume latency upon exiting a reduced power state. By arranging a storage controller and at least one NAND flash package of the SSD in separate power islands, storing context information for the SSD in at least one page buffer of NAND flash memory within the NAND flash package on one power island upon entering the reduced power state, and, once the context information is stored in the page buffer, allowing the NAND flash memory to enter a standby mode, placing the storage controller on the other power island in a predefined low power mode, and removing power from any unneeded components on the same power island as the storage controller, a scalable approach to reducing idle power levels in the SSD can be achieved. | 12-10-2015 |
20150378814 | EXTENSIBLE MEMORY HUB - The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies. | 12-31-2015 |
20160092361 | CACHING TECHNOLOGIES EMPLOYING DATA COMPRESSION - Caching technologies that employ data compression are described. The technologies of the present disclosure include cache systems, methods, and computer readable media in which data in a cache line is compressed prior to being written to cache memory. In some embodiments the technologies enable a caching controller to understand the degree to which data in a cache line is compressed, prior to writing the compressed data to cache memory. Consequently the cache controller may determine where the compressed data is to be stored in cache memory based at least in part on the size of the compressed data, a compression ratio attributable to the compressed data (or its corresponding input data), or a combination thereof. | 03-31-2016 |