Patent application number | Description | Published |
20120269291 | RF TRANSMITTER, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter has at least one digital signal processing module and at least one power amplifier module. The digital signal processing module includes at least one digital pre-distortion component arranged to receive at least one complex input signal, perform two-dimensional non-uniform mapping of the complex input signal to a first, in-phase, digital pre-distortion control word and a further, quadrature, digital pre-distortion control word, and output the in-phase and quadrature pre-distortion digital control words. The power amplifier module includes a first, in-phase, array of switch-mode power cells and at least one further, quadrature, array of switch-mode power cells. The two-dimensional non-uniform mapping has a pre-distortion profile at least partly based on an input/output relationship for the power amplifier module arranged to generate an analogue RF signal based at least partly on the in-phase and quadrature digital pre-distortion control words. | 10-25-2012 |
20120269293 | RF TRANSMITTER ARCHITECTURE, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter architecture includes at least one digital signal processing module. The at least one digital signal processing module is configurable to operate in at least a first mode wherein the at least one digital signal processing module is arranged to receive a digital input signal, select, from a reduced set of digital power amplifier (DPA) control values, a plurality of DPA control values based at least partly on the received digital input signal, perform interpolation of the plurality of selected DPA control values to determine a DPA control value from a non-reduced set of DPA control values representative of the received digital input signal, and output to at least one DPA component the determined DPA control value representative of the received digital input signal. | 10-25-2012 |
20130279630 | CIRCUIT AND TRANSMITTER FOR REDUCING TRANSMITTER GAIN ASYMMETRY VARIATION - The present invention provides for a circuit with slicing wherein a gain asymmetry variation is decreased across the plurality of mixer slices. In one or more embodiments, a calibration unit can be provided to determine the characteristics of gain asymmetry variation; and a digital compensation unit can be provided to adjust the gain of the circuit over frequency. | 10-24-2013 |
20140112414 | POWER AMPLIFIER AND THE RELATED POWER AMPLIFYING METHOD - A power amplifier includes: a plurality of amplifying stages arranged to generate an output signal at an output terminal according to a phase-modulated signal and a plurality of amplitude-modulated signals, where each amplifying stage is arranged to receive the phase-modulated signal and one of the plurality of amplitude-modulated signals; an inductive circuit coupled between the output terminal and a first reference voltage; a matching circuit coupled between the output terminal and a loading circuit for providing a matching impedance between the output terminal and the loading circuit; and a capacitive circuit coupled to the output terminal for providing an adjustable capacitance to adjust a loading capacitance at the output terminal according to an adjusting signal; wherein the adjusting signal is indicative of a power of the output signal. | 04-24-2014 |
20140177755 | RF TRANSMITTER, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter includes a power amplifier comprising a plurality of power amplifier cells. At least one digital signal processing module of the RF transmitter is operably coupled to the power amplifier and comprises at least one digital pre-distortion component arranged to apply at least one digital pre-distortion codeword to the plurality of power amplifier cells, wherein the at least one digital pre-distortion codeword is applied to at least one of the plurality of power amplifier cells via a digital filter. A combiner is arranged to combine outputs of the plurality of power amplifier cells thereby generating an analogue RF signal for transmission over an RF interface based at least partly on the digitally filtered at least one digital pre-distortion codeword. | 06-26-2014 |
20140355717 | RADIO FREQUENCY TRANSMITTER WITH EXTENDED POWER RANGE AND RELATED RADIO FREQUENCY TRANSMISSION METHOD - A radio frequency transmitter includes a digital power amplifier and a bias control circuit. The digital power amplifier is arranged for receiving at least a radio frequency input signal, a digital amplitude control word signal and at least one bias voltage to generate a radio frequency output signal. The bias control circuit is coupled to the digital power amplifier, and is arranged for adjusting the at least one bias voltage according to a power control signal. | 12-04-2014 |
Patent application number | Description | Published |
20140209993 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 07-31-2014 |
20150017795 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 01-15-2015 |
20150097224 | BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. | 04-09-2015 |
20150097245 | SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC. | 04-09-2015 |
Patent application number | Description | Published |
20100181573 | GATED CO-PLANAR POLY-SILICON THIN FILM DIODE - A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate. | 07-22-2010 |
20100230139 | PRINTED CIRCUIT BOARDS BY MASSIVE PARALLEL ASSEMBLY - A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together. | 09-16-2010 |
20120297618 | PRINTED CIRCUIT BOARDS BY MASSIVE PARALLEL ASSEMBLY - A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. | 11-29-2012 |
20130164900 | GATED CO-PLANAR POLY-SILICON THIN FILM DIODE - A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate. | 06-27-2013 |
20140106512 | MICROCHIP CHARGE PATTERNING - A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and using an external device to develop charge in the material. | 04-17-2014 |
20140106541 | MICROCHIP CHARGE PATTERNING - A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid. | 04-17-2014 |
20140159746 | CAPACITIVE IMAGING DEVICE WITH ACTIVE PIXELS - An apparatus includes a sensor array with a plurality of active pixels. Each active pixel in the sensor array includes: a three transistor (3T) sensor with a source follower transistor, and a detection diode coupled in series to a parasitic capacitor at a sensing junction. A gate of the source follower transistor amplifier is coupled to the sensing junction. The apparatus includes an insulator layer over the sensor array. The insulator layer provides a variable capacitance to the sensing junctions of underlying active pixels in response to portions of an object being proximate to the insulator layer. The variable capacitance is used to detect an image of the object. | 06-12-2014 |
20140272121 | Digital 3D Fabrication Using Multi-Layered Mold - A replica 3D structure is fabricated inside a multi-layered mold by patterning each mold layer to define a void/opening that matches a corresponding cross section of the structure's peripheral surface, and filling the patterned opening of each layer with a structural material (i.e., before depositing a subsequent layer of mold material). The mold material (e.g., photoresist or another dissolvable sacrificial material) is blanket deposited (e.g., by slot-die, spray coating) and then patterned using a laser or a printed mask. Each layer of modeling material (e.g., polymer, ceramic or metal, or a combination thereof) is electro-plated or otherwise deposited on the previously formed modeling material layer. High vertical resolution is achieved by utilizing relatively thin mold layers. The mold layer deposition, patterning and modeling material deposition is repeated until the replica 3D structure is entirely formed inside the multi-layered mold, and then the mold is dissolved or otherwise removed. | 09-18-2014 |
20150076961 | METHOD FOR REDUCTION OF STICTION WHILE MANIPULATING MICRO OBJECTS ON A SURFACE - A system and method reduce stiction while manipulating micro objects on a surface. The system and method employed a field generator configured to generate a driving force at a frequency and amplitude to at least partially overcome stiction between the micro objects and the surface. The field generator is further configured to generate a manipulation force to manipulate the micro objects on the surface in two dimensions. The manipulation force is spatially programmable. | 03-19-2015 |
20150077172 | EXTERNALLY INDUCED CHARGE PATTERNING USING RECTIFYING DEVICES - A system and method form charge patterns on micro objects. The system and method employ a micro object including a rectifying device. The rectifying device exhibits an asymmetric current-voltage (I-V) response curve. Further, the system and method employ a device external to the micro object to induce the flow of charge through the rectifying device. | 03-19-2015 |
20150102852 | Stressed Substrates For Transient Electronic Systems - A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event. | 04-16-2015 |
20150243528 | Fabrication Method For Microelectronic Components And Microchip Inks Used In Electrostatic Assembly - Charge-encoded chiplets are produced using a sacrificial metal mask and associated fabrication techniques and materials that are compatible with typical semiconductor fabrication processes to provide each chiplet with two different (i.e., positive and negative) charge polarity regions generated by associated patterned charge-inducing material structures. A first charge-inducing material (e.g., SiO | 08-27-2015 |
Patent application number | Description | Published |
20080213628 | Perpendicular recording media with Ta transition layer to improve magnetic and corrosion resistance performances and method of manufacturing the same - A perpendicular magnetic recording medium comprising a substrate, an underlayer, a Ta-containing seedlayer, a magnetic layer, wherein the underlayer comprises a soft magnetic material and the Ta-containing seedlayer is between the underlayer and the magnetic layer, and a process for improving corrosion resistance of the recording medium and for manufacturing the recording medium are disclosed. | 09-04-2008 |
20100007989 | HIGH DENSITY GRANULAR PERPENDICULAR RECORDING MEDIA FOR MECHANICAL RELIABILITY AND CORROSION RESISTANCE - An embodiment of the invention relates to a perpendicular magnetic recording medium comprising (1) a substrate, (2) an interlayer comprising hexagonal columns and (3) a magnetic layer, wherein the magnetic layer is deposited applying a bias voltage to the substrate such that the magnetic layer comprises magnetic grains having substantially no sub-grains within the magnetic layer, and the magnetic layer has perpendicular magnetic anisotropy. | 01-14-2010 |
20100209737 | MAGNETIC RECORDING MEDIA WITH ENHANCED WRITABILITY AND THERMAL STABILITY - Aspects are directed to recording media with enhanced magnetic properties for improved writability. Examples can be included or related to methods, systems and components that allow for improved writability while reducing defects so as to obtain uniform magnetic properties such as uniformly high anisotropy and narrow switching field distribution. Some examples include a recording medium with an exchange tuning layer inserted between the hard layer and the soft, semi-soft or thin semi-hard layer so as to maximize the writability improvement of the media. Preferably, the exchange tuning layer is granular and reduces or optimizes the vertical coupling between the hard layer and the soft, semi-soft or semi-hard layer of a magnetic recording or storing device. | 08-19-2010 |
20100209739 | MAGNETIC STORAGE MEDIA WITH Ag, Au-CONTAINING MAGNETIC LAYERS - A magnetic recording medium having a Au, Ag-containing magnetic layer having Co, Cr, Ag and Au; the magnetic recording layer having Co-containing magnetic grains surrounded by substantially nonmagnetic Cr-containing grain boundaries; wherein said Ag and said Au are substantially immiscible in the Co-containing magnetic grains is disclosed. | 08-19-2010 |
20130163118 | RECORDING MEDIUM WITH THIN STABILIZATION LAYER HAVING HIGH MAGNETIC SATURATION AND ANISOTROPIC FIELD CHARACTERISTICS - A perpendicular recording medium with enhanced magnetic stability. In accordance with some embodiments, a multi-layer recording structure is formed on a base substrate and adapted to magnetically store a magnetic bit sequence in domains substantially perpendicular to said layers. A thin magnetic stabilization layer is formed on the multi-layer recording substrate to magnetically stabilize an upper portion of the recording structure. | 06-27-2013 |
Patent application number | Description | Published |
20080276017 | SYSTEM AND ARTICLE OF MANUFACTURE FOR THE DETECTION OF MISDIRECTED DATA - Provided are a system and article of manufacture, wherein in certain embodiments an I/O command from a host is received at a first storage unit. An identifier is generated that identifies a destination to which the I/O command is to be transmitted from the first storage unit. The I/O command is augmented with the generated identifier at the first storage unit. The augmented I/O command is transmitted. In certain other embodiments, an I/O command is received at a storage unit, wherein the storage unit is associated with a storage unit identifier. A determination is made at the storage unit, whether the I/O command is associated with an identifier that identifies a destination for which the I/O command is intended. A further determination is made, at the storage unit, whether the identifier is the same as the storage unit identifier, in response to determining that the identifier associated with the I/O command identifies the destination for which the I/O command is intended. | 11-06-2008 |
20090013099 | SYSTEM AND PROGRAM FOR TRANSMITTING INPUT/OUTPUT REQUESTS FROM A FIRST CONTROLLER TO A SECOND CONTROLLER - Provided are a method, system, and program monitoring paths between a first controller and second controller. A determination is made as to whether one path has been unavailable for a predetermined time period in response to detecting that the path is unavailable. Indication is made that the path is in a first failed state if the path has been unavailable for more than the predetermined time period and indication is made that the path is in a second failed state if the path has not been unavailable for the predetermined time period. | 01-08-2009 |
20100088434 | FCP COMMAND-DATA MATCHING FOR WRITE OPERATIONS - A method for performing a data exchange between an initiator and a receiver in a fibre channel protocol (FCP) is provided. A control flag is set in a write command to indicate the presence of an identifier. The identifier is copied into a command descriptor block (CDB) of the write command and appended to a data frame. The write command and data frame, including the identifier, is sent from the initiator to the receiver. | 04-08-2010 |
Patent application number | Description | Published |
20130105887 | Vertical Gate LDMOS Device | 05-02-2013 |
20130105888 | Transistor with Buried P+ and Source Contact | 05-02-2013 |
20130109143 | Vertical Gate LDMOS Device | 05-02-2013 |
20130115744 | Vertical Gate LDMOS Device - A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material. | 05-09-2013 |
20130234249 | Methods and Apparatus for LDMOS Transistors - An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region. | 09-12-2013 |
20140134834 | Method of Fabricating Power Transistor with Protected Channel - A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source. | 05-15-2014 |
20140147979 | Vertical Gate LDMOS Device - A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material. | 05-29-2014 |
20140266091 | Voltage Regulators with Load-Dependent Bias - This document describes systems and techniques related to voltage regulators. The subject matter of this document can be embodied in a method that includes measuring an output current of a switching regulator. The switching regulator includes a high-side transistor and a low side-transistor wherein the high-side transistor and the low-side transistor are driven using a first gate voltage and a second, different gate voltage, respectively. The method also includes adjusting a direct-current (DC) voltage source of the switching regulator such that the first gate voltage is adjusted in accordance with the measured output current. | 09-18-2014 |
20140266113 | Voltage Regulators with Multiple Transistors - A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal. | 09-18-2014 |
20140374826 | Vertical Gate LDMOS Device - Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region. | 12-25-2014 |
Patent application number | Description | Published |
20090211980 | ION CHROMATOGRAPHY SYSTEMS WITH FLOW-DELAY ELUENT RECYCLE - A chromatographic method including chromatographically separating sample ionic species in an eluent stream, detecting the separated sample ionic species, catalytically combining hydrogen and oxygen gases or catalytically decomposing hydrogen peroxide in a catalytic gas elimination chamber, and recycling the effluent stream from the chamber to the chromatography separation column. The residence time between the detector and the chamber is at least about one minute. Also, flowing the recycle sequentially through two detector effluent flow channels of an electrolytic membrane suppressor. Also, applying heat or UV energy between the detector and the chamber. Also, detecting bubbles after the chamber. Also, a Platinum group metal catalyst and ion exchange medium in the chamber. Apparatus for performing the methods. | 08-27-2009 |
20090289009 | Ion chromatography systems with flow-delay eluent recycle - A chromatographic method including chromatographically separating sample ionic species in an eluent stream, detecting the separated sample ionic species, catalytically combining hydrogen and oxygen gases or catalytically decomposing hydrogen peroxide in a catalytic gas elimination chamber, and recycling the effluent stream from the chamber to the chromatography separation column. The residence time between the detector and the chamber is at least about one minute. Also, flowing the recycle sequentially through two detector effluent flow channels of an electrolytic membrane suppressor. Also, applying heat or UV energy between the detector and the chamber. Also, detecting bubbles after the chamber. Also, a Platinum group metal catalyst and ion exchange medium in the chamber. Apparatus for performing the methods. | 11-26-2009 |
20110174737 | ION CHROMATOGRAPHY SYSTEMS WITH FLOW-DELAY ELUENT RECYCLE - A chromatographic method including chromatographically separating sample ionic species in an eluent stream, detecting the separated sample ionic species, catalytically combining hydrogen and oxygen gases or catalytically decomposing hydrogen peroxide in a catalytic gas elimination chamber, and recycling the effluent stream from the chamber to the chromatography separation column. The residence time between the detector and the chamber is at least about one minute. Also, flowing the recycle sequentially through two detector effluent flow channels of an electrolytic membrane suppressor. Also, applying heat or UV energy between the detector and the chamber. Also, detecting bubbles after the chamber. Also, a Platinum group metal catalyst and ion exchange medium in the chamber. Apparatus for performing the methods. | 07-21-2011 |
20110290726 | HIGH PRESSURE DEGAS ASSEMBLY FOR CHROMATOGRAPHY SYSTEM AND METHOD - A degas assembly including a low pressure fluid channel for carrying a wash fluid at a first pressure, a pressurized channel for carrying eluent including a gas at a second pressure higher than the first pressure, and a degas separator defining a fluid barrier between the low pressure fluid channel and pressurized fluid channel, the separator configured to retain liquid in the pressurized fluid channel and allow gas to flow through the separator to the low pressure fluid channel. The pressurized fluid channel may extend along an outer periphery of the low pressure fluid channel. The eluent may be received from an eluent generator at a pressure of at least about 3300 psi, and in various embodiments up to about 5000 psi. A liquid chromatography system and method are also disclosed. | 12-01-2011 |
20130256232 | ION CHROMATOGRAPHY SYSTEMS WITH FLOW-DELAY ELUENT RECYCLE - A chromatographic method including chromatographically separating sample ionic species in an eluent stream, detecting the separated sample ionic species, catalytically combining hydrogen and oxygen gases or catalytically decomposing hydrogen peroxide in a catalytic gas elimination chamber, and recycling the effluent stream from the chamber to the chromatography separation column. The residence time between the detector and the chamber is at least about one minute. Also, flowing the recycle sequentially through two detector effluent flow channels of an electrolytic membrane suppressor. Also, applying heat or UV energy between the detector and the chamber. Also, detecting bubbles after the chamber. Also, a Platinum group metal catalyst and ion exchange medium in the chamber. Apparatus for performing the methods. | 10-03-2013 |
20130259750 | ION CHROMATOGRAPHY SYSTEMS WITH FLOW-DELAY ELUENT RECYCLE - A chromatographic method including chromatographically separating sample ionic species in an eluent stream, detecting the separated sample ionic species, catalytically combining hydrogen and oxygen gases or catalytically decomposing hydrogen peroxide in a catalytic gas elimination chamber, and recycling the effluent stream from the chamber to the chromatography separation column. The residence time between the detector and the chamber is at least about one minute. Also, flowing the recycle sequentially through two detector effluent flow channels of an electrolytic membrane suppressor. Also, applying heat or UV energy between the detector and the chamber. Also, detecting bubbles after the chamber. Also, a Platinum group metal catalyst and ion exchange medium in the chamber. Apparatus for performing the methods. | 10-03-2013 |