Patent application number | Description | Published |
20090293030 | Concurrently Modeling Delays Between Points in Static Timing Analysis Operation - An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between points in the design. The delays are conveyed in multiple clock signals of a single timing run of a static timing analysis operation. Multiple paths comprising logical user defined delay segments are assigned different delays. Only one signal may be permitted to propagate along each path. | 11-26-2009 |
20090293031 | Replicating Timing Data in Static Timing Analysis Operation - An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least one path comprising logical user defined delay segments and a timing point may be associated with both a common point and no delay. An original clock signal may propagate along the logical path without incurring delay until arriving back at the common point, along with the original signal. All other clocks may be ignored or prevented from propagating long the path. Multiple replicated copies may be accomplished without requiring additional hardware. | 11-26-2009 |
20110265052 | EFFICIENTLY APPLYING A SINGLE TIMING ASSERTION TO MULTIPLE TIMING POINTS IN A CIRCUIT - A computer implemented method, system and/or computer program product efficiently manage timing parameters in a circuit. Multiple instances of a definition are implemented onto a circuit. A set of related pins from the multiple instances are defined, and a common assertion value is asserted against all pins in the set of related pins. | 10-27-2011 |
20110271245 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 11-03-2011 |
20120023466 | IMPLEMENTING FORWARD TRACING TO REDUCE PESSIMISM IN STATIC TIMING OF LOGIC BLOCKS LAID OUT IN PARALLEL STRUCTURES ON AN INTEGRATED CIRCUIT CHIP - A method, system and computer program product are provided for implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip. A common path pessimism removal algorithm is enhanced by a forward tracing parallel clock tree proximity credit algorithm that uses forward tracing, and computes a proximity credit that is applied to reduce pessimism in the static timing. | 01-26-2012 |
20120023469 | IMPLEMENTING TIMING PESSIMISM REDUCTION FOR PARALLEL CLOCK TREES - A computer-implemented method, system, and computer program product are provided for implementing timing pessimism reduction for parallel clock trees. A common path tracing algorithm in a static timing tool is enhanced to include a proximity credit used for pairs of gates in two clock trees that are placed in close proximity to each other. The proximity credit given is equal to a predefined fraction of a proximity component of a gate delay. | 01-26-2012 |
20120204138 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 08-09-2012 |
20130074021 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 03-21-2013 |
20130074022 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 03-21-2013 |
Patent application number | Description | Published |
20100018616 | ZIRCONIUM STRIP MATERIAL AND PROCESS FOR MAKING SAME - Methods for producing zirconium strips that demonstrate improved formability are disclosed. The zirconium strips of the present disclosure have a purity and crystalline microstructure suitable for improved formability, for example, in the manufacture of certain articles such as panels for plate heat exchangers and high performance tower packing components. Other embodiments disclosed herein relate to formed substantially pure zirconium strip, articles of manufacture produced from the substantially pure zirconium strip, and methods for making the articles of manufacture. | 01-28-2010 |
20110120602 | ZIRCONIUM STRIP MATERIAL AND PROCESS FOR MAKING SAME - Methods for producing zirconium strips that demonstrate improved formability are disclosed. The zirconium strips of the present disclosure have a purity and crystalline microstructure suitable for improved formability, for example, in the manufacture of certain articles such as panels for plate heat exchangers and high performance tower packing components. Other embodiments disclosed herein relate to formed substantially pure zirconium strip, articles of manufacture produced from the substantially pure zirconium strip, and methods for making the articles of manufacture. | 05-26-2011 |
20120273094 | ALLOY STRIP MATERIAL AND PROCESS FOR MAKING SAME - Methods for producing alloy strips including zirconium alloy strips that demonstrate improved formability are disclosed. The strips of the present disclosure have a purity and crystalline microstructure suitable for improved formability, for example, in the manufacture of certain articles such as panels for plate heat exchangers and high performance tower packing components. Other embodiments disclosed herein relate to formed alloy strip, articles of manufacture produced from the alloy strip, and methods for making the articles of manufacture. | 11-01-2012 |
20140130946 | ALLOY STRIP MATERIAL AND PROCESS FOR MAKING SAME - Methods for producing alloy strips that demonstrate improved formability are disclosed. The strips have a crystalline microstructure suitable for improved formability in the manufacture of various articles such as panels for plate heat exchangers and high performance tower packing components. | 05-15-2014 |
Patent application number | Description | Published |
20090091758 | Method of constructing a deviation angle self compensating substantially achromatic retarder to compensate beam traslation - A method of configuring a system for introducing a relative phase retardation into orthogonally polarized components of an electromagnetic beam entered thereinto, wherein the system involves a substantially achromatic multiple element retarder system for use in wide spectral range (for example, 190-1700 nm) rotating compensator spectroscopic ellipsometer and/or polarimeter systems. | 04-09-2009 |
20100220313 | Terahertz-infrared ellipsometer system, and method of use - The present invention relates to ellipsometer and polarimeter systems, and more particularly is an ellipsometer or polarimeter or the like system which operates in a frequency range between 300 GHz or lower and extending to higher than at least 1 Tera-hertz (THz), and preferably through the Infra-red (IR) range up to, and higher than 100 THz, including:
| 09-02-2010 |
20110188040 | Mounting for deviation angle self compensating substantially achromatic retarder - A system, method of configuring, and application a system for introducing a relative phase retardation into orthogonally polarized components of an electromagnetic beam entered thereinto, wherein the system involves a substantially achromatic multiple element retarder system for use in wide spectral range (for example, 190-1700 nm) rotating compensator spectroscopic ellipsometer and/or polarimeter systems. | 08-04-2011 |
20120206724 | Terahertz-infrared ellipsometer system, and method of use - The present invention relates to ellipsometer and polarimeter systems, and more particularly is an ellipsometer or polarimeter or the like system which operates in a frequency range between 300 GHz or lower and extending to higher than at least 1 Tera-hertz (THz), and preferably through the Infra-red (IR) range up to, and higher than 100 THz, including:
| 08-16-2012 |
20120261580 | Terahertz-infrared ellipsometer system, and method of use - The present invention relates to ellipsometer and polarimeter systems, and more particularly is an ellipsometer or polarimeter or the like system which operates in a frequency range between 300 GHz or lower and extending to higher than at least 1 Tera-hertz (THz), and preferably through the Infra-red (IR) range up to, and higher than 100 THz, including:
| 10-18-2012 |
20130026368 | Terahertz ellipsometer system, and method of use - A terahertz ellipsometer, the basic preferred embodiment being a sequential system having a backward wave oscillator (BWO); a first rotatable polarizer that includes a wire grid (WGP | 01-31-2013 |
20140027644 | Terahertz-infrared ellipsometer system, and method of use - The present invention relates to ellipsometer and polarimeter systems, and more particularly is an ellipsometer or polarimeter or the like system which operates in a frequency range between 300 GHz or lower and extending to higher than at least 1 Tera-hertz (THz), and preferably through the Infra-red (IR) range up to, and higher than 100 THz, including:
| 01-30-2014 |
20140284484 | Terahertz ellipsometer system, and method of use - A terahertz ellipsometer, the basic preferred embodiment being a sequential system having a backward wave oscillator (BWO); a first rotatable polarizer that includes a wire grid (WGP | 09-25-2014 |
20150153230 | TERAHERTZ-INFRARED ELLIPSOMETER SYSTEM, AND METHOD OF USE - A dual scanning and FTIR system for application in the Terahertz and broadband blackbody frequency range including sources for providing Thz and broadband blackbody range and electromagnetic radiation, at least one detector of electromagnetic radiation in the THZ and broadband blackbody ranges, and at least one rotating element between the source and detector. | 06-04-2015 |
Patent application number | Description | Published |
20090046103 | Shared readable and writeable global values in a graphics processor unit pipeline - An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented. | 02-19-2009 |
20090046105 | Conditional execute bit in a graphics processor unit pipeline - An arithmetic logic stage in a graphics processor unit includes a number of arithmetic logic units (ALUs). An instruction is applied to sets of operands comprising pixel data associated with different pixels. The value of a conditional execute bit determines how the pixel data in a set of operands is processed by the ALUs. | 02-19-2009 |
20090049276 | Techniques for sourcing immediate values from a VLIW - Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists. | 02-19-2009 |
20110254848 | Buffering deserialized pixel data in a graphics processor unit pipeline - An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs. | 10-20-2011 |
20130002703 | Non-Real-Time Dither Using a Programmable Matrix - A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value. | 01-03-2013 |
20130135351 | INLINE IMAGE ROTATION - Methods and apparatus for performing an inline rotation of an image. The apparatus includes a rotation unit for reading pixels from a source image in an order based on a specified rotation to be performed. The source image is partitioned into multiple tiles, the tiles are processed based on where they will be located within the rotated image, and each tile is stored in a tile buffer. The target pixel addresses within a tile buffer are calculated and stored in a lookup table, and when the pixels are retrieved from the source image by the rotation unit, the lookup table is read to determine where to write the pixels within a corresponding tile buffer. | 05-30-2013 |
20130215134 | Alpha Channel Power Savings in Graphics Unit - A graphics processing circuit and method for power savings in the same is disclosed. In one embodiment, a graphics processing circuit includes a number of channels. The number of channels includes a number of color component channels that are each configured to process color components of pixel values of an incoming frame of graphics information. The number of channels also includes an alpha scaling channel configured to process alpha values (indicative of a level of transparency) for the incoming and/or outgoing frames. The graphics processing circuit also includes a control circuit. The control circuit is configured to place the alpha scaling channel into a low-power state responsive to determining that at least one of the incoming or outgoing frames does not include alpha values. | 08-22-2013 |
20130222411 | EXTENDED RANGE COLOR SPACE - Techniques are disclosed relating to additive color systems. In one embodiment, an apparatus is disclosed that includes a device configured to operate on pixel data having color component values falling within an extended range outside of 0.0 to 1.0 corresponding to an extended range color space. In one embodiment, a gamma correction function is disclosed that can be applied to the pixel data, where the gamma correction function is applicable to both negative and positive values. Various embodiments of formats for arranging pixel data are also disclosed. | 08-29-2013 |
20130222413 | BUFFER-FREE CHROMA DOWNSAMPLING - Methods and graphics processing pipelines for performing inline chroma downsampling of pixel data. The graphics processing pipeline includes a chroma downsampling unit for performing buffer-free downsampling of chroma pixel components. A vertical column of chroma pixel components is received in each clock cycle by the chroma downsampling unit, and downsampled chroma pixel components are generated on every clock cycle or every other clock cycle. Vertical, horizontal, and vertical and horizontal downsampling can be performed without buffers by the chroma downsampling unit. A programmable configuration register in the chroma downsampling unit determines the type of downsampling that is implemented. | 08-29-2013 |
20130223733 | PIXEL NORMALIZATION - Methods and apparatuses for performing lossless normalization of input pixel component values. The apparatus includes a normalization unit for converting pixel values from a range of 0 to (2 | 08-29-2013 |
20130223764 | PARALLEL SCALER PROCESSING - A parallel scaler unit for simultaneously scaling multiple pixels from a source image. The scaler unit includes multiple vertical scalers and multiple horizontal scalers. A column of pixels from the source image is presented to the vertical scalers, and each vertical scaler selects appropriate pixels from the column of pixels for scaling. Each vertical scaler scales the selected pixels in a vertical direction and then conveys the vertically scaled pixels to a corresponding horizontal scaler. Each horizontal scaler scales the received pixels in a horizontal direction. | 08-29-2013 |
20150084969 | NEIGHBOR CONTEXT PROCESSING IN BLOCK PROCESSING PIPELINES - A block processing pipeline in which blocks are input to and processed according to row groups so that adjacent blocks on a row are not concurrently at adjacent stages of the pipeline. A stage of the pipeline may process a current block according to neighbor pixels from one or more neighbor blocks. Since adjacent blocks are not concurrently at adjacent stages, the left neighbor of the current block is at least two stages downstream from the stage. Thus, processed pixels from the left neighbor can be passed back to the stage for use in processing the current block without the need to wait for the left neighbor to complete processing at a next stage of the pipeline. In addition, the neighbor blocks may include blocks from the row above the current block. Information from these neighbor blocks may be passed to the stage from an upstream stage of the pipeline. | 03-26-2015 |
20150085931 | DELAYED CHROMA PROCESSING IN BLOCK PROCESSING PIPELINES - A block processing pipeline in which macroblocks are input to and processed according to row groups so that adjacent macroblocks on a row are not concurrently at adjacent stages of the pipeline. The input method may allow chroma processing to be postponed until after luma processing. One or more upstream stages of the pipeline may process luma elements of each macroblock to generate luma results such as a best mode for processing the luma elements. Luma results may be provided to one or more downstream stages of the pipeline that process chroma elements of each macroblock. The luma results may be used to determine processing of the chroma elements. For example, if the best mode for luma is an intra-frame mode, then a chroma processing stage may determine a best intra-frame mode for chroma and reconstruct the chroma elements according to the best chroma intra-frame mode. | 03-26-2015 |
20150092843 | DATA STORAGE AND ACCESS IN BLOCK PROCESSING PIPELINES - Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline. | 04-02-2015 |
20150092855 | SKIP THRESHOLDING IN PIPELINED VIDEO ENCODERS - The video encoders described herein may make an initial determination to designate a macroblock as a skip macroblock, but may subsequently reverse that decision based on additional information. For example, an initial skip mode decision may be based on aggregate distortion metrics for the luma component of the macroblock (e.g., SAD, SATD, or SSD), then reversed based on an individual pixel difference metric, an aggregate or individual pixel metric for a chroma component of the macroblock, or on the position of the macroblock within a macroblock row. The final skip mode decision may be based, at least in part, on the maximum difference between any pixel in the macroblock (or in a region of interest within the macroblock) and the corresponding pixel in a reference frame. The initial skip mode decision may be made during an early stage of a pipelined video encoding process and reversed in a later stage. | 04-02-2015 |
20150287351 | SYSTEM AND METHOD OF REDUCING POWER USING A DISPLAY INACTIVE INDICATION - A system includes one or more video processing components and a display processing unit. The display processing unit may include one or more processing pipelines that generate read requests to fetch stored pixel data from a memory for subsequent display on a display unit. The display processing unit may also include a timing control unit that may generate an indication that indicates that the display unit will enter an inactive state. In response to receiving the indication, one or more of the video processing components may enter a low power state. | 10-08-2015 |
Patent application number | Description | Published |
20130143645 | GAMING SYSTEM, GAMING DEVICE, AND METHOD PROVIDING A MULTI-STAGE DICE BONUS GAME - The present disclosure provides gaming systems, devices, and methods providing a multi-stage bonus game. When a first stage triggering event occurs, the gaming system initiates a first bonus game stage. During the first stage, the gaming system enables the player to roll dice, and determine any first stage awards based on the outcome or outcomes of the rolls. When a second stage triggering event occurs, the gaming system initiates a second bonus game stage. During the second stage, the gaming system enables the player to roll dice, and may provide the player with elements, which the player accumulates during the second stage, based on the outcome or outcomes of the rolls. When a second stage termination event occurs, the gaming system determines any second stage awards based on a total quantity of elements accumulated by the player, provides the player with any determined awards, and terminates the bonus game. | 06-06-2013 |
20130337902 | GAMING SYSTEM AND METHOD FOR PROVIDING AN OFFER AND ACCEPTANCE GAME WITH PROGRESSIVE AWARDS - A gaming system for providing a progressive award in association with an offer and acceptance game. | 12-19-2013 |
20130337903 | GAMING SYSTEM AND METHOD FOR PROVIDING AN OFFER AND ACCEPTANCE GAME WITH PROGRESSIVE AWARDS - A gaming system for providing a progressive award in association with an offer and acceptance game. | 12-19-2013 |
20150080119 | GAMING SYSTEM AND METHOD FOR PROVIDING A PLURALITY OF CHANCES OF WINNING A PROGRESSIVE AWARD - The gaming system disclosed herein provides a player one or more chances or opportunities to win the same progressive award. In these embodiments, the gaming system provides the player one or more opportunities to win a progressive award in association with a first game sequence. If the player does not win the progressive award in association with the first game sequence, the gaming system determines whether to provide the player any additional chances or opportunities to win the same progressive award in a second game sequence. | 03-19-2015 |
Patent application number | Description | Published |
20090278964 | METHOD AND APPARATUS FOR CAPTURING HIGH QUALITY LONG EXPOSURE IMAGES WITH A DIGITAL CAMERA - A digital camera captures high quality long exposure images by capturing and summing several images of the same scene. The effective ISO of the camera is reduced by scaling the summed image, thus reducing image noise and improving long exposure quality. | 11-12-2009 |
20150070544 | OVERSAMPLED IMAGE SENSOR WITH CONDITIONAL PIXEL READOUT - In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold. | 03-12-2015 |
20150201142 | Image sensor with threshold-based output encoding - In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold. | 07-16-2015 |
20150229859 | FEEDTHROUGH-COMPENSATED IMAGE SENSOR - A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced. | 08-13-2015 |
20160028974 | LOW-NOISE, HIGH DYNAMIC-RANGE IMAGE SENSOR - An integrated-circuit image sensor generates, as constituent reference voltages of a first voltage ramp, a first sequence of linearly related reference voltages followed by a second sequence of exponentially related reference voltages. The integrated-circuit image sensor compares the constituent reference voltages of the first voltage ramp with a first signal level representative of photocharge integrated within a pixel of the image sensor to identify a first reference voltage of the constituent reference voltages that is exceeded by the first signal level | 01-28-2016 |
20160028985 | THRESHOLD-MONITORING, CONDITIONAL-RESET IMAGE SENSOR - An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data. | 01-28-2016 |
Patent application number | Description | Published |
20110225447 | PREFERRED RESOURCE SELECTOR - A computer implemented method, and computer program product for requesting resources. The computer receives an assignment of an Internet protocol address. The computer compares a computer context of a client computer with an intranet access criterion to form a comparison result. The computer selects at least one preferred uniform resource identifier based on the comparison result, indicating the intranet is accessible. The computer transmits a request to a server using at least one preferred uniform resource identifier using a packet network. | 09-15-2011 |
20150234810 | CONTEXTUAL UPDATING OF EXISTING DOCUMENTS USING NATURAL LANGUAGE PROCESSING - A method, system, and computer program product for contextual updating of existing documents using natural language processing (NLP) are provided in the illustrative embodiments. Information is received about a subject-matter domain. A portion of the existing document is identified, where the portion corresponds to the subject-matter domain. A search query is formed based on the portion, wherein the search query returns a result set, the result set including current information corresponding to the subject-matter domain, the current information being recent as compared to an age of the portion. A natural language (NL) update content is formed by processing the current information through an NLP application. The existing document is updated using the NL update content. | 08-20-2015 |
20150379530 | DRIVING BUSINESS TRAFFIC BY PREDICTIVE ANALYSIS OF SOCIAL MEDIA - According to a business requirement, a set of characteristics of a market is computed. The market comprises a group of potential buyers of a product. In a social medium, the market is identified. A data source operates in the market in the social medium. Data corresponding to the data source in the social medium is analyzed to identify a set of attributes of an event occurring in the social medium. An attribute in the set of attributes is correlated with the product. An information associated with a business application is manipulated such that a search result showing an availability of the product from the business application is promoted in a set of search results produced by a search engine, wherein the set of search results is responsive to a search related to the event in the social medium. | 12-31-2015 |
Patent application number | Description | Published |
20090041029 | METHOD AND SYSTEM FOR MANAGING TRAFFIC IN FIBRE CHANNEL SYSTEMS - Method and system for routing fibre channel frames using a fibre channel switch element is provided. The method includes, inserting a time stamp value in a fibre channel frame that is received at a receive segment of the fibre channel switch element; determining if a timeout occurs after a frame arrives at a receive buffer; and processing the frame if the timeout occurred. The method also includes, determining if a delta time value, which provides an accumulated wait time for a frame, is present in frame data; subtracting the delta time stamp value from a global time stamp value and using the resulting time stamp value to determine frame timeout status in the fibre channel switch element. A timeout checker circuit declares a timeout after comparing a time stamp value that is inserted in a fibre channel frame with a programmed time out value and a global counter value. | 02-12-2009 |
20090296715 | METHOD AND SYSTEM FOR PROGRAMMABLE DATA DEPENDANT NETWORK ROUTING - A method and system for routing fibre channel frames using a fibre channel switch element is provided. The switch element includes, a look up table that is indexed by domain, area, a virtual storage area number and/or AL_PA values of frames entering the fibre channel switch element; and logic for generating a column select signal that is used to select a column from the look up table for frame routing information The switch element also includes logic for validating a frame route by performing word depth match. A register is used to load look up table entries and column entries are selected based on the column select signal. The method includes, indexing a look up table with plural fibre channel frame header values; selecting a table value for routing a fibre channel frame based on a column select signal; and routing the frame if a route is valid. | 12-03-2009 |
20100040074 | MULTI-SPEED CUT THROUGH OPERATION IN FIBRE CHANNEL SWITCHES - A method and system for routing frames based on a port's speed using a fibre channel switch element is provided. The method includes, receiving a portion of a frame in a receive buffer of a port; determining a frame length threshold; and setting up a status bit based on the port's speed, the frame length threshold and an amount of frame received. The status bit is sent to a transmit segment of the fibre channel switch element and the frame length threshold value is inversely proportional to the port's speed. Also, if the receive buffer is almost full when a frame arrives at the receive port, then a cut status is based on a frames end of frame (“EOF”) value. | 02-18-2010 |
20100118880 | METHOD AND SYSTEM FOR NETWORK SWITCH ELEMENT - Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports | 05-13-2010 |
20120069839 | METHOD AND SYSTEM FOR NETWORK SWITCH ELEMENT - Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports. | 03-22-2012 |
Patent application number | Description | Published |
20140139353 | INDICATOR SYSTEM - An indicator system includes a human perceptible indicator, a motion-activated switch, and a controller in electrical communication with the indicator and the motion activated switch. The controller includes a non-transitory memory storing first and second indicator sequences, and a counter counting a number of activations of the motion-activated switch. The controller causes activation of the indicator according to the first indicator sequence when the number of switch activations is less than a first threshold count, and according to the second indicator sequence when the number of switch activations is greater than or equal to the first threshold count, and less than a second threshold count. | 05-22-2014 |
20150033583 | ARTICLES OF FOOTWEAR - An article of footwear includes an outsole and an upper joined with the outsole, the upper having an exterior surface. A panel is joined with the upper, the panel being foldable about an axis between a first position and a second position. A first indicia element is exposed when the panel is in the first position, and a second, different indicia element is exposed when the panel is in the second position. | 02-05-2015 |
20150201866 | ANTHROPOMETRIC MEASURING DEVICE - A measuring device with a measuring tape and a one-piece handle. The handle includes a main body with a fixed reference, an anchor portion with a movable reference and a resilient element. The measuring tape is secured to the anchor portion. The resilient element allows the anchor portion to move with respect to the main body when the measuring tape is under the tension. The resilient element is configured so that the movable reference comes into alignment with the fixed reference when the measuring tape is under proper tension. The fixed reference may also provide a reference from which to take measurements. The resilient element may include a pair of nonlinear segments that straighten under tension. The main body may include a pair of fixed references disposed on opposite sides of the measuring tape, and the anchor portion may include a pair of corresponding movable references. | 07-23-2015 |