Patent application number | Description | Published |
20090041563 | Wafer Transferring Apparatus, Polishing Apparatus, and Wafer Receiving Method - A wafer transferring apparatus includes a top ring ( | 02-12-2009 |
20090067959 | Substrate processing apparatus, substrate transfer apparatus, substrate clamp apparatus, and chemical liquid treatment apparatus - The present invention relates to a substrate processing apparatus which can improve a tact time of substrate processing. A polishing apparatus as the substrate processing apparatus includes plural polishing sections ( | 03-12-2009 |
20090068935 | POLISHING APPARATUS - A polishing apparatus has a top ring configured to hold a semiconductor wafer on a substrate holding surface, and a pushser configured to deliver the semiconductor wafer to the top ring and receive the semiconductor wafer from the top ring. The pushser includes a push stage having a substrate placement surface on which the semiconductor wafer is placed and an air cylinder configured to vertically move the push stage. The pushser also includes a high-pressure fluid port configured to eject a high-pressure fluid toward the semiconductor wafer. | 03-12-2009 |
20090186557 | Method of operating substrate processing apparatus and substrate processing apparatus - A method of operating a substrate processing apparatus, upon the occurrence of a nonfatal failure in the apparatus, makes it possible to continue part of the apparatus operations for substrates to clean and recover a substrate or to easily discharge a substrate from the apparatus, without stopping an entire apparatus, thereby reducing the risk of a substrate becoming unprocessable. The method of operating a substrate processing apparatus having a polishing section, a cleaning section and a transferring mechanism, includes: classifying substrates, upon detection of a malfunction in any of the polishing section, the cleaning section and the transferring mechanism, according to the site of the malfunction and to the positions of the substrates in the substrate processing apparatus; and carrying out an operation for each of the substrates after the detection of the malfunction, the operation varying depending on the classification of the substrate. | 07-23-2009 |
20090247057 | Polishing platen and polishing apparatus - The present invention provides a polishing platen which does not require a large force for removing a polishing pad from an upper surface of the polishing platen and can thus make it relatively easy to remove the polishing pad therefrom. The present invention also provides a polishing apparatus having such polishing platen. The polishing platen ( | 10-01-2009 |
20120193506 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE TRANSFER APPARATUS, SUBSTRATE CLAMP APPARATUS, AND CHEMICAL LIQUID TREATMENT APPARATUS - The present invention relates to a substrate processing apparatus which can improve a tact time of substrate processing. A polishing apparatus as the substrate processing apparatus includes plural polishing sections each for polishing a semiconductor wafer (W), and a swing transporter for transferring the wafer (W). The swing transporter includes a wafer clamp mechanism adapted to clamp the wafer (W), a vertically moving mechanism for vertically moving the wafer clamp mechanism along a frame of a casing of the polishing section, and a swing mechanism for swinging the wafer clamp mechanism about a shaft adjacent to the frame. | 08-02-2012 |
20120231703 | METHOD OF OPERATING SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING APPARATUS - A method of operating a substrate processing apparatus, upon the occurrence of a nonfatal failure in the apparatus, makes it possible to continue part of the apparatus operations for substrates to clean and recover a substrate or to easily discharge a substrate from the apparatus, without stopping an entire apparatus, thereby reducing the risk of a substrate becoming unprocessable. The method of operating a substrate processing apparatus having a polishing section, a cleaning section and a transferring mechanism, includes: classifying substrates, upon detection of a malfunction in any of the polishing section, the cleaning section and the transferring mechanism, according to the site of the malfunction and to the positions of the substrates in the substrate processing apparatus; and carrying out an operation for each of the substrates after the detection of the malfunction, the operation varying depending on the classification of the substrate. | 09-13-2012 |
Patent application number | Description | Published |
20090324060 | LEARNING APPARATUS FOR PATTERN DETECTOR, LEARNING METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A learning apparatus for a pattern detector, which includes a plurality of weak classifiers and detects a specific pattern from input data by classifications of the plurality of weak classifiers, acquires a plurality of data for learning in each of which whether or not the specific pattern is included is given, makes the plurality of weak classifiers learn by making the plurality of weak classifiers detect the specific pattern from the acquired data for learning, selects a plurality of weak classifiers to be composited from the weak classifiers which have learned, and composites the plurality of weak classifiers into one composite weak classifier based on comparison between a performance of the composite weak classifier and performances of the plurality of weak classifiers. | 12-31-2009 |
20100180189 | INFORMATION PROCESSING METHOD AND APPARATUS, PROGRAM, AND STORAGE MEDIUM - An information processing method comprises the steps of: inputting an input information of a multi-dimensional array; calculating an accumulated information value corresponding to a position of each element of the input information; and holding the accumulated information value in a buffer having a size of predetermined bits, wherein in the holding step, when an accumulated information value calculated in the calculating step overflows with respect to the size, a part not more than the predetermined bits of the calculated accumulated information value is held as the accumulated information value. | 07-15-2010 |
20130051662 | LEARNING APPARATUS, METHOD FOR CONTROLLING LEARNING APPARATUS, DETECTION APPARATUS, METHOD FOR CONTROLLING DETECTION APPARATUS AND STORAGE MEDIUM - A learning apparatus comprises a plurality of detection units configured to detect a part or whole of a target object in an image and output a plurality of detection results; an estimation unit configured to estimate a state of the target object based on at least one of the plurality of detection results; a classification unit configured to classify the image into a plurality of groups based on the state of the target object; and a weight calculation unit configured to calculate weight information on each of the plurality of detection units for each of the groups based on the detection results. | 02-28-2013 |
20130259307 | OBJECT DETECTION APPARATUS AND METHOD THEREFOR - An object detection apparatus includes a first detection unit configured to detect a first portion of an object from an input image, a second detection unit configured to detect a second portion different from the first portion of the object, a first estimation unit configured to estimate a third portion of the object based on the first portion, a second estimation unit configured to estimate a third portion of the object based on the second portion, a determination unit configured to determine whether the third portions, which have been respectively estimated by the first and second estimation units, match each other, and an output unit configured to output, if the third portions match each other, a detection result of the object based on at least one of a detection result of the first or second detection unit and an estimation result of the first or second estimation unit. | 10-03-2013 |
20130259310 | OBJECT DETECTION METHOD, OBJECT DETECTION APPARATUS, AND PROGRAM - An object detection method includes an image acquisition step of acquiring an image including a target object, a layer image generation step of generating a plurality of layer images by one or both of enlarging and reducing the image at a plurality of different scales, a first detection step of detecting a region of at least a part of the target object as a first detected region from each of the layer images, a selection step of selecting at least one of the layer images based on the detected first detected region and learning data learned in advance, a second detection step of detecting a region of at least a part of the target object in the selected layer image as a second detected region, and an integration step of integrating a detection result detected in the first detection step and a detection result detected in the second detection step. | 10-03-2013 |
Patent application number | Description | Published |
20120241917 | SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode. | 09-27-2012 |
20130082382 | SEMICONDUCTOR DEVICE - First and second sub-bumps are provided on both surfaces of each substrate along with a usual bump structure (first and second main bumps), and at least one of the first and second sub-bumps is made greater in height than the first and second main bumps, so that the sub-bumps come into contact with one another earlier than the main bumps at the time of joining semiconductor chips, thereby securing margins of joint among the main bumps and suppressing the thin-filming of a layer, such as a solder layer, to be fluidized by heating. | 04-04-2013 |
20130134548 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality. | 05-30-2013 |
20130313689 | SEMICONDUCTOR DEVICE - In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material. | 11-28-2013 |
20140183704 | SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a semiconductor substrate having first and second surfaces and a peripheral edge, the first and second surfaces being opposite to each other, includes forming an inter-layer insulator having a guard ring on the first surface, adjacent to the peripheral edge, forming a first groove on the second surface and adjacent to the peripheral edge, and forming a through electrode that penetrates the second surface to the inter-layer insulator near the first groove and on an opposite side of the groove with respect to the peripheral edge. | 07-03-2014 |
Patent application number | Description | Published |
20090033958 | Image Processing Apparatus for Displaying a Control Method Corresponding to a Control Code Provided in a Document - An image processing apparatus detects a control code provided to a document in order to prevent image data, which is created by reading the document, from being leaked in accordance with the detected control code. A control table storage part stores the control code by relating to a control method to prevent leaking. A control method display section displays the control method, which is retrieved from the control table storage part, on a display part based on the control code. | 02-05-2009 |
20110238957 | SOFTWARE CONVERSION PROGRAM PRODUCT AND COMPUTER SYSTEM - According to one embodiment, a software conversion program product having a computer readable medium including programmed instructions, wherein the instructions, when executed by a computer system including a host processor and one or more accelerator processors, causes the computer system to perform: analyzing input software and obtaining a compute intensity calculated by dividing the number of arithmetic processing times in a loop by the size of data accessed in the loop and a data reference area size that is a total size of areas where data is referred to; determining a processor that executes loops on the basis of obtained values and a preliminarily prepared win-loss table in which wins and losses of execution times between the host processor and the accelerator processor are defined; and converting the input software so that the determined processor executes the loops. | 09-29-2011 |
20120246387 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD - According to an embodiment, a semiconductor memory device includes a nonvolatile memory; an input/output control unit to control input/output of data to/from the nonvolatile memory; an address translation table that associates first address information specifying a logical recording position of user data stored in the nonvolatile memory with second address information indicating a physical recording position in the nonvolatile memory; a translating unit to translate the first address information to the second address information according to the table; and a generating unit to generate redundant data for checking whether there is error in the user data and the first address information used as one data piece. The input/output control unit records, as data set, the user data, the first address information, and the redundant data, which are used as one data set, in the physical recording position in the nonvolatile memory indicated by the second address information. | 09-27-2012 |
20130080863 | STORAGE DEVICE - According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits. | 03-28-2013 |
20130104002 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory. | 04-25-2013 |
20130246887 | MEMORY CONTROLLER - According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i−1)-th parities. | 09-19-2013 |
20130305120 | MEMORY CONTROLLER, STORAGE DEVICE AND ERROR CORRECTION METHOD - According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities. | 11-14-2013 |
20140032992 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit. | 01-30-2014 |
20140108887 | STORAGE DEVICE - According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits. | 04-17-2014 |
20140245099 | MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability. | 08-28-2014 |
20140245101 | SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor memory includes a memory cell unit, an encoding circuit that generates a first parity and a second parity for data, and a decoding circuit that performs error correction by using the data, the first parity, and the second parity, the first parity is generated by using a first generation polynomial for the data, the second parity is generated by using a second generation polynomial for the input data and the first parity, the second generation polynomial is selected based on the first generation polynomial, the data and the first parity is output to the outside, and the second parity is not output to the outside. | 08-28-2014 |
20140245103 | MEMORY CONTROLLER, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory. | 08-28-2014 |
Patent application number | Description | Published |
20130098063 | COOLNG STRUCTURE FOR RECOVERY-TYPE AIR-COOLED GAS TURBINE COMBUSTOR - In a cooling structure for a recovery-type air-cooled gas turbine combustor having a recovery-type air-cooling structure that bleeds, upstream of the combustor, and pressurizes compressed air supplied from a compressor, that uses the bled and pressurized air to cool a wall, and that recovers and reuses the bled and pressurized air as combustion air for burning fuel in the combustor together with a main flow of the compressed air, wall cooling in which cooling air is supplied to cooling air passages formed in the wall of the combustor to perform cooling involves a downstream wall region, closer to a turbine, that is cooled using the bled and pressurized air as the cooling air and an upstream wall region, closer to a burner, that is cooled using, as the cooling air, bled compressed air bled from a main flow of the compressed air through a housing inner space. | 04-25-2013 |
20140216055 | GAS TURBINE - In this gas turbine, at a downstream portion of a transition piece of a combustor, inner surfaces of a pair of lateral walls facing each other in a circumferential direction of a turbine rotor form inclination surfaces that incline down to a downstream end of the transition piece in a direction approaching the transition piece of another adjacent combustor that gradually draws closer as it goes to the downstream side of the transition piece in an axis direction. | 08-07-2014 |
20150197833 | Ni-BASED SINGLE CRYSTAL SUPERALLOY - Provided is a Ni-based single crystal superalloy containing
| 07-16-2015 |
Patent application number | Description | Published |
20100172366 | SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD - A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information. | 07-08-2010 |
20100183015 | SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD - A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set. | 07-22-2010 |
20100321051 | SEMICONDUCTOR INTEGRATED CIRCUIT, DEBUG/TRACE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT OPERATION OBSERVING METHOD - A main functional structure executes continuous predetermined operations to continuously generate events associated with the operations. A debug/trace circuit compares an event occurring at the main functional structure with detection condition indicating information of one entry in a control information list, and executes the operation designated by operation indicating information paired with the detection condition indicating information in accordance with the result of the comparison. The debug/trace circuit continuously performs this in accordance with the control information list to identify the event. | 12-23-2010 |
20100332709 | PERFORMANCE OPTIMIZATION SYSTEM, METHOD AND PROGRAM - Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access. | 12-30-2010 |
20110026405 | ROUTER, INFORMATION PROCESSING DEVICE HAVING SAID ROUTER, AND PACKET ROUTING METHOD - A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing. | 02-03-2011 |
Patent application number | Description | Published |
20100088318 | INFORMATION SEARCH SYSTEM, METHOD, AND PROGRAM - Disclosed is a system in which an index registration unit registers an index, which will be used for search processing, as a partitioned index which is partitioned on a time series basis, and a search means reads indexes older than a specified point in time, which is used as a search base point, to perform search processing, thereby searching for information based on a point in time in the past. | 04-08-2010 |
20100250634 | FILE SERVER SYSTEM AND FILE MANAGEMENT METHOD - A management policy is given to a predetermined storage area by an administrator or a predetermined end user of end users as users of a plurality of client terminals. At this time, a file server generates a setting file in which the management policy is written, to set in a directory corresponding to the predetermined storage area. A write instruction (change data) is given by the administrator or the predetermined end user. The file server changes the management policy based on the change data. | 09-30-2010 |
20110231508 | CLUSTER CONTROL SYSTEM, CLUSTER CONTROL METHOD, AND PROGRAM - A slave computer out of a plurality of slave computers that are connected to a plurality of clients through a front network and provide the front network with a single IP address that is a same IP address comprises: a responsible client table that indicates a client for which each of the plurality of slave computers is responsible; and an ARP processing unit that refers to the responsible client table when an ARP request for the single IP address has been received from one of the plurality of clients and sends an ARP response when a client that has sent the ARP request is present in the responsible client table, and otherwise does not send the ARP response, wherein a client in the responsible client table is added, changed, or deleted by a master computer connected through a back-end network. | 09-22-2011 |
20110320750 | INFORMATION PROCESSING SYSTEM AND METHOD - The present invention provides information storage system and method capable of changing an information storage format to a format suitable for the data utilization form. There are provided a means that records history information of information processing on data, a plurality of information storing means that store information in mutually different information storage formats, and an information storage format control means that changes an information storage format of data, on the basis of a history of processing relating to the data. | 12-29-2011 |
20120036317 | STORAGE SYSTEM AND STORAGE ACCESS METHOD AND PROGRAM - A system has a data structure in which a value can be obtained from a key. In a write access, a first pair and a second pair are stored respectively in a volatile storage device. The first pair is saved in a nonvolatile storage device before returning a response, and the second pair is saved in the first storage device at any time with the second pair saved in the volatile storage device. In a read access in which a value is obtained from a key, it is determined that data is not stored normally if the second pair is not found in processing in which after obtaining the hash value of the value from the first pair, the second pair is read. | 02-09-2012 |
20130046845 | STORAGE SYSTEM, CONTROL METHOD FOR STORAGE SYSTEM, AND COMPUTER PROGRAM - A control method for a storage system, whereby a plurality of storage nodes included in the storage system are grouped into a first group composed of storage nodes with a network distance in the storage system within a predetermined distance range, and second groups composed of storage nodes that share position information for the storage nodes that store data. A logical spatial identifier that identifies the second groups is allocated for each of the second groups, to calculate a logical spatial position using a data identifier as an input value for a distributed function, and store data corresponding to the data identifier in the storage node that belongs the second group to which the identifier corresponding to the calculated position is allocated. | 02-21-2013 |
20130346365 | DISTRIBUTED STORAGE SYSTEM AND DISTRIBUTED STORAGE METHOD - A distributed storage system of the present invention includes a plurality of data nodes coupled via a network and respectively including data storage units. At least two of the data nodes hold in the respective data storage units thereof replicas of a plurality of types of data structures that are logically identical but are physically different between the data nodes. | 12-26-2013 |
20140129863 | SERVER, POWER MANAGEMENT SYSTEM, POWER MANAGEMENT METHOD, AND PROGRAM - To increase the reliability of power supply control of a server group and reduce the power consumption of the server group. A server includes a power supply stop control unit which stops a power supply of a predetermined processing unit upon receiving a power supply stop instruction signal instructing to stop the power supply, a power supply start-up control unit which intermittently starts up the power supply of the predetermined processing unit when the power supply stop control unit stops the power supply of the predetermined processing unit, a power supply start-up determination unit which determines whether a processing load of other servers which are executing their processes among a plurality of other servers is higher than an upper limit load determined in advance as a load required to be processed by servers the number of which is greater than or equal to the number of the other servers which are executing their processes when the power supply start-up control unit starts up the power supply of the predetermined processing unit, and a process control unit which controls process execution for the predetermined processing unit when the processing load of the other servers which are executing their processes is determined to be higher than the upper limit load. | 05-08-2014 |
20140173035 | DISTRIBUTED STORAGE SYSTEM AND METHOD - Provided a plurality of data nodes connected in a network, each including a data storage unit. The data node of data replication destination temporarily stores the-data to be updated in an intermediate data structure, and converts asynchronously with respect to the update request to a target data structure to store the converted data in the data storage unit. Based on access history information stored in an access history recording unit, trigger information, concerning timing for execution of conversion to the target data structure performed asynchronously by the data node is changed. | 06-19-2014 |
20150163298 | COMPUTER NETWORK SYSTEM AND METHOD OF DETERMINING NECESSITY OF TRANSFERRING LOAD IN COMPUTER NETWORK SYSTEM - An evaluation value D | 06-11-2015 |