Patent application number | Description | Published |
20080238248 | MULTI-LAYER PIEZOELECTRIC ACTUATORS WITH CONDUCTIVE POLYMER ELECTRODES - A multi-layer piezoelectric actuator with conductive polymer electrodes is described. The piezoelectric actuator comprises a stack of alternating conductive electrode layers and piezoelectric layers. The conductive electrode layers are comprised of a polymeric electrically conductive material. A device for cooling by forced-air convection may comprise the piezoelectric actuator, a fan blade and an alternating current supply. The piezoelectric actuator coupled with the fan blade and the alternating current supply, which is provided for vibrating the fan blade. A method of cooling by forced-air convection comprises supplying an alternating current to the piezoelectric actuator, wherein the alternating current has a frequency and causes the fan blade to vibrate with the same frequency. | 10-02-2008 |
20080296754 | APPARATUS TO MINIMIZE THERMAL IMPEDANCE USING COPPER ON DIE BACKSIDE - A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress. | 12-04-2008 |
20090079063 | MICROELECTRONIC PACKAGE AND METHOD OF COOLING AN INTERCONNECT FEATURE IN SAME - A microelectronic package comprises a substrate ( | 03-26-2009 |
20090084931 | ENABLING BARE DIE LIQUID COOLING FOR THE BARE DIE AND HOT SPOTS - A liquid cooling device for a die including a support block supporting a plurality of substantially vertical channels transporting fluid to and from a bare die surface for heat removal. The device is mounted on top of a bare die using a frame or spring. In another embodiment, the device allows thermoelectric cooling of a dedicated fluid line. | 04-02-2009 |
20090085438 | PIEZOELECTRIC FAN, COOLING DEVICE CONTAINING SAME, AND METHOD OF COOLING A MICROELECTRONIC DEVICE USING SAME - A piezoelectric fan includes a piezoelectric actuator patch ( | 04-02-2009 |
20090096087 | MICROELECTRONIC ASSEMBLY AND METHOD OF PREPARING SAME - A microelectronic assembly includes a die ( | 04-16-2009 |
20090129022 | Micro-chimney and thermosiphon die-level cooling - A method and arrangement for dissipating heat from a localized area within a semiconductor die is presented. A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area. As such, thermal stress on the die is reduced, and total heat from the die is more readily dissipated. | 05-21-2009 |
20090174999 | PIEZOELECTRIC AIR JET AUGMENTED COOLING FOR ELECTRONIC DEVICES - In some embodiments, piezoelectric air jet augmented cooling for electronic devices is presented. In this regard, an apparatus is introduced having a plurality of more than about one hundred lead-free piezoelectric layers and electrodes stacked on top of each other and formed around a central opening, and a diaphragm coupled to the piezoelectric layers and substantially covering the central opening to vibrate and blow air when an operating voltage is applied to the electrodes. Other embodiments are also disclosed and claimed. | 07-09-2009 |
20090218681 | Carbon nanotube and metal thermal interface material, process of making same, packages containing same, and systems containing same - A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used. | 09-03-2009 |
20090289353 | COVERED DEVICES IN A SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface. | 11-26-2009 |
20110103438 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 05-05-2011 |
20110135015 | COOLING DEVICES IN SEMICONDUCTOR PACKAGES - An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface. | 06-09-2011 |
20110214285 | CARBON NANOTUBE AND METAL THERMAL INTERFACE MATERIAL, PROCESS OF MAKING SAME, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME - A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used. | 09-08-2011 |
20110297362 | MICRO-CHIMNEY AND THERMOSIPHON DIE-LEVEL COOLING - A method and arrangement for dissipating heat from a localized area within a semiconductor die is presented. A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area. As such, thermal stress on the die is reduced, and total heat from the die is more readily dissipated. | 12-08-2011 |
20120021566 | CARBON NANOTUBE MICRO-CHIMNEY AND THERMO SIPHON DIE-LEVEL COOLING - A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die. | 01-26-2012 |
20120289002 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 11-15-2012 |
20130122656 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 05-16-2013 |