Lee, Icheon-Si
Byoung-Kwang Lee, Icheon-Si KR
Patent application number | Description | Published |
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20120040241 | COPPER FOIL FOR CURRENT COLLECTOR OF LITHIUM SECONDARY BATTERY - A copper foil for a current collector of a lithium secondary battery is configured such that a nodule cluster having an inter-nodule aspect ratio of 0.001 to 2 is provided at a matte side formed on one surface of the copper foil, in aspect of a crystal structure, a ratio of a texture coefficient of a (200) surface to a sum of texture coefficients of a (111) surface and the (200) surface is 30 to 80%, the copper foil has a water contact angle of 90° or below, and impurity spots existing at the surface of the copper foil have a maximum diameter of 100 μm or less, and a minimal spacing distance between the impurity spots is 1 cm or more. | 02-16-2012 |
Byung-Duk Lee, Icheon-Si KR
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20090243033 | FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction. | 10-01-2009 |
20100044797 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased. | 02-25-2010 |
20120007184 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased. | 01-12-2012 |
20120088361 | FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction. | 04-12-2012 |
Byung In Lee, Icheon-Si KR
Cho Yeon Lee, Icheon-Si KR
Patent application number | Description | Published |
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20100282605 | Apparatus for Detecting Nano Particle Having Nano-Gap Electrode - The present invention relates to a nanoparticle sensor which is capable to identify an existence/nonexistence, a concentration, a size distribution and a component of the nanoparticles using an electrode pair having a separated distance of a nano-gap, in which the nanoparticle sensor includes a unit element configured with a plurality of unit electrodes electrically operated independently from each other and detects the nanoparticles based on the number of the unit electrodes electrically changed due to the nanoparticles captured into the nano-gap. The nanoparticle sensor of the present invention can detect the component, the size, the size distribution and the concentration of the nanoparticles by single measurement, have high reliability and regeneration while reducing a detection time by statistical method via a plurality of electrode pairs having the nano-gap, and detect even very low concentration of nanoparticles. | 11-11-2010 |
Chun-Hee Lee, Icheon-Si KR
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20090159964 | VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration. | 06-25-2009 |
20090242945 | Semiconductor device and method of fabricating the same - In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier. | 10-01-2009 |
20090253236 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier. | 10-08-2009 |
20090253254 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes. | 10-08-2009 |
20110169074 | VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration. | 07-14-2011 |
Dong Geun Lee, Icheon-Si KR
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20100081248 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises forming a first plate electrode that defines a storage node region over a semiconductor substrate, forming a first dielectric film at sidewalls of the storage node region, forming a storage node over the storage node region, and forming a second dielectric film and a second plate electrode over the resulting structure, thereby preventing collapse of the storage node and also preventing generation of defects by electric short between capacitors. | 04-01-2010 |
Don Ik Lee, Icheon-Si KR
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20090072198 | SULFUR-CONTAINING DISPERSANT AND SULFIDE PHOSPHOR PASTE COMPOSITION COMPRISING THE SAME - A sulfide phosphor paste composition comprising a sulfur-containing dispersant, and a fluorescent film prepared therefrom, are provided. The sulfur-containing dispersant has a dual head structure containing both a carboxyl group and a thiol group or a structure containing a thiol or thiophene group as a head group. An oligomeric sulfur-containing dispersant is also provided. Adsorption of the dispersant on the surface of the sulfide phosphor prevents aggregation of the phosphor particles, and thereby improves the dispersibility of the sulfide phosphor paste composition, the homogeneity of the phosphor in the paste composition, and the density of a film produced from the paste composition. Fluorescent films and display devices produced from the phosphor paste composition exhibit improved luminescent properties and excellent processability. | 03-19-2009 |
Eun Ryeong Lee, Icheon-Si KR
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20090302901 | Command decoder and command signal generating circuit - A command decoder generates a command signal based on first to fourth control signals in response to a second chip select signal generated by delaying a first chip select signal for a predetermined interval. | 12-10-2009 |
20110050289 | INPUT BUFFER - An input buffer includes a driving signal generation unit, a comparison signal generation unit, and a driving unit. The driving signal generation unit is configured to generate first and second driving signals which are selectively enabled in response to a control signal generated depending on a level of an input signal. The comparison signal generation unit is configured to compare the level of the input signal with the level of a reference voltage and generate a comparison signal. The driving unit is configured to buffer the comparison signal and drive an output signal with a drivability determined by the first and second driving signals. | 03-03-2011 |
Ga Hee Lee, Icheon-Si KR
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20100227469 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region. In addition, damage to a tunnel oxide film, a semiconductor substrate or a floating gate while an isolation film is etched at a predetermined depth in order to control the EFH can be prevented by controlling the EFH in such a manner than conductive layer spacers are formed on sidewalls of the floating gate and the isolation film is further etched. | 09-09-2010 |
Geun Il Lee, Icheon-Si KR
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20120081145 | IMPEDANCE CONTROL SIGNAL GENERATION CIRCUIT AND IMPEDANCE CONTROL METHOD OF SEMICONDUCTOR CIRCUIT - An impedance control signal generation circuit includes an impedance control signal generation unit configured to generate an impedance control signal in response to a command, a storage unit configured to latch and output the impedance control signal in response to an update pulse signal, a control unit configured to determine whether the impedance control signal is within a predetermined range and generate an update enable signal according to a determination result, and a prohibition unit configured to control input of the update pulse signal to the storage unit in response to the update enable signal. | 04-05-2012 |
20140176209 | CLOCK GENERATION CIRCUIT AND CLOCK GENERATION SYSTEM USING THE SAME - A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes. | 06-26-2014 |
Go Hyun Lee, Icheon-Si KR
Patent application number | Description | Published |
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20120307544 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other. | 12-06-2012 |
20130135930 | NONVOLATILE MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory apparatus includes a a memory cell array, a page buffer unit connected to bit lines of the memory cell array through a high voltage switching unit, a first interconnection configured to connect a high voltage switch of the high voltage switching unit, connected to an even bit line, to the page buffer unit, and formed at a first layer, and a second interconnection configured to connect a high voltage switch of the high voltage switching unit, connected to an odd bit line, to the page buffer unit, and formed at a second layer different from the first layer. | 05-30-2013 |
Hee Bum Lee, Icheon-Si KR
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20120001055 | RAMP SIGNAL GENERATOR AND IMAGE SENSOR - Disclosed are a ramp signal generator and an image sensor. The ramp signal generator includes: a comparator comparing a first bias voltage input to a first input terminal and a second bias voltage input to a second input terminal and outputting a ramp signal from an output terminal; a ramp signal adjustment unit including a plurality of switched capacitors made up of switches and capacitors connected in series, and connected in parallel between a first input terminal of the comparator and an output terminal of the comparator; and a controller switching the switches of the plurality of switched capacitors to adjust the ramp signal output from the comparator such that the ramp signal becomes nonlinear over time. | 01-05-2012 |
20120037791 | IMAGE SENSOR - An image sensor includes a band gap reference unit configured to provide a reference voltage having a predetermined voltage level, a storage unit configured to store the reference voltage, a switch configured to selectively connect the storage unit to the band gap reference unit, and a ramp signal generation unit configured to receive an input voltage corresponding to the reference voltage stored in the storage unit and generate a ramp signal. | 02-16-2012 |
Hyung Dong Lee, Icheon-Si KR
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20120140584 | SEMICONDUCTOR SYSTEM, SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR INPUT/OUTPUT OF DATA USING THE SAME - A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller. | 06-07-2012 |
20120273961 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a plurality of semiconductor chips which are stacked; and an auxiliary semiconductor chip configured to recover and transmit signals of the plurality of semiconductor chips through a plurality of through vias which extend vertically, at a predetermined time interval. | 11-01-2012 |
20130031439 | SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM HAVING THE SAME - A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines. | 01-31-2013 |
20130092936 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal. | 04-18-2013 |
20130094316 | MEMORY SYSTEM - A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other. | 04-18-2013 |
20140006863 | TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME | 01-02-2014 |
20140006901 | MEMORY SYSTEM | 01-02-2014 |
20140006902 | SEMICONDUCTOR DEVICE INCLUDING ECC CIRCUIT | 01-02-2014 |
20140177358 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die. | 06-26-2014 |
20140181439 | Memory system - A memory system includes a processor, one or more volatile memory dies stacked with the processor and one or more nonvolatile memory dies stacked with the processor and the volatile memory dies. The processor transfers data stored in the volatile memory die to the nonvolatile memory die in response to a backup signal, and transfers the data stored in the nonvolatile memory die to the volatile memory die in response to a recovery signal. | 06-26-2014 |
20140181449 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes a memory unit and a memory controller. The memory unit includes a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line. The memory controller is configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value. | 06-26-2014 |
Hyung-Min Lee, Icheon-Si KR
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20130083596 | NONVOLATILE MEMORY DEVICE - Embodiments of present invention relate to a nonvolatile memory device that includes a first page buffer controlling any one of a first even bit line and a first odd bit line; a second page buffer controlling any one of a second even bit line and a second odd bit line; wherein the second page buffer operates the second odd bit line according to program when the first page buffer operates the first even bit line according to program, and the second page buffer operates the second even bit line according to program when the first page buffer operates the first odd bit line according to program. | 04-04-2013 |
20140063944 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell block configured to have memory cell groups, a peripheral circuit configured to read data by supplying a read voltage to memory cells in the memory cell groups, a fail detection circuit configured to perform a pass/fail check operation of memory cell groups according to the data read by the peripheral circuit and a control circuit configured to control the peripheral circuit and the fail detection circuit to perform again the read operation about the memory cell groups using a compensation read voltage different from the read voltage in the event that it is determined that one or more memory cell group is failed according to the pass/fail check operation. | 03-06-2014 |
Hyun Joo Lee, Icheon-Si KR
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20120106242 | MEMORY APPARATUS HAVING STORAGE MEDIUM DEPENDENT ON TEMPERATURE AND METHOD FOR DRIVING THE SAME - A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having a compensated level and width to a memory cell in response to the pulse control signal. | 05-03-2012 |
20120155204 | SEMICONDUCTOR MEMORY APPARATUS HAVING A PRE-DISCHARGING FUNCTION, SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal. | 06-21-2012 |
20140063926 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started. | 03-06-2014 |
In No Lee, Icheon-Si KR
Patent application number | Description | Published |
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20080220578 | METHOD OF FABRICATING A NON-VOLATILE MEMORY DEVICE - In a method of fabricating a non-volatile memory device, a semiconductor substrate includes an isolation layer formed in an isolation region, a tunnel insulating layer and a first conductive layer for a floating gate formed in an active region, and a dielectric layer, a second conductive layer for a control gate, and a gate hard mask formed over the first conductive layer including the isolation layer. The second conductive layer is patterned using the gate hard mask as an etch mask. The dielectric layer is patterned so that the first conductive layer, which is exposed as the dielectric layer is etched, is also etched. The first conductive layer is patterned along a pattern of the gate hard mask. Accordingly, at the time of gate patterning, micro bridges between the floating gates can be prevented and a 2-bit failure between neighboring cells is less likely. | 09-11-2008 |
20080242074 | Method of Forming Gate Pattern of Flash Memory Device - A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved. | 10-02-2008 |
20090104763 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal silicide layer, including the surface roughness, is polished before or during a gate etch process in order to diminish the surface roughnesses. Thus, although surface roughnesses exist in the metal silicide layer, a SAC nitride layer formed over a gate can be prevented from being lost in a subsequent polishing process of a pre-metal dielectric layer, which is performed in order to form a contact plug. Accordingly, a hump phenomenon of a transistor can be improved. | 04-23-2009 |
20090191697 | METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE - In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern. | 07-30-2009 |
In Pyo Lee, Icheon-Si KR
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20120314519 | WORD LINE DRIVING SIGNAL CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND WORD LINE DRIVING METHOD - A word line driving signal control circuit of a semiconductor memory apparatus provided with a sub-redundancy cell array includes a fuse unit configured to generate a redundancy enable signal in response to a bank active signal and an address signal, and a repair determination unit configured to activate one of a normal word line driving signal, a redundancy word line driving signal, and a sub-redundancy word line driving signal in response to the bank active signal and the redundancy enable signal. | 12-13-2012 |
Jae Soo Lee, Icheon-Si KR
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20090309198 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads. | 12-17-2009 |
20110108970 | SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF - A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed. | 05-12-2011 |
Jeong Hun Lee, Icheon-Si KR
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20120044780 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data. | 02-23-2012 |
20120081100 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system. | 04-05-2012 |
Jeon Kyu Lee, Icheon-Si KR
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20100164114 | Wire Structure of Semiconductor Device and Method for Manufacturing the Same - Disclosed herein are a wire structure of a semiconductor device and a method of making the same. The method includes obtaining a layout of an active region in a semiconductor substrate, the layout extending in a direction diagonally intersecting a layout of a bit line. The method also includes forming an isolation layer that delimits the active region, | 07-01-2010 |
20110004854 | Method for Fabricating Assist Features in a Photomask - Disclosed is a method of fabricating an assist feature in a photomask, which includes: fabricating a design layout in which main patterns are arranged; setting a critical dimension (a) of assist features to be formed and a spacing (b) between the main pattern and the assist feature; setting a first expanded region extending from the main pattern by (a+b); setting a second expanded region extending from the main pattern by (b); and setting the assist features by removing the second expanded region from the first expanded region. | 01-06-2011 |
20140205954 | METHOD FOR FORMING PATTERNS OF SEMICONDUCTOR DEVICE BY USING MIXED ASSIST FEATURE SYSTEM - A method for forming patterns of a semiconductor device includes providing a photomask that includes an array of contact holes in an active region, a plurality of first dummy contact holes for restricting pattern distortion of the contact holes in an area outside of the array of the contact holes, a plurality of first assist features for restricting pattern distortion of the first dummy contact holes disposed inside a corresponding one of the first dummy contact holes, and an array of second assist features for additionally restricting pattern distortion of the first dummy contact holes. The array of second assist features is disposed outside of the first dummy contact holes. The method also includes forming an array of contact holes and first dummy contact holes on a wafer by using the photomask as an exposure mask. | 07-24-2014 |
Jihang Lee, Icheon-Si KR
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20100323063 | PROCESS FOR THE PREPARATION OF ISOMALTOOLIGOSACCHARIDE-HYDROGENATED - Processes for preparing isomaltooligosaccharide-hydrogenated (‘IMO-H’) syrup and IMO-H syrup made by the processes. In the process isomaltooligosaccharide (‘IMO’) is generally obtained by liquefying a raw material and then conducting one or more saccharification steps followed by additional processing steps, including filtration, decolorization, ion-exchange and evaporation. The IMO is then hydrogenated and the IMO-H is refined. | 12-23-2010 |
Jin Hui Lee, Icheon-Si KR
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20110304038 | SEMICONDUCTOR CHIP DESIGNED TO DISSIPATE HEAT EFFECTIVELY, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND STACK PACKAGE USING THE SAME - A semiconductor chip includes a semiconductor chip body having a top surface, a bottom surface, and side surfaces. The bottom surface may have a groove pattern defined by removing a partial thickness of the semiconductor chip body to extend from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body. Through electrodes may be formed to extend from the top surface of the semiconductor chip body and pass through the groove pattern defined on the bottom surface. A heat dissipation pattern may fill in the groove pattern defined on the bottom surface and may be connected with the through electrodes. | 12-15-2011 |
20120007213 | SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME - A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate. | 01-12-2012 |
Jin Hwan Lee, Icheon-Si KR
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20080233727 | Method of manufacturing semiconductor device - Disclosed is a method for manufacturing a semiconductor device. More specifically, in the invention, a gate pattern is formed and then an interlayer insulating pattern burying the space between the gate patterns is formed to ensure the region into which a landing plug contact hole has to be opened, thereby avoiding a problem in that the landing plug contact hole is not opened when forming the landing plug contact hole in a subsequent process. As a result, a failure that may occur in a subsequent test process can be avoided and further a current drivability of a gate, a tWR feature and a timing margin are ensured and thereby improve the device features. | 09-25-2008 |
20120091557 | ANTI-FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An anti-fuse of a semiconductor device and a method for manufacturing the same are disclosed. In order to achieve stable operation of the anti-fuse, a gate rupture prevention film is formed between a gate pattern and a source/drain junction region and a gate oxide film is formed at both ends of a lower edge of the gate pattern. Therefore, when applying a voltage, the overlapped gate oxide film is ruptured so that a current level is stabilized and the anti-fuse is stably operated. | 04-19-2012 |
Jin-Ku Lee, Icheon-Si KR
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20100084720 | Gate in semiconductor device and method of fabricating the same - A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate. | 04-08-2010 |
Joo-Hyun Lee, Icheon-Si KR
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20090001433 | Image Sensor and Method for Manufacturing the Same - Provided are an image sensor and a method of fabricating the same. The image sensor includes a substrate having an active area and a device isolation area; a well implantation area in the active area; a threshold voltage implantation area in the well implantation area; and a transistor gate on the threshold voltage implantation area, wherein the threshold voltage implantation has a width greater than a width of the transistor gate. | 01-01-2009 |
20090029519 | METHOD OF MANUFACTURING MIM CAPACITOR - Embodiments relate to a method of manufacturing an MIM capacitor, which is capable of obtaining a desired capacitance by controlling a k value of insulator thin film formed between bottom and top electrodes by adjusting a plasma doping condition. An MIM capacitor may be manufactured by forming a bottom electrode over a semiconductor substrate. An insulator thin film may be formed over the bottom electrode. A k value of the insulator thin film may be adjusted to an optional range by performing a plasma nitridation doping process on the insulator thin film. A top electrode may be formed over the insulator thin film. | 01-29-2009 |
Jung Woong Lee, Icheon-Si KR
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20090127714 | CONTACT PLUG OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The present invention relates to a contact plug of a semiconductor device and a method of forming the same. The method includes forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a first conductive layer over the insulating layer including the contact holes, etching the first conductive layer so that the first conductive layer remains at lower portions of the contact holes, wherein the insulating layer is also etched in order to widen upper widths of the contact holes, and forming a second conductive layer over the first conductive layer of the contact holes, thus forming the contact plugs. | 05-21-2009 |
Jun Woo Lee, Icheon-Si KR
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20110267112 | OUTPUT DRIVER AND SEMICONDUCTOR APPARATUS HAVING THE SAME - An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal. | 11-03-2011 |
20120195153 | SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other. | 08-02-2012 |
Kang-Jae Lee, Icheon-Si KR
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20110147823 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench. | 06-23-2011 |
Kang Seol Lee, Icheon-Si KR
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20120188836 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period. | 07-26-2012 |
20120218843 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor device includes a control signal generation unit configured to activate, latch, and output a toggle control signal when a delayed refresh signal is inputted at the initial stage, deactivate and output the toggle control signal after additionally counting a redundancy word line address when counting of the main word line address with respect to the mat address is completed, and then activate, latch, and output the toggle control signal when the delayed refresh signal is inputted. | 08-30-2012 |
Kang Won Lee, Icheon-Si KR
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20130037939 | SEMICONDUCTOR PACKAGE AND STACK-TYPE SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a semiconductor chip having a first surface, a second surface which faces away from the first surface, and through holes which pass through the first surface and the second surface; a dielectric layer formed on one or more of the first surface and the second surface and formed with grooves around the through holes on a fourth surface of the dielectric layer facing away from a third surface of the dielectric layer which is attached to the semiconductor chip; through-silicon vias filling the through holes; and bumps formed on the through-silicon vias and on portions of the dielectric layer around the through-silicon vias and filling the grooves. | 02-14-2013 |
20130240885 | SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate including a substrate body divided into device regions and a peripheral region generally outside the device regions, and having one surface generally facing away from an other surface, and trenches which are defined generally in the device regions substantially on the one surface; and an active layer formed substantially in the trenches and made of polysilicon; semiconductor devices formed substantially over the active layer; and through electrodes substantially passing through the peripheral region of the substrate body. | 09-19-2013 |
20130241078 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate having one surface, an other surface which faces away from the one surface, and through holes which pass through the one surface and the other surface; through electrodes filled in the through holes; and a gettering layer formed of polysilicon interposed between the through electrodes and inner surfaces of the semiconductor substrate whose form is defined by the through holes. | 09-19-2013 |
20130264689 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR CHIP HAVING THE SAME, AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor substrate includes a substrate body divided into device regions and a peripheral region outside the device region, and having one surface, another surface substantially facing away from the one surface, trenches defined in the device regions under the one surface and inner surfaces which are formed due to defining of the trenches; active regions formed in the trenches; and a gettering layer formed between the inner surfaces of the substrate body and the active regions. | 10-10-2013 |
Kang Youl Lee, Icheon-Si KR
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20120080750 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias. | 04-05-2012 |
20130166993 | ERROR DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other. | 06-27-2013 |
Ki-Hong Lee, Icheon-Si KR
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20100163963 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer. | 07-01-2010 |
20140061770 | NONVOLATILE MEMORY DEVICE - A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer. | 03-06-2014 |
Kyeong Bock Lee, Icheon-Si KR
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20100244118 | Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device comprises floating gates formed over an active region of a semiconductor substrate, isolation layers formed within respective isolation regions of the semiconductor substrate, first nitridation patterns formed on sidewalls of the floating gates, a first insulating layer, a second nitride layer, a second insulating layer, and a third nitride layer formed on an entire surface of the first nitridation patterns and the isolation layers, and control gates formed over the third nitride layer. | 09-30-2010 |
Kyeong-Hyo Lee, Icheon-Si KR
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20100025806 | Semiconductor device and method of fabricating the same - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 02-04-2010 |
20110266634 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 11-03-2011 |
20110266648 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 11-03-2011 |
Kyoung Han Lee, Icheon-Si KR
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20120217562 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of maximizing a channel area in a pillar and a method of manufacturing the same are provided. The semiconductor device includes a pillar disposed on a semiconductor substrate and having first to fourth side surfaces, a first bit line disposed in the first side surface, a storage node junction region disposed in the third side surface facing the first side surface, and a gate disposed in the second side surface or a fourth side surface facing the second surface. | 08-30-2012 |
Mi Ri Lee, Icheon-Si KR
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20090163013 | Method for Forming Gate of Non-Volatile Memory Device - Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT. | 06-25-2009 |
20090186456 | Method of Manufacturing Semiconductor Device using Salicide Process - A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate. | 07-23-2009 |
Myoung Jin Lee, Icheon-Si KR
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20110254085 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING REDUCED UNIT CELL AREA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions. | 10-20-2011 |
20110255324 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SECURING GATE PERFORMANCE AND CHANNEL LENGTH - A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged to cross with the word lines, and delimiting a plurality of crossing regions where the word lines intersect the bit lines and a plurality of unit memory cell regions with each cell region bounded by an adjacent pair of the word lines and an adjacent pair of the bit lines; and gate electrodes for the respective unit memory cell regions, each gate electrode electrically connected with any one of a pair of word lines which delimit a corresponding unit memory cell, and formed such that at least a portion of the gate electrode is bent toward a bit line direction. | 10-20-2011 |
20120026773 | SEMICONDUCTOR MEMORY APPARATUS HAVING SENSE AMPLIFIER - Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line. | 02-02-2012 |
20120057395 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a cell block including a plurality of cell mats having a plurality of word lines and a plurality of bit lines perpendicular to the plurality of word lines, a cell plate electrode formed over a whole area of the cell block, and a plate power mesh line including a first plate power mesh line electrically connected to the cell plate electrode while extending in a direction parallel to the word lines, and a second plate power mesh line extending in a direction parallel to the bit lines. The first plate power mesh line includes at least one cutting part. | 03-08-2012 |
Myung Hwan Lee, Icheon-Si KR
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20120249214 | DRIVER CIRCUIT OF SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME - A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal. | 10-04-2012 |
Nam-Jae Lee, Icheon-Si KR
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20100044770 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, forming a diffusion barrier for preventing metal diffusion over the insulation layer, forming a gate electrode layer over the diffusion barrier, forming a metal layer over the gate electrode layer, and performing a thermal treatment process on the substrate structure to form a metal silicide layer having a uniform thickness. | 02-25-2010 |
20100052031 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device includes gate lines and select lines formed over a substrate, and at least two dummy lines formed in a gap region between adjacent select lines. The memory device is able to reduce a width of the select line by enhancing uniformity of the line pattern density. Therefore, a degree of integration of the memory device is enhanced and the cost of production is reduced. Furthermore, by forming a source line in a gap region between adjacent dummy lines, it is possible to secure a process margin of photolithography for forming a contact hole and to reduce contact resistance. | 03-04-2010 |
20120319186 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for forming a memory device includes: forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings. | 12-20-2012 |
Sang Don Lee, Icheon-Si KR
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20100072541 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA AND DECREASED LEAKAGE CURRENT - The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region. | 03-25-2010 |
20120274380 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes a first detection unit, a second detection unit, a control unit, and a voltage pumping unit. The first detection unit compares an internal voltage with a first reference voltage to generate a first detection signal when the first detection unit is activated in response to a first enable signal. The second detection unit compares the internal voltage with a second reference voltage to generate a second detection signal. The control unit generates the first enable signal and a second enable signal in response to the first detection signal and the second detection signal. The voltage pumping unit generates the internal voltage in response to the second enable signal. | 11-01-2012 |
20120306470 | DOWN-CONVERTING VOLTAGE GENERATING CIRCUIT - A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal. | 12-06-2012 |
Sang Kyu Lee, Icheon-Si KR
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20120026800 | SEMICONDUCTOR APPARATUS AND METHOD FOR TRANSFERRING CONTROL VOLTAGE - A semiconductor apparatus includes a control voltage transfer unit configured to transfer a control voltage transmitted through first transmission lines, to second transmission lines in response to a select signal transmitted through a select signal transmission line; a select signal driving unit configured to drive the select signal to the select signal transmission line; and a voltage boosting control unit configured to float the select signal transmission line when a voltage level of the select signal transmission line increase to or above a target level. | 02-02-2012 |
Seaung Suk Lee, Icheon-Si KR
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20100103720 | BIOSENSOR AND SENSING CELL ARRAY USING THE SAME - A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline). Ingredients of adjacent materials are separated based on electrical characteristics of ingredients by sensing magnetic susceptibility and dielectric constant depending on the sizes of the ingredients. | 04-29-2010 |
Seong Seop Lee, Icheon-Si KR
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20100008160 | Temperature sensor capable of reducing test mode time - A temperature sensor includes a temperature sensing unit for producing a sensing level by sensing an internal temperature in a semiconductor memory device, a reference level generating unit for setting up a reference level by selecting one of a plurality of reference voltages, which are set up according to the internal temperature of the semiconductor memory device, in response to a test mode signal and a temperature detecting signal, wherein the reference level generating unit includes fuse, and a comparison unit for comparing the sensing level to the reference level and producing the temperature detecting signal. | 01-14-2010 |
20110050311 | FLAG SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal. | 03-03-2011 |
20110208471 | SYNCHRONOUS MULTI-TEMPERATURE SENSOR FOR SEMICONDUCTOR INTEGRATED CIRCUITS - A temperature sensor includes a counting signal generation unit, a counting signal decoding unit, an input reference voltage selection unit, and a latch pulse generation unit. The counting signal generation unit is configured to generate one or more counting signals in response to an oscillation signal. The counting signal decoding unit is configured to decode the one or more counting signals and to generate one or more test selection signals and an end signal. The input reference voltage selection unit is configured to output a first selection reference voltage or a second selection reference voltage as an input reference voltage in response to the one or more test selection signals. The latch pulse generation unit is configured to generate one or more latch pulses in response to the one or more test selection signals. | 08-25-2011 |
20110279168 | TEMPERATURE SENSOR - A temperature sensor includes a selection signal generation unit and a reference voltage selection unit. The selection signal generation unit is configured to generate first and second selection signals in response to a fuse cutting or an input of a test mode pulse in a test mode. The reference voltage selection unit is configured to output a first reference voltage or a second reference voltage as a first selection reference voltage, and output a third reference voltage or a fourth reference voltage as a second selection reference voltage in response to the first and second selection signals. | 11-17-2011 |
20130034121 | SEMICONDUCTOR MEMORY DEVICE INCLUDING TEMPERATURE TEST CIRCUIT - A semiconductor memory device includes: a temperature sensor configured to select first and second selection reference voltages selected in a test mode as an input reference voltage according to first and second counting signals which are sequentially counted, compare the selected input reference voltage with a level of a variable voltage which changes according to internal temperature, and generate a temperature flag signal containing information on the internal temperature; and a temperature test circuit configured to output the first and second counting signals at a time point where a level of the temperature flag signal changes. | 02-07-2013 |
Seung-Hyun Lee, Icheon-Si KR
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20100065817 | Memory device and method of fabricating the same - A memory device includes a first electrode, a second electrode spaced apart from the first electrode and a nanotube or nanowire network disposed between the first electrode and the second electrode, having a heterojunction structure of a P-type network and an N-type network, and having a diode characteristic. Since the nanotube or nanowire network has the heterojunction structure of the P-type network and the N-type network, and has the diode characteristic, it is possible to enhance a degree of integration of the memory device and simplify the fabrication processes without separately requiring a selection device. | 03-18-2010 |
Seung-Hyung Lee, Icheon-Si KR
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20120242930 | BACKLIGHT UNIT AND DISPLAY DEVICE HAVING THE SAME - Provided are a backlight unit and a display device having the same. The backlight unit includes a light source configured to generate light and a plurality of light guide members stacked so that individual surfaces of each light guide member contact a surface of another one of the light guide members, the plurality of light guide members configured to guide the light. Each of the light guide members includes a light incident for receiving incident light from the light source, an opposite surface facing an adjacent one of the light guide members, and a plurality of light path change patterns disposed on the opposite surface. Thus, brightness of the display device may be improved. | 09-27-2012 |
Seung Mi Lee, Icheon-Si KR
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20100285642 | Method of Doping Impurity Ions in Dual Gate and Method of Fabricating the Dual Gate using the same - A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an upper portion of the gate conductive layer is higher than that in a lower portion; doping second conductivity type impurity ions in a portion of the gate conductive layer in the second region using a mask for opening the portion of the gate conductive layer in the second region; and diffusing the first conductivity type impurity ions and the second conductivity type impurity ions by performing heat treatment. | 11-11-2010 |
20100317180 | Method of Doping P-type Impurity Ions in Dual Poly Gate and Method of Forming Dual Poly Gate Using the Same - A method of doping p-type impurity ions in a dual poly gate, comprising: forming a polysilicon layer doped with n-type impurity ions on a substrate with a gate insulation layer being interposed between the polysilicon layer and the substrate; exposing a region of the polysilicon layer; implementing a first doping of p-type impurity ions into the exposed region of the polysilicon layer by ion implantation so with a projection range Rp to a predetermined depth of the polysilicon layer; and implementing a second doping of p-type impurity ions into the exposed region of the polysilicon layer doped with the p-type impurity ions by plasma doping with a sloped doping profile. | 12-16-2010 |
Sinjae Lee, Icheon-Si KR
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20090294941 | PACKAGE-ON-PACKAGE SYSTEM WITH HEAT SPREADER - A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base. | 12-03-2009 |
20100025835 | INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM - An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive. | 02-04-2010 |
Sul Hwan Lee, Icheon-Si KR
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20120220115 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming at least two gate patterns on a substrate, forming sidewalls surrounding the gate patterns, wherein the sidewalls extend above an upper surface of the gate patterns, and forming a first conducting material in a first space and a second space, wherein the first space is provided above the gate patterns and between the sidewalls that extend above the upper surface of the gate patterns and the second space is provided between the gate patterns. | 08-30-2012 |
Sung Yeon Lee, Icheon-Si KR
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20120106242 | MEMORY APPARATUS HAVING STORAGE MEDIUM DEPENDENT ON TEMPERATURE AND METHOD FOR DRIVING THE SAME - A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having a compensated level and width to a memory cell in response to the pulse control signal. | 05-03-2012 |
20120257436 | SEMICONDUCTOR INTERGRATED CIRCUIT AND OPERATING METHOD THEREOF - A semiconductor integrated circuit includes a variable resistive element, a current supply unit and a control signal generating unit. The resistance of the variable resistive element is changed depending on current flowing therethrough. The current supply unit controls the current in response to a control signal. The control signal generating unit generates the control signal by sensing the change in the resistance of the variable resistive element. | 10-11-2012 |
20120257445 | NONVOLATILE MEMORY APPARATUS HAVING MAGNETORESISTIVE MEMORY ELEMENTS AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line. | 10-11-2012 |
20130163349 | PROGRAMMING PULSE GENERATION CIRCUIT AND NON-VOLATILE MEMORY APPARATUS HAVING THE SAME - A program pulse generation circuit includes: a set pulse generator configured to apply a set pulse to an output node in response to a driving signal, a set pulse control signal, and a first switching signal, and a current controller configured to control step reductions forming the set pulse in response to the driving signal and a second switching signal. | 06-27-2013 |
20140185370 | NONVOLATILE MEMORY APPARATUS HAVING MAGNETORESISTIVE MEMORY ELEMENTS AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the second bit line. | 07-03-2014 |
Sun Jin Lee, Icheon-Si KR
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20120009790 | METHOD FOR FABRICATING STORAGE NODE OF SEMICONDUCTOR DEVICE - A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer. | 01-12-2012 |
Tae Yong Lee, Icheon-Si KR
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20120274348 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via receives an input voltage. The voltage driving unit is connected to the through via to receive the input voltage, changes a level of the input voltage in response to a test control signal, and generates a test voltage. The determination unit compares the input voltage with the test voltage to outputs a resultant signal. | 11-01-2012 |
20120286849 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE SYSTEM - A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal. | 11-15-2012 |
Won Hee Lee, Icheon-Si KR
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20110109861 | Fringe Field Switching Mode Liquid Crystal Display Device and Method of Fabricating the Same - Provided is a liquid crystal display including a transparent pixel electrode and a transparent common electrode in a pixel region to drive liquid crystals. The transparent common electrode includes a plurality of slits and is configured to open at least a portion of a switching device to connect unit pixels, the slits have an angle of 5 to 10° with respect to a gate line, and a rubbing direction of a liquid crystal layer is substantially parallel to a gate direction. Therefore, it is possible to provide the liquid crystal display capable of removing factors decreasing an aperture ratio, preventing light from leaking, and further improving internal reflection. | 05-12-2011 |
Young Bok Lee, Icheon-Si KR
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20080227268 | METHOD OF FORMING AN ISOLATION LAYER IN A SEMICONDUCTOR MEMORY DEVICE - A method of forming an isolation layer in a semiconductor memory device is disclosed. After a trench is formed in a semiconductor substrate, a plasma nitrification annealing process is performed before and preferably after a wall oxide layer is formed to prevent trap charges and degradation problems at the interface and sidewalls of a tunnel insulating layer due to PSZ stress induced in a subsequent process. Accordingly, a variation in the ISPP step can be prevented. | 09-18-2008 |
20090029491 | METHOD OF INSPECTING DEFECT OF SEMICONDUCTOR DEVICE - A method of inspecting defects in a semiconductor device includes forming a test pattern in a scribe lane region of a semiconductor substrate. The test pattern includes a second conductive layer formed on an isolation layer of the semiconductor substrate. Further, the method includes measuring a current flowing between the second conductive layer and the semiconductor substrate by applying a first voltage between the second conductive layer and the semiconductor substrate. Defects formed in the isolation layer can be inspected during a semiconductor manufacturing process. Accordingly, the yield of semiconductor devices can be improved with the inspection results. | 01-29-2009 |
20120119209 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes isolation layers arranged in a memory array region and a monitoring region, wherein the isolation layers are positioned in parallel; gate lines arranged to cross the isolation layers in the memory array region, wherein the gate lines are formed in the memory array region; dummy gate lines arranged in a substantially same direction as the isolation layers in the monitoring region, wherein the dummy gate lines are formed in the monitoring region; monitoring junctions arranged between the dummy gate lines and in a substantially same direction as the dummy gate lines, wherein the monitoring junctions are arranged in the monitoring region; and spacers arranged on sidewalls of each of the gate lines and the dummy gate lines, wherein at least one of the monitoring junctions is covered by any one of the spacers. | 05-17-2012 |
Youn Gyo Lee, Icheon-Si KR
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20090050179 | Cleaner composition consisting of alkalic agent, sodium polyacrylate and sterilizer and cleaning method using the same - The present invention relates to a cleaner composition comprising an alkalic agent, sodium polyacrylate as ion exchanger, a sterilizer and water, and a cleaning method using the same. More particularly, the present invention relates to a cleaner composition comprising 5 to 15 weight % of an alkalic agent, 5 to 20 weight % of sodium polyacrylate having a molecular weight 4,000 to 10,000 as ion exchanger, 0.5 to 30 weight % of a sterilizer, and water as remainder, and a cleaning method using the same. The cleaner composition of the present invention provides the effect of removing fats, proteins, minerals, etc. comparable to or better than that of the conventional cleaner, and can reduce cleaning time and cost because the cleaning process is simplified. Hence, it can be utilized to clean milking machines or other appliances. | 02-26-2009 |