Tai, CA
Albert K. Tai, San Francisco, CA US
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20090013420 | Psmcs as Modifiers of the Rb Pathway and Methods of Use - Human PSMC genes are identified as modulators of the RB pathway, and thus are therapeutic targets for disorders associated with defective RB function. Methods for identifying modulators of RB, comprising screening for agents that modulate the activity of PSMC are provided. | 01-08-2009 |
Albert K. Tai, San Franscisco, CA US
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20120107827 | PSMCs As Modifiers of the RB Pathway and Methods of Use - Human PSMC genes are identified as modulators of the RB pathway, and thus are therapeutic targets for disorders associated with defective RB function. Methods for identifying modulators of RB, comprising screening for agents that modulate the activity of PSMC are provided. | 05-03-2012 |
Anna Tai, Emeryville, CA US
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20140273144 | USE OF PHOSPHOKETOLASE AND PHOSPHOTRANSACETYLASE FOR PRODUCTION OF ACETYL-COENZYME A DERIVED COMPOUNDS - Provided herein are compositions and methods for improved production of acetyl-CoA and acetyl-CoA derived compounds in a host cell. In some embodiments, the host cell is genetically modified to comprise a heterologous nucleotide sequence encoding a phosphoketolase (PK), and a functional disruption of an endogenous enzyme that converts acetyl phosphate to acetate. In some embodiments, the host cell further comprises a heterologous nucleotide sequence encoding a phosphotransacetylase (PTA). In some embodiments, the enzyme that converts acetyl phosphate to acetate is a glycerol-1-phosphatase. In some embodiments, the glycerol-1-phosphatase is GPP1/RHR2. In some embodiments, the glycerol-1-phosphatase is GPP2/HOR2. The compositions and methods described herein provide an efficient route for the heterologous production of acetyl-CoA-derived compounds, including but not limited to, isoprenoids, polyketides, and fatty acids. | 09-18-2014 |
Anthony Ya-Nai Tai, San Jose, CA US
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20080273042 | Apparatus and method for texture level of detail computation - A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations. | 11-06-2008 |
20080273043 | Coordinate computations for non-power of 2 texture maps - A graphic processing system to compute a texture coordinate. An embodiment of the graphic processing system includes a memory device, a texture coordinate generator, and a display device. The memory device is configured to store a plurality of texture maps. The texture coordinate generator is coupled to the memory device. The texture coordinate generator is configured to compute a final texture coordinate using an arithmetic operation exclusive of a division operation. The display device is coupled to the texture coordinate generator. The display device is configured to display a representation of one of the plurality of texture maps according to the final texture coordinate. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than division. | 11-06-2008 |
20130002651 | Apparatus and Method For Texture Level Of Detail Computation - A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations. | 01-03-2013 |
Chang-Wei Tai, Los Altos, CA US
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20090288045 | Design-For-Test-Aware Hierarchical Design Planning - Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains. | 11-19-2009 |
Charles Tai, San Ramon, CA US
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20130046809 | METHOD AND APPARATUS FOR MONITORING NETWORK TRAFFIC AND DETERMINING THE TIMING ASSOCIATED WITH AN APPLICATION - A method and apparatus is disclosed herein for monitoring network traffic. In one embodiment, the method comprises monitoring, using a monitoring device located near a first end of one segment of a connection with a client and a server in a network, packets that are part of an initial TCP handshake between the client and the server and determining a network time, a server time, and a client time based on information collected when monitoring the one segment. | 02-21-2013 |
Chia Hsuan Tai, Sunnyvale, CA US
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20150370115 | Display with Column Spacer Structures - A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor layer. Column spacers may be formed on the color filter layer to maintain a desired gap between the color filter and thin-film transistor layers. Support pads may be used to support the column spacers. The column spacers and support pads may have comparable thicknesses. Different column spacers may be located at different portions of the support pads to allow the support pad size to be reduced while ensuring adequate support. | 12-24-2015 |
Chi-Chih Tai, San Ramon, CA US
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20100148523 | Gate Latch - A reversible and lockable gate latch is disclosed. The gate latch includes a pivotal latch, having a pivotal opening, a first striker bar receiving opening, and a slider lock opening, a back plate having a pivotal support opening, a second striker bar receiving opening, and a slider lock slot, a slider lock configured to slide along the slider lock slot and the slider lock opening, and a striker bar with supporting structure, where the striker bar with supporting structure is used with the pivotal latch, the back plate and the slider lock to control opening and closing of a gate. | 06-17-2010 |
Chih-Cheng Tai, Santa Clara, CA US
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20120204397 | Drinking Assistant - A drinking assistant to be used on a beverage can. The drinking assistant includes a cover portion coupled to the top of the beverage can and a skirt portion coupled to the outer surface of the cylindrical body of the drinking container. The cover portion and the skirt portion form a lid structure. The cover portion can have a recess portion having an edge substantially aligned with the edge of an opening on the top of the beverage can. | 08-16-2012 |
20130150189 | BASEBALL PITCHING TRAINING DEVICE - A pitching training device comprises a typical baseball with raised pitching training structure on top of the stitches on the seam. The pitching training structure is able to be an additional layer of stitches on top of the typical stitches of a baseball. The pitching training structure provides a finger rest area allowing a user to spin the baseball more easily at a breaking ball pitching release. | 06-13-2013 |
Chih-Cheng Tai, Sunnyvale, CA US
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20100283601 | MEDICATION USAGE MONITORING AND REMINDING DEVICE AND METHOD - The medication usage monitoring and reminding device and method enables a user to easily monitor usage of medications by weighing the medications using a weighing component, a processing component and an I/O component. Additionally, the device is able to remind a user regarding the medications if the medication has not been timely taken. The device is also able to obtain information regarding medications such as possible conflicts, updates and other information. The device is able to be used for food/drink information or dietary information. | 11-11-2010 |
20110031820 | RENEWABLE ENERGY TRANSMISSION, GENERATION, AND UTILIZATION DEVICE AND METHOD - The power generation and transmission device and method is able to be used to harness power such as solar and/or wind power and then transmit the power to a device on the other side of a physical structure such as a house, a car, a umbrella, a tent, and an awning. | 02-10-2011 |
Chih-Cheng Tai, Campbell, CA US
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20130284727 | Microwave Moisture Lock Cover - Methods of and device for retaining a moisture level of a food heated/reheated in a microwave oven are provided. The device includes a microwave splatter cover, a lid, or a lunch box integrated with a steam generator. The device is able to contain a steam generator capable of generating steam from added water when a microwave radiation is provided. The steam generator is able to rotatably couple with the center of the microwave cover. Water added to the cover is able to be temporary stored on the cover and subsequently flow to a dish structure underneath the cover. Alternatively, water is able to be added directly through a hole on the cover to the dish structure. | 10-31-2013 |
20130320780 | ENERGY TRANSMISSION, GENERATION, AND UTILIZATION DEVICE AND METHOD - The power generation and transmission device and method is able to be used to harness power such as solar and/or wind power and then transmit the power to a device on the other side of a physical structure such as a house, a car, a umbrella, a tent, and an awning. | 12-05-2013 |
20130327734 | Storage Systems for Milk Bags - Embodiments of the present invention are directed to storage systems for milk bags. A storage system for milk bags receives milk bags and management of the stored milk bags. The milk bags are stored in compartments for easy storage and retrieval. | 12-12-2013 |
20150058037 | MEDICATION USAGE MONITORING AND REMINDING DEVICE AND METHOD - The medication usage monitoring and reminding device and method enables a user to easily monitor usage of medications by weighing the medications using a weighing component, a processing component and an I/O component. Additionally, the device is able to remind a user regarding the medications if the medication has not been timely taken. The device is also able to obtain information regarding medications such as possible conflicts, updates and other information. The device is able to be used for food/drink information or dietary information. | 02-26-2015 |
20150176889 | Storage Systems for Milk Bags - Embodiments of the present invention are directed to storage systems for milk bags. A storage system for milk bags receives milk bags and management of the stored milk bags. The milk bags are stored in compartments for easy storage and retrieval. | 06-25-2015 |
20150228180 | MEDICATION USAGE MONITORING AND REMINDING DEVICE AND METHOD - The medication usage monitoring and reminding device and method enables a user to easily monitor usage of medications by weighing the medications using a weighing component, a processing component and an I/O component. Additionally, the device is able to remind a user regarding the medications if the medication has not been timely taken. The device is also able to obtain information regarding medications such as possible conflicts, updates and other information. The device is able to be used for food/drink information or dietary information. | 08-13-2015 |
20150367217 | RAISED SEEM BASEBALL TRAINING DEVICE - A first baseball comprises a skin portion and a first seam portion higher than a second seam portion. A second baseball comprises a skin, a first seam portion having a first stitches pattern, and a second seam portion having a second stitches pattern different from the first stitches pattern. A baseball training kit comprises a skin portion and a first seam portion having a first stitches feature and a second seam portion having a second stitches feature different from the first stitches feature. | 12-24-2015 |
20160046835 | ANTI-CORROSIVE, WEAR RESISTANT AND ANTI-UV COATING FOR THERMAL TRANSFER, AND PREPARATION METHOD AND APPLICATION OF THE SAME - An anti-corrosive, wear-resistant, and UV-blocking/absorbing coating for dye sublimation, the preparation method thereof, and the application thereof are provided. The coating for dye sublimation includes the following compositions, in parts by weight: 70 to 99 parts of polyurethane, 0.4 to 10 parts of inorganic nano silicon oxides, 0.3 to 10 parts of inorganic nano aluminum oxides, and 0.3 to 10 parts of inorganic nano zirconium oxides. | 02-18-2016 |
Daniel Tai, Union City, CA US
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20160073249 | SYSTEM AND METHOD FOR DISCOVERING A WIRELESS DEVICE - One or more discovery communications are received by a user device over a wireless communication medium. The one or more discovery communications can be communicated using a Layer 2 protocol. The one or more discovery communications can be processed to determine information included with the one or more discovery communications. The information can include an identifier of the wireless device and dynamic information about an active process of the wireless device. When the user device is not connected to the discovered wireless device, the user device displays a representation of the wireless device. The representation can include information determined from the one or more discovery communications, including the identifier of the wireless device and content that is based on the dynamic information. | 03-10-2016 |
Daniel Tai, Sunnyvale, CA US
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20090196303 | SWITCH FABRIC WITH MEMORY MANAGEMENT UNIT FOR IMPROVED FLOW CONTROL - A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module. | 08-06-2009 |
Daniel Tai, Santa Clara, CA US
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20110035580 | MEDIA ACCESS CONTROL SECURITY MANAGEMENT IN PHYSICAL LAYER - A media access control (MAC) security (MACsec) function block may implement MACsec protocols on a network. A physical layer device (PHY) may connect to the MACsec function block and an interface register configured to store command information for the MACsec function block. A central processing unit (CPU) may provide the command information for the MACsec function block to the PHY via a management data input/output (MDIO) bus. The PHY may execute either a read command or a write command against the MACsec function block based on the command information, receive, from the MACsec function block, a response corresponding to the execution of the read command or write command against the MACsec function block, and provide the response to the CPU via the MDIO bus. | 02-10-2011 |
Daniel D. Tai, Union City, CA US
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20140149544 | SYSTEM AND METHOD FOR PROVIDING RIGHTS MANAGEMENT SERVICES FOR NETWORK SERVICES - A first device implements an application platform that is shared with a second device. The application platform can be implemented so that the first device and the second device operate to have a same identity to at least the network service. The first device provides a user interface in order to receive input for accessing or using the network service. Additionally, the first device communicates input received in response to providing the user interface to the network service. The first device can receive a token from the network service in response to communicating the input. Additionally, the first device can communicate a set of data items to the second device. The set of data items includes the token and one or more identifiers that enable the second device to access and use the network service while appearing as the first device to the network service. | 05-29-2014 |
20140149876 | SYSTEM AND METHOD FOR USE OF NETWORK SERVICES IN RECEIVING CONTENT AND DATA - A first device implements an application platform that is shared with a second device. The application platform can be implemented so that the first device and the second device operate to have a same identity to at least the network service. The first device provides a user interface in order to receive input for accessing or using the network service. Additionally, the first device communicates input received in response to providing the user interface to the network service. The first device can receive a token from the network service in response to communicating the input. Additionally, the first device can communicate a set of data items to the second device. The set of data items includes the token and one or more identifiers that enable the second device to access and use the network service while appearing as the first device to the network service. | 05-29-2014 |
20140150079 | SYSTEM AND METHOD FOR AUTHENTICATING MULTIPLE DEVICES WITH A SAME CREDENTIAL - A first device implements an application platform that is shared with a second device. The application platform can be implemented so that the first device and the second device operate to have a same identity to at least the network service. The first device provides a user interface in order to receive input for accessing or using the network service. Additionally, the first device communicates input received in response to providing the user interface to the network service. The first device can receive a token from the network service in response to communicating the input. Additionally, the first device can communicate a set of data items to the second device. The set of data items includes the token and one or more identifiers that enable the second device to access and use the network service while appearing as the first device to the network service. | 05-29-2014 |
Daniel W. Tai, Cupertino, CA US
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20130259047 | INTERNET GROUP MEMBERSHIP PROTOCOL GROUP MEMBERSHIP SYNCHRONIZATION IN VIRTUAL LINK AGGREGATION - In one embodiment, a system includes at least one local processor adapted for executing logic, logic adapted for receiving a packet from an access switch on a virtual link aggregation (vLAG) port of a first switch, logic adapted for modifying a source media access control (MAC) address of the packet to include a MAC address of the first switch, wherein a last byte of the modified source MAC address includes a trunk identifier of the vLAG port on which the packet was received, and logic adapted for forwarding the packet to an inter-switch link (ISL) port. Other systems, methods, and computer program products are presented according to more embodiments. | 10-03-2013 |
Dyson Tai, Cupertino, CA US
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20110101201 | Photodetector Array Having Electron Lens - Photodetectors, photodetector arrays, image sensors, and other apparatus are disclosed. An apparatus, of one aspect, may include a surface to receive light, a photosensitive region disposed within a substrate, and a material coupled between the surface and the photosensitive region. The material may receive the light. At least some of the light may free electrons in the material. An electron lens coupled between the surface and the material may focus the electrons in the material toward the photosensitive region. Other apparatus are also disclosed, as are methods of using such apparatus, methods of fabricating such apparatus, and systems incorporating such apparatus. | 05-05-2011 |
Dyson Tai, San Jose, CA US
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20150295007 | IMAGE SENSOR WITH DIELECTRIC CHARGE TRAPPING DEVICE - An image sensor pixel includes a photosensitive element, a floating diffusion region, a transfer gate, a dielectric charge trapping region, and a first metal contact. The photosensitive element is disposed in a semiconductor layer to receive electromagnetic radiation along a vertical axis. The floating diffusion region is disposed in the semiconductor layer, while the transfer gate is disposed on the semiconductor layer to control a flow of charge produced in the photosensitive element to the floating diffusion region. The dielectric charge trapping device is disposed on the semiconductor layer to receive electromagnetic radiation along the vertical axis and to trap charges in response thereto. The dielectric charge trapping device is further configured to induce charge in the photosensitive element in response to the trapped charges. The first metal contact is coupled to the dielectric charge trapping device to provide a first bias voltage to the dielectric charge trapping device. | 10-15-2015 |
Dyson H. Tai, San Jose, CA US
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20140035089 | PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via. | 02-06-2014 |
20140312447 | LATERAL LIGHT SHIELD IN BACKSIDE ILLUMINATED IMAGING SENSORS - A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. | 10-23-2014 |
20150076639 | OPTICAL SHIELD IN A PIXEL CELL PLANARIZATION LAYER FOR BLACK LEVEL CORRECTION - A pixel array includes a plurality of photodiodes disposed in a semiconductor layer and arranged in the pixel array. A color filter layer is disposed proximate to the semiconductor layer. Light is to be directed to at least a first one of the plurality of photodiodes through the color filter layer. An optical shield layer is disposed proximate to the color filter layer. The color filter layer is disposed between the optical shield layer and the semiconductor layer. The optical shield layer shields at least a second one of the plurality of photodiodes from the light. | 03-19-2015 |
20150097213 | IMAGE SENSOR AND PIXELS INCLUDING VERTICAL OVERFLOW DRAIN - Embodiments of an apparatus comprising a pixel array including a plurality of pixels formed in a substrate having a front surface and a back surface, each pixel including a photosensitive region formed at or near the front surface and extending into the substrate a selected depth from the front surface. A filter array is coupled to the pixel array, the filter array including a plurality of individual filters each optically coupled to a corresponding photosensitive region, and a vertical overflow drain (VOD) is positioned in the substrate between the back surface and the photosensitive region of at least one pixel in the array. | 04-09-2015 |
20150108507 | IMAGE SENSOR WITH DOPED SEMICONDUCTOR REGION FOR REDUCING IMAGE NOISE - A backside illuminated image sensor includes a semiconductor layer having a back-side surface and a front-side surface. The semiconductor layer includes a pixel array region including a plurality of photodiodes configured to receive image light through the back-side surface of the semiconductor layer. The semiconductor layer also includes a peripheral circuit region including peripheral circuit elements for operating the plurality of photodiodes that borders the pixel array region. The peripheral circuit elements emit photons. The peripheral circuit region also includes a doped semiconductor region positioned to absorb the photons emitted by the peripheral circuit elements to prevent the plurality of photodiodes from receiving the photons. | 04-23-2015 |
20150123172 | BIG-SMALL PIXEL SCHEME FOR IMAGE SENSORS - An image sensor pixel for use in a high dynamic range image sensor includes a first photodiode, a plurality of photodiodes, a shared floating diffusion region, a first transfer gate, and a second transfer gate. The first photodiode is disposed in a semiconductor material. The first photodiode has a first light exposure area and a first doping concentration. The plurality of photodiodes is also disposed in the semiconductor material. Each photodiode in the plurality of photodiodes has the first light exposure area and the first doping concentration. The first transfer gate is coupled to transfer first image charge from the first photodiode to the shared floating diffusion region. The second transfer gate is coupled to transfer distributed image charge from each photodiode in the plurality of photodiodes to the shared floating diffusion region. | 05-07-2015 |
20150130010 | Dual Pixel-Sized Color Image Sensors And Methods For Manufacturing The Same - A dual pixel-size color image sensor, including an imaging surface, for imaging of incident light, and a plurality of color pixels, each color pixel including (a) four large photosites, including two large first-color photosites sensitive to a first color of the incident light, and (b) four small photosites including two small first-color photosites sensitive to the first color of the incident light. The large and small first-color photosites are arranged such that connected regions of the imaging surface, not associated with large and/or small first-color photosites, are not continuous straight lines. A method for manufacturing a color filter array on an imaging surface of a dual pixel-size image sensor includes forming a first-color coating on first portions of the imaging surface to form large and small first-color photosites sensitive to a first color, wherein connected portions of the imaging surface, different from the first portions, are not continuous straight lines. | 05-14-2015 |
20150236058 | IMAGE SENSOR PIXEL CELL WITH SWITCHED DEEP TRENCH ISOLATION STRUCTURE - A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion. | 08-20-2015 |
20150270302 | IMAGE SENSOR HAVING A GAPLESS MICROLENSES - An image sensor includes a plurality of photosensitive devices arranged in a semiconductor substrate. A planar layer is disposed over the plurality of photosensitive devices in the semiconductor substrate. A plurality of first microlenses comprised of a lens material is arranged in first lens regions on the planar layer. A plurality of lens barriers comprised of the lens material is arranged on the planar layer to provide boundaries that define second lens regions on the planar layer. A plurality of second microlenses comprised of the lens material is formed within the boundaries provided by the plurality of lens barriers that define the second lens regions on the planar layer. The plurality of lens barriers are integrated with respective second microlenses after a reflow process of the plurality of second microlenses. | 09-24-2015 |
20150271377 | COLOR IMAGE SENSOR WITH METAL MESH TO DETECT INFRARED LIGHT - An image sensor includes a pixel array with a plurality of pixels arranged in a semiconductor layer. A color filter array including a plurality of groupings of filters is disposed over the pixel array. Each filter is optically coupled to a corresponding one of the plurality pixels. Each one of the plurality of groupings of filters includes a first, a second, a third, and a fourth filter having a first, a second, the second, and a third color, respectively. A metal layer is disposed over the pixel array and is patterned to include a metal mesh having mesh openings with a size and pitch to block incident light having a fourth color from reaching the corresponding pixel. The metal layer is patterned to include openings without the metal mesh to allow the incident light to reach the other pixels. | 09-24-2015 |
20150303235 | IMAGE SENSOR PIXEL HAVING STORAGE GATE IMPLANT WITH GRADIENT PROFILE - A pixel cell includes a storage transistor disposed in a semiconductor substrate. The storage transistor includes a storage gate disposed over the semiconductor substrate, and a storage gate implant that is annealed and has a gradient profile in the semiconductor substrate under the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate. A transfer transistor is disposed in the semiconductor substrate and is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. The transfer transistor includes a transfer gate disposed over the semiconductor substrate. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a read out node. The output transistor includes an output gate disposed over the semiconductor substrate. | 10-22-2015 |
20160037111 | NEGATIVE BIASED SUBSTRATE FOR PIXELS IN STACKED IMAGE SENSORS - A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip. | 02-04-2016 |
20160071892 | DOPANT CONFIGURATION IN IMAGE SENSOR PIXELS - An image sensor pixel including a photodiode includes a first dopant region disposed within a semiconductor layer and a second dopant region disposed above the first dopant region and within the semiconductor layer. The second dopant region contacts the first dopant region and the second dopant region is of an opposite majority charge carrier type as the first dopant region. A third dopant region is disposed above the first dopant region and within the semiconductor layer. The third dopant region is of a same majority charge carrier type as the second dopant region but has a greater concentration of free charge carriers than the second dopant region. A transfer gate is positioned to transfer photogenerated charge from the photodiode. The second dopant region extends closer to an edge of the transfer gate than the third dopant region. | 03-10-2016 |
20160086999 | HIGH NEAR INFRARED SENSITIVITY IMAGE SENSOR - An image sensor includes a plurality of photodiodes disposed proximate to a frontside of a first semiconductor layer to accumulate image charge in response to light directed into the frontside of the first semiconductor layer. A plurality of pinning wells is disposed in the first semiconductor layer. The pinning wells separate individual photodiodes included in the plurality of photodiodes. A plurality of dielectric layers is disposed proximate to a backside of the first semiconductor layer. The dielectric layers are tuned such that light having a wavelength substantially equal to a first wavelength included in the light directed into the frontside of the first semiconductor layer is reflected from the dielectric layers back to a respective one of the plurality of photodiodes disposed proximate to the frontside of the first semiconductor layer. | 03-24-2016 |
20160088265 | COLOR FILTER ARRAY WITH REFERENCE PIXEL TO REDUCE SPECTRAL CROSSTALK - A color filter array includes a plurality of tiled minimal repeating units, each minimal repeating unit comprising an M×N set of individual filters. Each minimal repeating unit includes a plurality of imaging filters including individual filters having at least first, second, and third photoresponses, and at least one reference filter having a reference photoresponse, wherein the reference filter is positioned among the imaging filters and wherein the reference photoresponse transmits substantially the crosstalk spectrum that is not filtered from light incident on the color filter array by the plurality of imaging filters. Other embodiments are disclosed and claimed. | 03-24-2016 |
Dyson Hsinchih Tai, San Jose, CA US
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20140374862 | CMOS Image Sensor With Integrated Silicon Color Filters - A color photosensor array has photosensors of a first type having a thick overlying silicon layer, photosensors of a second type having a thin overlying silicon layer, and photosensors of a third type having no overlying silicon layer; the photosensors of the first type having peak sensitivity in the red, the photosensors of the second type having peak sensitivity in the green. In particular embodiments, color correction circuitry is provided to enhance color saturation. | 12-25-2014 |
20150163418 | Image Sensors For Capturing Both Visible Light Images And Infrared Light Images, And Associated Systems And Methods - An image sensor for capturing both visible light images and infrared light images includes a semiconductor substrate having length, width, and height, a plurality of visible light photodetectors disposed in the semiconductor substrate, and a plurality of combination light photodetectors disposed in the semiconductor substrate. Each of the plurality of visible light photodetectors has a respective depth in the height direction, and each of the plurality of combination light photodetectors has a respective depth in the height direction that is greater than the respective depth of each of the plurality of visible light photodetectors. | 06-11-2015 |
20160104735 | Dual-Mode Image Sensor With A Signal-Separating Color Filter Array, And Method For Same - A dual-mode image sensor with a signal-separating CFA includes a substrate including a plurality of photodiode regions and a plurality of tall spectral filters having a uniform first height and for transmitting a first electromagnetic wavelength range. Each of the tall spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of short spectral filters for transmitting one or more spectral bands within a second electromagnetic wavelength range. Each of the short spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of single-layer blocking filters for blocking the first electromagnetic wavelength range. Each single-layer blocking filter is disposed on a respective short spectral filter. Each single-layer blocking filter and its respective short spectral filter have a combined height substantially equal to the first height. | 04-14-2016 |
Dyson Hsin-Chih Tai, San Jose, CA US
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20150318327 | BACKSIDE ILLUMINATED COLOR IMAGE SENSORS AND METHODS FOR MANUFACTURING THE SAME - A method for manufacturing a backside illuminated color image sensor includes (a) modifying the frontside of an image sensor wafer, having pixel arrays, to produce electrical connections to the pixel arrays, wherein the electrical connections extend depth-wise into the image sensor wafer from the frontside, and (b) modifying the backside of the image sensor wafer to expose the electrical connections. | 11-05-2015 |
Elizabeth Tai, Cupertino, CA US
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20100136771 | SUB-CRITICAL SHEAR THINNING GROUP IV BASED NANOPARTICLE FLUID - A Group IV based nanoparticle fluid is disclosed. The nanoparticle fluid includes a set of nanoparticles—comprising a set of Group IV atoms, wherein the set of nanoparticles is present in an amount of between about 1 wt % and about 20 wt % of the nanoparticle fluid. The nanoparticle fluid also includes a set of HMW molecules, wherein the set of HMW molecules is present in an amount of between about 0 wt % and about 5 wt % of the nanoparticle fluid. The nanoparticle fluid further includes a set of capping agent molecules, wherein at least some capping agent molecules of the set of capping agent molecules are attached to the set of nanoparticles. | 06-03-2010 |
20110012066 | GROUP IV NANOPARTICLE FLUID - A Group IV based nanoparticle fluid is disclosed. The nanoparticle fluid includes a set of nanoparticles-comprising a set of Group IV atoms, wherein the set of nanoparticles is present in an amount of between about 1 wt % and about 20 wt % of the nanoparticle fluid. The nanoparticle fluid also includes a set of HMW molecules, wherein the set of HMW molecules is present in an amount of between about 0 wt % and about 5 wt % of the nanoparticle fluid. The nanoparticle fluid further includes a set of capping agent molecules, wherein at least some capping agent molecules of the set of capping agent molecules are attached to the set of nanoparticles. | 01-20-2011 |
20140065764 | METHOD FOR MANUFACTURING A PHOTOVOLTAIC CELL WITH A LOCALLY DIFFUSED REAR SIDE - A method for manufacturing a photovoltaic cell with a locally diffused rear side, comprising steps of: (a) providing a doped silicon substrate, the substrate comprising a front, sunward facing, surface and a rear surface; (b) forming a silicon dioxide layer on the front surface and the rear surface; (c) depositing a boron-containing doping paste on the rear surface in a pattern, the boron-containing paste comprising a boron compound and a solvent; (d) depositing a phosphorus-containing doping paste on the rear surface in a pattern, the phosphorus-containing doping paste comprising a phosphorus compound and a solvent; (e) heating the silicon substrate in an ambient to a first temperature and for a first time period in order to locally diffuse boron and phosphorus into the rear surface of the silicon substrate. | 03-06-2014 |
20150364615 | ALUMINUM-TIN PASTE AND ITS USE IN MANUFACTURING SOLDERABLE ELECTRICAL CONDUCTORS - The present invention is directed to a paste composition comprising Al and Sn dispersed in an organic medium and to paste compositions that provide a solderable electrode. The present invention is further directed to an electrode formed from the paste composition and a semiconductor device and, in particular, a solar cell comprising such an electrode. The paste compositions that provide a solderable electrode are particularly useful for forming a solar cell back side solderable electrode. | 12-17-2015 |
Franklin Tai, Playa Del Rey, CA US
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20130084847 | METHOD AND SYSTEM FOR CONTROLLING A MOBILE COMMUNICATION DEVICE - Disclosed herein is a method and system for detecting, monitoring and/or controlling one or more of mobile services for a mobile communication device (also referred to herein as a Controllable Mobile Device or CMD), and in particular, when the device is being used and the vehicle, operated by the user of the device, is moving. The present method and system determines whether the vehicle is being operated by a user that may also have access to a mobile communication device which, if used concurrently while the vehicle is in operation, may lead to unsafe operation of the vehicle. If the mobile services control system determines that a vehicle operator has potentially unsafe access to a mobile communication device, the mobile services control system may restrict operator access to one or more services that would otherwise be available to the operator via the mobile communication device. | 04-04-2013 |
20140113619 | METHOD AND SYSTEM FOR CONTROLLING AND MODIFYING DRIVING BEHAVIORS - Disclosed herein is a method and system for detecting, monitoring and/or controlling one or more of mobile services for a mobile communication device (also referred to herein as a Controllable Mobile Device or CMD), and in particular, when the device is being used and the vehicle, operated by the user of the device, is moving. In addition, one aspect of the invention generally relates to a method and system for modifying a user's driving behaviors, in particular to a system and method for modifying a user's unsafe driving behaviors, e.g., using one or more services of a controllable mobile device while driving, by providing a score to the user rating indicating that they are using a mobile device in a distracting way, or driving in a manner that indicates that they are distracted. | 04-24-2014 |
Gwo-Chung Tai, San Jose, CA US
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20090021310 | SYSTEM AND METHOD FOR PHASE-LOCKED LOOP (PLL) FOR HIGH-SPEED MEMORY INTERFACE (HSMI) - A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures. | 01-22-2009 |
Han Tai, Corona, CA US
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20090302205 | LENS FRAME AND OPTICAL FOCUS ASSEMBLY FOR IMAGER MODULE - An imager apparatus and methods are described. An embodiment of an imager module includes a plurality of groups of optical lenses, a lens frame, and at least one associated lens barrel configured to position and hold the plurality of groups of optical lenses. At least one of the groups of optical lenses is movable with respect to at least one other group of optical lenses for achieving optical focus. The imager module includes an integrated circuit (IC) imager die in proximity to the plurality of lenses, the imager die containing at least one image capture microelectronic device. The imager module includes a modular frame assembly that contains a first portion that holds a plurality of lens barrels, each containing one or more focusing lenses, and a second portion that supports the first portion at a specific distance from the substrate being imaged. The lens barrels are each responsive to different wavelengths or bands of wavelengths. The first and second portions include minimal, partial, or full partition structures between the imaging areas defined by the lens barrels. | 12-10-2009 |
Hsi-Chih Tai, San Jose, CA US
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20130113969 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING IMPROVED FULL WELL CAPACITY IN AN IMAGE SENSOR PIXEL - Techniques and mechanisms for improving full well capacity for pixel structures in an image sensor. In an embodiment, a first pixel structure of the image sensor includes an implant region, where a skew of the implant region corresponds to an implant angle, and a second pixel structure of the image sensor includes a transfer gate. In another embodiment, an offset of the implant region of the first pixel structure from the transfer gate of the second pixel structure corresponds to the implant angle. | 05-09-2013 |
Hsin-Chih Tai, San Jose, CA US
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20100038523 | IMAGE SENSOR WITH BURIED SELF ALIGNED FOCUSING ELEMENT - An image sensor includes an optical sensor region, a stack of dielectric and metal layers, and an embedded layer. The optical sensor is disposed within a semiconductor substrate. The stack of dielectric and metal layers are disposed on the front side of the semiconductor substrate above the optical sensor region. The embedded focusing layer is disposed on the backside of the semiconductor substrate in a Backside Illuminated (BSI) image sensor, supported by a support grid, or a support grid composed of the semiconductor substrate. | 02-18-2010 |
20100323470 | BACKSIDE ILLUMINATED IMAGE SENSOR HAVING DEEP LIGHT REFLECTIVE TRENCHES - An array of pixels is formed using a semiconductor layer having a frontside and a backside through which incident light is received. Each pixel typically includes a photosensitive region formed in the semiconductor layer and a trench formed adjacent to the photosensitive region. The trench causes the incident light to be directed away from the trench and towards the photosensitive region. | 12-23-2010 |
20110068429 | IMAGE SENSOR WITH CONTACT DUMMY PIXELS - An image sensor array includes a substrate layer, a metal layer, an epitaxial layer, a plurality of imaging pixels, and a contact dummy pixel. The metal layer is disposed above the substrate layer. The epitaxial layer is disposed between the substrate layer and the metal layer. The imaging pixels are disposed within the epitaxial layer and each include a photosensitive element for collecting an image signal. The contact dummy pixel is dispose within the epitaxial layer and includes an electrical conducting path through the epitaxial layer. The electrical conducting path couples to the metal layer above the epitaxial layer. | 03-24-2011 |
20110085067 | MULTILAYER IMAGE SENSOR PIXEL STRUCTURE FOR REDUCING CROSSTALK - An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type. | 04-14-2011 |
20110089311 | TRENCH TRANSFER GATE FOR INCREASED PIXEL FILL FACTOR - An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion. | 04-21-2011 |
20110089517 | CMOS IMAGE SENSOR WITH HEAT MANAGEMENT STRUCTURES - An image sensor includes a device wafer substrate of a device wafer, a device layer of the device wafer, and optionally a heat control structure and/or a heat sink. The device layer is disposed on a frontside of the device wafer substrate and includes a plurality of photosensitive elements disposed within a pixel array region and peripheral circuitry disposed within a peripheral circuits region. The photosensitive elements are sensitive to light incident on a backside of the device wafer substrate. The heat control structure is disposed within the device wafer substrate and thermally isolates the pixel array region from the peripheral circuits region to reduce heat transfer between the peripheral circuits region and the pixel array region. The heat sink conducts heat away from the device layer. | 04-21-2011 |
20110115002 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH REINFORCED PAD STRUCTURE - A backside illuminated imaging sensor with reinforced pad structure includes a device layer, a metal stack, an opening and a frame. The device layer has an imaging array formed in a front side of the device layer and the imaging array is adapted to receive light from a back side of the device layer. The metal stack is coupled to the front side of the device layer where the metal stack includes at least one metal interconnect layer having a metal pad. The opening extends from the back side of the device layer to the metal pad to expose the metal pad for wire bonding. The frame is disposed within the opening to structurally reinforce the metal pad. | 05-19-2011 |
20110140221 | IMAGE SENSOR HAVING CURVED MICRO-MIRRORS OVER THE SENSING PHOTODIODE AND METHOD FOR FABRICATING - The invention involves the integration of curved micro-mirrors over a photodiode active area (collection area) in a CMOS image sensor (CIS) process. The curved micro-mirrors reflect light that has passed through the collection area back into the photo diode. The curved micro-mirrors are best implemented in a backside illuminated device (BSI). | 06-16-2011 |
20110169991 | IMAGE SENSOR WITH EPITAXIALLY SELF-ALIGNED PHOTO SENSORS - An image sensor pixel includes a substrate doped to have a first conductivity type. A first epitaxial layer is disposed over the substrate and doped to also have the first conductivity type. A transfer transistor gate is formed on the first epitaxial layer. An epitaxially grown photo-sensor region is disposed in the first epitaxial layer and has a second conductivity type. The epitaxially grown photo-sensor region includes an extension region that extends under a portion of the transfer transistor gate. | 07-14-2011 |
20110177650 | CMOS IMAGE SENSOR WITH SELF-ALIGNED PHOTODIODE IMPLANTS - An example method of forming a pinned photodiode includes applying a photoresist mask to a semiconductor layer at a location where a transfer gate will subsequently be formed. First dopant ions are then implanted at a first angle to form a first dopant region under an edge of the photoresist mask. Next, a photoresist mask is etched such that a thickness of the photoresist mask is reduced to form a trimmed photoresist mask. Second dopant ions are then implanted at a second angle to form a second dopant region, wherein the second dopant ions are shadowed by the trimmed photoresist mask to exclude the second dopant ions from a region partially above the first dopant region and adjacent to an edge of the trimmed photoresist mask. | 07-21-2011 |
20110199518 | IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION - An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array. | 08-18-2011 |
20110241090 | HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT - Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed. | 10-06-2011 |
20110260221 | LASER ANNEAL FOR IMAGE SENSORS - A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing. | 10-27-2011 |
20120013777 | CMOS IMAGE SENSOR WITH IMPROVED PHOTODIODE AREA ALLOCATION - Embodiments of an apparatus comprising a pixel array comprising a plurality of macropixels. Each macropixel includes a pair of first pixels each including a color filter for a first color, the first color being one to which pixels are most sensitive, a second pixel including a color filter for a second color, the second color being one to which the pixels are least sensitive and a third pixel including a color filter for a third color, the third color being one to which pixels have a sensitivity between the least sensitive and the most sensitive, wherein the first pixels each occupy a greater proportion of the light-collection area of the macropixel than either the second pixel or the third pixel. Corresponding process and system embodiments are disclosed and claimed. | 01-19-2012 |
20120018620 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH VERTICAL PIXEL SENSOR - A backside illuminated imaging sensor includes a vertical stacked sensor that reduces cross talk by using different silicon layers to form photodiodes at separate levels within a stack (or separate stacks) to detect different colors. Blue light-, green light-, and red light-detection silicon layers are formed, with the blue light detection layer positioned closest to the backside of the sensor and the red light detection layer positioned farthest from the backside of the sensor. An anti-reflective coating (ARC) layer can be inserted in between the red and green light detection layers to reduce the optical cross talk captured by the red light detection layer. Amorphous polysilicon can be used to form the red light detection layer to boost the efficiency of detecting red light. | 01-26-2012 |
20120019695 | IMAGE SENSOR HAVING DARK SIDEWALLS BETWEEN COLOR FILTERS TO REDUCE OPTICAL CROSSTALK - An apparatus and technique for fabricating an image sensor including the dark sidewall films disposed between adjacent color filters. The image sensor further includes an array of photosensitive elements disposed in a substrate layer, a color filter array (“CFA”) including CFA elements having at least two different colors disposed on a light incident side of the substrate layer, and an array of microlenses disposed over the CFA. Each microlens is aligned to direct light incident on the light incident side of the image sensor through a corresponding CFA element to a corresponding photosensitive element. The dark sidewall films are disposed on sides of the CFA elements and separate adjacent ones of the CFA elements having different colors. | 01-26-2012 |
20120019696 | IMAGE SENSOR WITH DUAL ELEMENT COLOR FILTER ARRAY AND THREE CHANNEL COLOR OUTPUT - A color image sensor is disclosed. The color image sensor includes a pixel array including a color filter array (“CFA”) overlaying an array of photo-sensors for acquiring a color image. The CFA includes first color filter elements of a first color overlaying a first group of the photo-sensors and second color filter elements of a second color overlaying a second group of the photo-sensors. The first color filter elements contribute to a first color channel of the color image and the second color filter elements contribute to a second color channel of the color image. The color image sensor further includes a color combiner unit coupled to combine the first color channel with the second color channel to generate a third color channel of the color image based on the first and second color channels. An output port is coupled to the pixel array to output the color image having three color channels including the first, second, and third color channels. | 01-26-2012 |
20120038014 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH STRESSED FILM - A backside illuminated (“BSI”) complementary metal-oxide semiconductor (“CMOS”) image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident on a backside of the BSI CMOS image sensor to collect an image charge. The stress adjusting layer is disposed on a backside of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region. | 02-16-2012 |
20120080765 | METHOD OF DAMAGE-FREE IMPURITY DOPING FOR CMOS IMAGE SENSORS - A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed. | 04-05-2012 |
20120086844 | CIRCUIT AND PHOTO SENSOR OVERLAP FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A method of operation of a backside illuminated (BSI) pixel array includes acquiring an image signal with a first photosensitive region of a first pixel within the BSI pixel array. The image signal is generated in response to light incident upon a backside of the first pixel. The image signal acquired by the first photosensitive region is transferred to pixel circuitry of the first pixel disposed on a frontside of the first pixel opposite the backside. The pixel circuitry at least partially overlaps the first photosensitive region of the first pixel and extends over die real estate above a second photosensitive region of a second pixel adjacent to the first pixel such that the second pixel donates die real estate unused by the second pixel to the first pixel to accommodate larger pixel circuitry than would fit within the first pixel. | 04-12-2012 |
20120104525 | IMAGE SENSOR WITH COLOR PIXELS HAVING UNIFORM LIGHT ABSORPTION DEPTHS - An example image sensor includes first, second, and third micro-lenses. The first micro-lens is in a first color pixel and has a first curvature and a first height. The second micro-lens is in a second color pixel and has a second curvature and a second height. The third micro-lens is in a third color pixel and has a third curvature and a third height. The first curvature is the same as both the second curvature and the third curvature and the first height is greater than the second height and the second height is greater than the third height, such that light absorption depths for the first, second, and third color pixels are the same. | 05-03-2012 |
20120153123 | IMAGE SENSOR HAVING SUPPLEMENTAL CAPACITIVE COUPLING NODE - An image sensor includes a pixel array, a bit line, supplemental capacitance node line, and a supplemental capacitance circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells to selectively couple a supplemental capacitance to the FD nodes of the second group in response to a control signal. In various embodiments, the first and second group of pixel cells may be the same group or a different group of the pixel cells and may add a capacitive boost feature or a multi conversion gain feature. | 06-21-2012 |
20120175722 | SEAL RING SUPPORT FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring. | 07-12-2012 |
20120235212 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH REDUCED BLOOMING AND ELECTRICAL SHUTTER - Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor. | 09-20-2012 |
20120249845 | IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION - An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array. | 10-04-2012 |
20120261730 | FLOATING DIFFUSION STRUCTURE FOR AN IMAGE SENSOR - An image sensor including a pixel array having a floating diffusion region of a pixel which is disposed in a substrate, the floating diffusion region to receive a charge from a photosensitive region. In an embodiment, a transfer gate disposed on the substrate, wherein a portion of the transfer gate forms a cavity extending through the transfer gate. In another embodiment, a cavity extending through a transfer gate exposes a floating diffusion region. | 10-18-2012 |
20120280109 | METHOD, APPARATUS AND SYSTEM TO PROVIDE CONDUCTIVITY FOR A SUBSTRATE OF AN IMAGE SENSING PIXEL - Techniques for promoting conductivity in a substrate for a pixel array. In an embodiment, an isolation region and a dopant well are disposed within an epitaxial layer adjoining the substrate, where a portion of the dopant well is between the substrate and a portion of the isolation well. In another embodiment, a contact is further disposed within the epitaxial layer, where a portion of the isolation region surrounds a portion of the contact. | 11-08-2012 |
20120282728 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH REINFORCED PAD STRUCTURE - A method of fabricating a backside illuminated imaging sensor that includes a device layer, a metal stack, and an opening is disclosed. The device layer has an imaging array formed in a front side of the device layer, where the imaging array is adapted to receive light from a back side of the device layer. The metal stack is coupled to the front side of the device layer and includes at least one metal interconnect layer having a metal pad. The opening extends from the back side of the device layer to the metal pad to expose the metal pad for wire bonding. The method includes depositing a film on the back side of the device layer and within the opening, then etching the film to form a frame within the opening to structurally reinforce the metal pad. | 11-08-2012 |
20120302000 | LASER ANNEAL FOR IMAGE SENSORS - A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing. | 11-29-2012 |
20120313197 | IN-PIXEL HIGH DYNAMIC RANGE IMAGING - Embodiments of the invention describe providing high dynamic range imaging (HDRI or simply HDR) to an imaging pixel by coupling a floating diffusion node of the imaging pixel to a plurality of metal-oxide semiconductor (MOS) capacitance regions. It is understood that a MOS capacitance region only turns “on” (i.e., changes the overall capacitance of the floating diffusion node) when the voltage at the floating diffusion node (or a voltage difference between a gate node and the floating diffusion node) is greater than its threshold voltage; before the MOS capacitance region is “on” it does not contribute to the overall capacitance or conversion gain of the floating diffusion node. | 12-13-2012 |
20130001661 | HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT - Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed. | 01-03-2013 |
20130009043 | IMAGE SENSOR HAVING SUPPLEMENTAL CAPACITIVE COUPLING NODE - An image sensor includes a pixel array, a bit line, a supplemental capacitance node line, and a control circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells different from the first group. The control circuit is coupled to the supplemental capacitance node line to selectively increase the potential at the FD node of each of the pixel cells of the second group by selectively asserting a FD boost signal on the supplemental capacitance node line. | 01-10-2013 |
20130032921 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH STRESSED FILM - An image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident through a first side of the image sensor to collect an image charge. The stress adjusting layer is disposed over the first side of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region. | 02-07-2013 |
20130033627 | COLOR FILTER PATTERNING USING HARD MASK - Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed. | 02-07-2013 |
20130033629 | IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION - An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array. | 02-07-2013 |
20130056808 | Isolation Area Between Semiconductor Devices Having Additional Active Area - An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel. | 03-07-2013 |
20130063641 | DUAL-SIDED IMAGE SENSOR - An apparatus for a dual-sided image sensor is described. The dual-sided image sensor captures frontside image data incident upon a frontside of the dual-sided image sensor within an array of photosensitive regions integrated into a semiconductor layer of the dual-sided image sensor. Backside image data incident upon a backside of the dual-sided image sensor is also captured within the same array of photosensitive regions. | 03-14-2013 |
20130069188 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 03-21-2013 |
20130082163 | IMAGE SENSOR WITH MICRO-LENS COATING - Techniques and architectures for providing a coating for one or more micro-lenses of a pixel array. In an embodiment, a pixel element includes a micro-lens and a coating portion extending over a surface of the micro-lens, where a profile of the coating portion is super-conformal to, or at least conformal to, a profile of the micro-lens. In another embodiment, the coating portion is formed at least in part by orienting the surface of the micro-lens to face generally downward with the direction of gravity, the orienting to allow a fluid coating material to flow for formation of the coating portion. | 04-04-2013 |
20130083223 | IMAGE SENSOR WITH DUAL ELEMENT COLOR FILTER ARRAY AND THREE CHANNEL COLOR OUTPUT - A color image sensor includes a pixel array including CFA overlaying an array of photo-sensors for acquiring color image data. The CFA includes first color filter elements of a first color overlaying a first group of the photo-sensors and second color filter elements of a second color overlaying a second group of the photo-sensors. The first group of photo-sensors generate first color signals of a first color channel and the second group of photo-sensors generate second color signals of a second color channel. The color image sensor further includes a color signal combiner circuit (“CSCC”) coupled to receive the first and second color signals output from the pixel array. The CSCC includes a combiner coupled to combine the first and second colors signals to generate third color signals of a third color channel. An output port is coupled to the CSCC to output the color image data. | 04-04-2013 |
20130083224 | IMAGE SENSOR WITH DUAL ELEMENT COLOR FILTER ARRAY AND THREE CHANNEL COLOR OUTPUT - A color image sensor includes a pixel array including a CFA overlaying an array of photo-sensors for acquiring a color image. The CFA includes first color filter elements of a first color overlaying a first group of the photo-sensors, second color filter elements of a second color overlaying a second group of the photo-sensors, and a plurality of filter stacks overlaying a third group of the photo-sensors. The first group generates first color signals of a first color channel and the second group generates second color signals of a second color channel. Each of the filter stacks includes a first stacked filter of the first color and a second stacked filter of the second color. A sensitivity of the filter stacks equals a product of sensitivities of the first and the second stacked filters and the filter stacks generate a third color channel. | 04-04-2013 |
20130092982 | PARTIAL BURIED CHANNEL TRANSFER DEVICE FOR IMAGE SENSORS - Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate. | 04-18-2013 |
20130113065 | PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via. | 05-09-2013 |
20130122637 | SEAL RING SUPPORT FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring. | 05-16-2013 |
20130200396 | PREVENTION OF LIGHT LEAKAGE IN BACKSIDE ILLUMINATED IMAGING SENSORS - An apparatus includes a semiconductor layer, a dielectric layer, and a light prevention structure. The semiconductor layer has a front surface and a backside surface. The semiconductor layer includes a light sensing element and a periphery circuit region containing a light emitting element and not containing the light sensing element. The dielectric layer contacts at least a portion of the backside surface of the semiconductor layer. At least a portion of the light prevention structure is disposed between the light sensing element and the light emitting element. The light prevention structure is positioned to prevent light emitted by the light emitting element from reaching the light sensing element. | 08-08-2013 |
20130207212 | LATERAL LIGHT SHIELD IN BACKSIDE ILLUMINATED IMAGING SENSORS - A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. The trench is positioned to impede a light path between the light emitting element and the light sensing element when the light path is internal to the semiconductor layer. | 08-15-2013 |
20130217173 | METHODS OF FORMING VARYING DEPTH TRENCHES IN SEMICONDUCTOR DEVICES - A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench. | 08-22-2013 |
20130256822 | METHOD AND DEVICE WITH ENHANCED ION DOPING - Techniques for providing a pixel cell which exhibits improved doping in a semiconductor substrate. In an embodiment, a first doping is performed through a backside of the semiconductor substrate. After the first doping, the semiconductor substrate is thinned to expose a front side which is opposite of the backside. In another embodiment, a second doping is performed through the exposed front side of the thinned semiconductor substrate to form at least part of a pixel cell structure. | 10-03-2013 |
20130258144 | SYSTEM, APPARATUS AND METHOD FOR DARK CURRENT CORRECTION - Embodiments of the invention describe a system, apparatus and method for obtaining black reference pixels for dark current correction processing are described herein. Embodiments of the invention capture image signal data via a plurality of pixel cells of a pixel unit of an image device, wherein capturing image signal data involves establishing a first state of exposing incident light on each pixel of the pixel unit and a second state of shielding incident light from one or more pixels of the pixel unit via a shutter unit disposed over the pixel unit. Image signal data from each pixel of the pixel unit captured during the first state and the second state is read, and scene image data is created by combining a subset of image signal data captured during the first state with a dark current component including a subset of image signal data captured during the second state. | 10-03-2013 |
20130264688 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer. | 10-10-2013 |
20130285183 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 10-31-2013 |
20130292751 | IMAGE SENSOR WITH SEGMENTED ETCH STOP LAYER - An apparatus includes a semiconductor layer having an array of pixels arranged therein. A passivation layer is disposed proximate to the semiconductor layer over the array of pixels. A segmented etch stop layer including a plurality of etch stop layer segments is disposed proximate to the passivation layer over the array of pixels. Boundaries between each one of the plurality of etch stop layer segments are aligned with boundaries between pixels in the array of pixels. | 11-07-2013 |
20140014813 | INTEGRATED CIRCUIT STACK WITH INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELDING - An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface. | 01-16-2014 |
20140048897 | PIXEL WITH NEGATIVELY-CHARGED SHALLOW TRENCH ISOLATION (STI) LINER - Embodiments of a pixel including a substrate having a front surface and a photosensitive region formed in or near the front surface of the substrate. An isolation trench is formed in the front surface of the substrate adjacent to the photosensitive region. The isolation trench includes a trench having a bottom and sidewalls, a passivation layer formed on the bottom and the sidewalls, and a filler to fill the portion of the trench not filled by the passivation layer. | 02-20-2014 |
20140084135 | Backside-Illuminated Photosensor Array With White, Yellow ad Red-Sensitive Elements - A monolithic backside-sensor-illumination (BSI) image sensor has a sensor array is tiled with a multiple-pixel cells having a first pixel sensor primarily sensitive to red light, a second pixel sensor primarily sensitive to red and green light, and a third pixel sensor having panchromatic sensitivity, the pixel sensors laterally adjacent each other. The image sensor determines a red, a green, and a blue signal comprising by reading the red-sensitive pixel sensor of each multiple-pixel cell to determine the red signal, reading the sensor primarily sensitive to red and green light to determine a yellow signal and subtracting the red signal to determine a green signal. The image sensor reads the panchromatic-sensitive pixel sensor to determine a white signal and subtracts the yellow signal to provide the blue signal. | 03-27-2014 |
20140103189 | Compact In-Pixel High Dynamic Range Imaging - Embodiments of the invention describe providing a compact solution to provide high dynamic range imaging (HDRI or simply HDR) for an imaging pixel by utilizing a control node for resetting a floating diffusion node to a reference voltage value and for selectively transferring an image charge from a photosensitive element to a readout node. Embodiments of the invention further describe control node to have to a plurality of different capacitance regions to selectively increase the overall capacitance of the floating diffusion node. This variable capacitance of the floating diffusion node increases the dynamic range of the imaging pixel, thereby providing HDR for the host imaging system, as well as increasing the signal-to-noise ratio (SNR) of the imaging system. | 04-17-2014 |
20140103410 | PARTIAL BURIED CHANNEL TRANSFER DEVICE IN IMAGE SENSORS - An image sensor pixel includes a photosensitive element, a floating diffusion (“FD”) region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The FD region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region. The transfer device includes a gate, a buried channel dopant region and a surface channel region. The gate is disposed between the photosensitive element and the FD region. The buried channel dopant region is disposed adjacent to the FD region and underneath the gate. The surface channel region is disposed between the buried channel dopant region and the photosensitive element and disposed underneath the gate. | 04-17-2014 |
20140124889 | DIE SEAL RING FOR INTEGRATED CIRCUIT SYSTEM WITH STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer. | 05-08-2014 |
20140210028 | COLOR FILTER INCLUDING CLEAR PIXEL AND HARD MASK - Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed. | 07-31-2014 |
20140231622 | CIRCUIT STRUCTURE FOR PROVIDING CONVERSION GAIN OF A PIXEL ARRAY - Techniques and mechanisms for a pixel array to provide a level of conversion gain. In an embodiment, the pixel array includes conversion gain control circuitry to be selectively configured at different times for different operational modes, each mode for implementing a respective conversion gain. The conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—a supply voltage. In another embodiment, the conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—sample and hold circuitry. | 08-21-2014 |
20140239152 | IMAGE SENSOR WITH PIXEL UNITS HAVING MIRRORED TRANSISTOR LAYOUT - An image sensor includes a first pixel unit horizontally adjacent to a second pixel unit. Each pixel unit includes plurality of photodiodes and a shared floating diffusion region. A first pixel transistor region of the first pixel unit has a plurality of pixel transistors. A second pixel transistor region of the second pixel unit is horizontally adjacent to the first pixel transistor region and also has a plurality of pixel transistors. A transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region. | 08-28-2014 |
20140239154 | HIGH DYNAMIC RANGE PIXEL HAVING A PLURALITY OF AMPLIFIER TRANSISTORS - A pixel cell for use in a high dynamic range image sensor includes a photodiode disposed in semiconductor material to accumulate charge in response to light incident upon the photodiode. A transfer transistor is disposed in the semiconductor material and is coupled between a floating diffusion and the photodiode. A first amplifier transistor is disposed in the semiconductor material having a gate terminal coupled to the floating diffusion and a source terminal coupled to generate a first output signal of the pixel cell. A second amplifier transistor is disposed in the semiconductor material having a gate terminal coupled to the floating diffusion and a source terminal coupled to generate a second output signal of the pixel cell. | 08-28-2014 |
20140239351 | PROCESS TO ELIMINATE LAG IN PIXELS HAVING A PLASMA-DOPED PINNING LAYER - Embodiments of a process including depositing a sacrificial layer on the surface of a substrate over a photosensitive region, over the top surface of a transfer gate, and over at least the sidewall of the transfer gate closest to the photosensitive region, the sacrificial layer having a selected thickness. A layer of photoresist is deposited over the sacrificial layer, which is patterned and etched to expose the surface of the substrate over the photosensitive region and at least part of the transfer gate top surface, leaving a sacrificial spacer on the sidewall of the transfer gate closest to the photosensitive region. The substrate is plasma doped to form a pinning layer between the photosensitive region and the surface of the substrate. The spacing between the pinning layer and the sidewall of the transfer gate substantially corresponds to a thickness of the sacrificial spacer. Other embodiments are disclosed and claimed. | 08-28-2014 |
20140246561 | HIGH DYNAMIC RANGE PIXEL HAVING A PLURALITY OF PHOTODIODES WITH A SINGLE IMPLANT - A high dynamic range image sensor pixel includes a short integration photodiode and a long integration photodiode disposed in semiconductor material. The long integration photodiode has a light exposure area that is substantially larger than a light exposure area of the short integration photodiode. The light exposure area of the short integration photodiode has a first doping concentration from a first doping implantation. The light exposure area of the long integration photodiode includes at least one implanted portion having the first doping concentration from the first doping implantation. The light exposure area of the long integration photodiode further includes at least one non-implanted portion photomasked from the first doping implantation such that a combined doping concentration of the implanted and non-implanted portions of the light exposure area of the long integration photodiode is less than the first doping concentration of the light exposure area of the short integration photodiode. | 09-04-2014 |
20140299956 | LAYERS FOR INCREASING PERFORMANCE IN IMAGE SENSORS - An imaging device includes a semiconductor substrate having a photosensitive element for accumulating charge in response to incident image light. The semiconductor substrate includes a light-receiving surface positioned to receive the image light. The imaging device also includes a negative charge layer and a charge sinking layer. The negative charge layer is disposed proximate to the light-receiving surface of the semiconductor substrate to induce holes in an accumulation zone in the semiconductor substrate along the light-receiving surface. The charge sinking layer is disposed proximate to the negative charge layer and is configured to conserve or increase an amount of negative charge in the negative charge layer. The negative charge layer is disposed between the semiconductor substrate and the charge sinking layer. | 10-09-2014 |
20140299957 | IMAGE SENSOR HAVING METAL CONTACT COUPLED THROUGH A CONTACT ETCH STOP LAYER WITH AN ISOLATION REGION - An image sensor pixel includes one or more photodiodes disposed in a semiconductor layer. Pixel circuitry is disposed in the semiconductor layer coupled to the one or more photodiodes. A passivation layer is disposed proximate to the semiconductor layer over the pixel circuitry and the one or more photodiodes. A contact etch stop layer is disposed over the passivation layer. One or more metal contacts are coupled to the pixel circuitry through the contact etch stop layer. One or more isolation regions are defined in the contact etch stop layer that isolate contact etch stop layer material through which the one or more metal contacts are coupled are coupled to the pixel circuitry from the one or more photodiodes. | 10-09-2014 |
20140306360 | METHOD OF FORMING DUAL SIZE MICROLENSES FOR IMAGE SENSORS - A method of forming microlenses for an image sensor having at least one large-area pixel and at least one small-area pixel is disclosed. The method includes forming a uniform layer of microlens material on a light incident side of the image sensor over the large-area pixel and over the small-area pixel. The method also includes forming the layer of microlens material into a first block disposed over the large-area pixel and into a second block disposed over the small-area pixel. A void is also formed in the second block to reduce a volume of microlens material included in the second block. The first and second blocks are then reflowed to form a respective first microlens and second microlens. The first microlens has substantially the same effective focal length as the second microlens. | 10-16-2014 |
20140346572 | IMAGE SENSOR PIXEL CELL WITH GLOBAL SHUTTER HAVING NARROW SPACING BETWEEN GATES - A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively. | 11-27-2014 |
20150048427 | IMAGE SENSOR PIXEL CELL WITH SWITCHED DEEP TRENCH ISOLATION STRUCTURE - A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion. | 02-19-2015 |
20150054106 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 02-26-2015 |
20150091119 | COLOR FILTER INCLUDING CLEAR PIXEL AND HARD MASK - Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed. | 04-02-2015 |
20150349004 | DIE SEAL RING FOR INTEGRATED CIRCUIT SYSTEM WITH STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer. | 12-03-2015 |
Hsin-Chih Tai, Cupetino, CA US
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20090302409 | IMAGE SENSOR WITH MULTIPLE THICKNESS ANTI-RELFECTIVE COATING LAYERS - An image sensor includes a substrate having a surface at which incident light is received. A pixel array is formed over and within the substrate. The pixel array includes a first and a second pixel arranged to receive light of different colors. The first pixel includes a photosensitive region formed in the substrate and has a first anti-reflective coating (ARC) layer formed over the photosensitive region. The first ARC layer has a first thickness that produces destructive interference above the first ARC layer in response to the incident light. The second pixel includes a photosensitive region formed in the substrate, and a second ARC layer formed over the photosensitive region that produces destructive interference above the second ARC layer in response to the incident light. | 12-10-2009 |
Hsin-Chih Dyson Tai, Cupertino, CA US
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20090002528 | HIGH DYNAMIC RANGE SENSOR WITH BLOOMING DRAIN - An image sensor has at least two photodiodes in each unit pixel. A high dynamic range is achieved by selecting different exposure times for the photodiodes. Additionally, blooming is reduced. The readout timing cycle is chosen so that the short exposure time photodiodes act as drains for excess charge overflowing from the long exposure time photodiodes. To improve draining of excess charge, the arrangement of photodiodes may be further selected so that long exposure time photodiodes are neighbored along vertical and horizontal directions by short exposure time photodiodes. A micro-lens array may also be provided in which light is preferentially coupled to the long exposure time photodiodes to improve sensitivity. | 01-01-2009 |
Hung-Shou Tai, San Mateo, CA US
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20160048727 | METHOD AND SYSTEM FOR RECOGNIZING AN OBJECT - A method, a system, and a non-transitory computer readable medium for recognizing an object are disclosed, the method including: emitting an array of infrared rays from an infrared emitter towards a projection region, the projection region including a first object; generating a reference infrared image by recording an intensity of ray reflection from the projection region without the first object; generating a target infrared image by recording the intensity of ray reflection from the projection region with the first object; comparing the target infrared image to the reference infrared image to generate a predetermined intensity threshold; and extracting the first object from the target infrared image, if the intensity of ray reflection of the target infrared image of the first object exceeds the predetermined intensity threshold. | 02-18-2016 |
Hwan-Ching Tai, Pasadena, CA US
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20080312424 | METHOD AND COMPOSITIONS FOR THE DETECTION OF PROTEIN GLYCOSYLATION - The invention provides methods and compositions for the rapid and sensitive detection of post-translationally modified proteins, and particularly of those with post-translational glycosylations. The methods can be used to detect O-GlcNAc posttranslational modifications on proteins on which such modifications were undetectable using other techniques. In one embodiment, the method exploits the ability of an engineered mutant of β-1,4-galactosyltransferase to selectively transfer an unnatural ketone functionality onto O-GlcNAc glycosylated proteins. Once transferred, the ketone moiety serves as a versatile handle for the attachment of biotin, thereby enabling detection of the modified protein. The approach permits the rapid visualization of proteins that are at the limits of detection using traditional methods. Further, the preferred embodiments can be used for detection of certain disease states, such as cancer, Alzheimer's disease, neurodegeneration, cardiovascular disease, and diabetes. | 12-18-2008 |
20110217732 | METHOD AND COMPOSITIONS FOR THE DETECTION OF PROTEIN GLYCOSYLATION - The invention provides methods and compositions for the rapid and sensitive detection of post-translationally modified proteins, and particularly of those with post-translational glycosylations. The methods can be used to detect O-GlcNAc posttranslational modifications on proteins on which such modifications were undetectable using other techniques. In one embodiment, the method exploits the ability of an engineered mutant of β-1,4-galactosyltransferase to selectively transfer an unnatural ketone functionality onto O-GlcNAc glycosylated proteins. Once transferred, the ketone moiety serves as a versatile handle for the attachment of biotin, thereby enabling detection of the modified protein. The approach permits the rapid visualization of proteins that are at the limits of detection using traditional methods. Further, the preferred embodiments can be used for detection of certain disease states, such as cancer, Alzheimer's disease, neurodegeneration, cardiovascular disease, and diabetes. | 09-08-2011 |
20130183712 | METHOD AND COMPOSITIONS FOR THE DETECTION OF PROTEIN GLYCOSYLATION - The invention provides methods and compositions for the rapid and sensitive detection of post-translationally modified proteins, and particularly of those with posttranslational glycosylations. The methods can be used to detect O-GlcNAc posttranslational modifications on proteins on which such modifications were undetectable using other techniques. In one embodiment, the method exploits the ability of an engine˜red mutant of β-1,4-galactosyltransferase to selectively transfer an unnatural ketone functionality onto O-GlcNAc glycosylated proteins. Once transferred, the ketone moiety serves as a versatile handle for the attachment of biotin, thereby enabling detection of the modified protein. The approach permits the rapid visualization of proteins that are at the limits of detection using traditional methods. Further, the preferred embodiments can be used for detection of certain disease states, such as cancer, Alzheimer's disease, neurodegeneration, cardiovascular disease, and diabetes. | 07-18-2013 |
Hwan-Ching Tai, Pasadene, CA US
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20150344932 | METHOD AND COMPOSITIONS FOR THE DETECTION OF PROTEIN GLYCOSYLATION - The invention provides methods and compositions for the rapid and sensitive detection of post-translationally modified proteins, and particularly of those with posttranslational glycosylations. The methods can be used to detect O-GlcNAc posttranslational modifications on proteins on which such modifications were undetectable using other techniques. In one embodiment, the method exploits the ability of an engine˜red mutant of β-1,4-galactosyltransferase to selectively transfer an unnatural ketone functionality onto O-GlcNAc glycosylated proteins. Once transferred, the ketone moiety serves as a versatile handle for the attachment of biotin, thereby enabling detection of the modified protein. The approach permits the rapid visualization of proteins that are at the limits of detection using traditional methods. Further, the preferred embodiments can be used for detection of certain disease states, such as cancer, Alzheimer's disease, neurodegeneration, cardiovascular disease, and diabetes. | 12-03-2015 |
Jack Han Chin Tai, Irvine, CA US
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20100091712 | WIRELESS COMMUNICATION METHODS UTILIZING A SINGLE ANTENNA WITH MULTIPLE CHANNELS AND THE DEVICES THEREOF - The present invention provides wireless communication methods utilizing a single antenna with multiple channels and the devices thereof. The method includes providing a plurality of communication channels within the single antenna. The plurality of communication channels may include a probe channel and a data channel. The single antenna may selectively switch between the probe channel and the data channel based on a probe signal transmitted in the probe channel so as to facilitate data transmission. | 04-15-2010 |
Jianfeng Tai, Foster City, CA US
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20140172618 | METHOD AND SYSTEM FOR IMPLEMENTING A CRM QUOTE AND ORDER CAPTURE CONTEXT SERVICE - Disclosed is an improved approach for implementing enterprise software systems that addresses the above-described problems with existing systems. The present approach provides an effective and efficient way for defining schemas for services, and to define how to map the schema to particular transactional contexts. | 06-19-2014 |
Joseph Tai, San Diego, CA US
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20090259177 | RESORBABLE HOLLOW DEVICES FOR IMPLANTATION AND DELIVERY OF THERAPEUTIC AGENTS - A method of manufacturing a resorbable balloon designed to contain bone cement for vertebroplasty or kyphoplasty applications is described. The resorbable balloon can be inserted into a vertebral body following vertebral cavitation and filled with bone cement. The balloon remains in place in the vertebral body and resorbs over time. Methods and apparatus are also described for delivering therapeutic agents using collapsible, resorbable balloons. The balloons may be nested and filled with various therapeutic agents that are released over time at rates dependent upon structures and degradation rates of the balloons. Furthermore, the function of the hollow devices can encompass both encapsulation and therapeutic substance delivery roles simultaneously. | 10-15-2009 |
20100065989 | RESORBABLE HOLLOW DEVICES FOR IMPLANTATION AND DELIVERY OF THERAPEUTIC AGENTS - A method of manufacturing a resorbable balloon designed to contain bone cement for vertebroplasty or kyphoplasty applications is described. The resorbable balloon can be inserted into a vertebral body following vertebral cavitation and filled with bone cement. The balloon remains in place in the vertebral body and resorbs over time. Methods and apparatus are also described for delivering therapeutic agents using collapsible, resorbable balloons. The balloons may be nested and filled with various therapeutic agents that are released over time at rates dependent upon structures and degradation rates of the balloons. Furthermore, the function of the hollow devices can encompass both encapsulation and therapeutic substance delivery roles simultaneously. | 03-18-2010 |
Joseph W. Tai, San Diego, CA US
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20100015204 | CELL CARRIER AND CELL CARRIER CONTAINMENT DEVICES CONTAINING REGENERATIVE CELLS - The present invention relates to a device comprising a cell carrier portion containing regenerative cells, e.g. stem and progenitor cells, and a cell carrier containment portion. The device is useful for the treatment of bone related disorders, including spinal fusion related disorders and long bone or flat bone related defects. The device may be used in conjunction with disclosed automated systems and methods for separating and concentrating regenerative cells. | 01-21-2010 |
20130060338 | CELL CARRIER AND CELL CARRIER CONTAINMENT DEVICES CONTAINING REGENERATIVE CELLS - The present invention relates to a device comprising a cell carrier portion containing regenerative cells, e.g., stem and progenitor cells, and a cell carrier containment portion. The device is useful for the treatment of bone related disorders, including spinal fusion related disorders and long bone or flat bone related defects. The device may be used in conjunction with disclosed automated systems and methods for separating and concentrating regenerative cells. | 03-07-2013 |
Kuochou Tai, Fremont, CA US
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20150085513 | LIGHTING ARRANGEMENT - Lighting arrangement ( | 03-26-2015 |
Li-Cheng Tai, San Jose, CA US
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20090100188 | METHOD AND SYSTEM FOR CLUSTER-WIDE PREDICTIVE AND SELECTIVE CACHING IN SCALABLE IPTV SYSTEMS - A method for caching of stream data is accomplished by assigning for each video segment in the system a likelihood rating of future showing and then determining for each node that contains a copy of the segment a second likelihood value that reflecting a probability that the node will be used to serve streams for the segment. The future cost value of a segment copy is then predicted and preload orders are issued to nodes for segments with the per-copy likelihood above a predefined threshold. | 04-16-2009 |
Paul K. Tai, Sunnyvale, CA US
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20100001029 | WHEEL-LESS CARGO CARRIER WITH EXTENDABLE BEAMS - A wheel-less cargo carrier or dolly has multiple telescoping or expandable support beams that can remain attached to a vehicle in a retracted configuration when not in use. For use of the wheel-less cargo carrier, the beams are extended and engaged with a floor, fence, or other structural portion of the wheel-less cargo carrier. Telescoping beams can include multiple rails where smaller rails nest within larger rails and slide relative to the larger rails as the beams are being extended or collapsed. The rails can share a common top surface, so that a base or floor of the wheel-less cargo carrier lies on a flat support structure. | 01-07-2010 |
Philip H. Tai, Cupertino, CA US
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20130227503 | DATA FLOW ANALYZER - A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The method includes providing the schematic design of the integrated circuit, and generating logical slices of the integrated circuit from the schematic design. The method also includes generating, grouping and manipulating macros, responsive to identification of multiple occurrences of logical slices. The method further includes performing data flow analysis to identify data paths for the physical design, quantifying weight indices for the data paths, and positioning objects in the physical design based on the weight indices. | 08-29-2013 |
20160103941 | BUFFER CHAIN MANAGEMENT FOR ALLEVIATING ROUTING CONGESTION - Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains. | 04-14-2016 |
Phillip H. Tai, Mountain View, CA US
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20140189629 | PATTERN-BASED POWER-AND-GROUND (PG) ROUTING AND VIA CREATION - Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules. | 07-03-2014 |
Seng Chin Tai, Sunnyvale, CA US
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20150222020 | TUNABLE ANTENNA STRUCTURE - Example embodiments disclosed herein relate to a tunable antenna structure. A short arm of an antenna structure is coupled to a matching circuit, where the matching circuit is coupled to an input signal. A long arm of the antenna structure is coupled to at least one active tuning element. The short arm is for tuning the antenna structure to a high frequency band and the long arm is for tuning the antenna structure to a low frequency band. | 08-06-2015 |
Sheio-Hsien Tai, Milpitas, CA US
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20100011074 | PUBLICATION OF INFORMATIONAL MESSAGES TO SOFTWARE APPLICATIONS IN A COMPUTING ENVIRONMENT - Systems and methods for publishing information to a plurality of software applications are provided. The methods may comprise identifying a plurality of records to transmit to the software applications based on a last sequential identification code in a high watermark table of a persistent store. The plurality of records may be generated subsequent to a previous record corresponding to the last sequential identification code. A plurality of corresponding messages each corresponding to a record of the plurality of records may be prepared. Each of those messages may then be transmit to at least one software application and may include a most recent message corresponding to a most recent record. In the high water mark table of the persistent store, an updated last sequential identification code may be stored as a pointer for subsequent reference. The updated last sequential identification code may correspond to the most recent message transmitted in the plurality of corresponding messages. | 01-14-2010 |
Stephen Kuong-Io Tai, San Jose, CA US
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20130212622 | INFORMATION INSERTION METHOD AND SYSTEM - An information insertion method and system are provided. The method includes: determining whether an insertion interval starts when a presentation module presents information from a first information source apparatus; when the interval starts, transmitting information from a second information source apparatus, preferably a local apparatus, into the presentation module for presentation; and when the interval ends, stopping transmission of information from the second apparatus into the presentation module, so that the module stops presenting information from the second apparatus and presents information from the first apparatus, thereby preventing the problem caused by channel switching or network congestion resulting in no image on the screen or temporary appearance of a screensaver image. Therefore, the information insertion can be conducted quickly at the beginning of the interval to provide an easy way for the operators to publish information very quickly or provide potential marketing opportunities for businesses to improve economic performance. | 08-15-2013 |
Steve Tak-Shu Tai, Menlo Park, CA US
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20140108903 | METHODS AND SYSTEMS FOR CORPORATE PERFORMANCE MANAGEMENT - A computing module and method for corporate performance management (CPM) is disclosed. A spreadsheet is determined for inclusion in a CPM software application. Dimensional members associated with the spreadsheet are captured, and hierarchies associated with the spreadsheet based on the captured dimensional members and formulas in the spreadsheet are determined. A spreadsheet template associated with the spreadsheet is determined and data from the spreadsheet is obtained. The spreadsheet template, dimensional members, hierarchies, and data are then published into the CPM software application. | 04-17-2014 |
20160098651 | SELF-SERVICE MODEL DESIGNER FOR FEDERATED FINANCIAL PLANNING AND ANALYSIS - A methods and apparatuses for creating a federated multidimensional business planning model may comprise: creating, via a computing device, a first multidimensional business planning model; creating, via a computing device, a second multidimensional business planning model; integrating, via a computing device, the first multidimensional business planning model with the second multidimensional business planning model, wherein the integrating comprises mapping, via a computing device, dimensions of the first multidimensional business planning model to the second multidimensional business planning model, utilizing user input through a model map spreadsheet worksheet defining, via a computing device, at least one source dimension in the first multidimensional business planning model corresponding with at least one target dimension in the second multidimensional business planning model. | 04-07-2016 |
Vincent W.f Tai, San Mateo, CA US
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20120121540 | Certain Nitrogen Containing Bicyclic Chemical Entities For Treating Viral Infections - Provided are certain chemical entities, pharmaceutical compositions, and methods of treatment of a member of the flaviviradae family of viruses such as hepacivirus (Hepatitis C or HCV). | 05-17-2012 |
20130156727 | INDOLE DERIVATIVES AS INHIBITORS OF HISTONE DEACETYLASE - Described herein are compounds and pharmaceutical compositions containing such compounds, which inhibit the activity of histone deacetylase 8 (HDAC8). Also described herein are methods of using such HDAC8 inhibitors, alone and in combination with other compounds, for treating diseases or conditions that would benefit from inhibition of HDAC8 activity. | 06-20-2013 |
20150299119 | INDOLE DERIVATIVES AS INHIBITORS OF HISTONE DEACETYLASE - Described herein are compounds and pharmaceutical compositions containing such compounds, which inhibit the activity of histone deacetylase 8 (HDAC8). Also described herein are methods of using such HDAC8 inhibitors, alone and in combination with other compounds, for treating diseases or conditions that would benefit from inhibition of HDAC8 activity. | 10-22-2015 |
Vincent W-F Tai, San Mateo, CA US
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20090176778 | Certain nitrogen containing bicyclic chemical entities for treating viral infections - Provided are certain chemical entities, pharmaceutical compositions, and methods of treatment of a member of the flaviviradae family of viruses such as hepacivirus (Hepatitis C or HCV). | 07-09-2009 |
20100204265 | Certain Nitrogen Containing Bicyclic Chemical Entities for Treating Viral Infections - Provided are certain chemical entities, pharmaceutical compositions, and methods of treatment of a member of the flaviviradae family of viruses such as hepacivirus (Hepatitis C or HCV). | 08-12-2010 |
Wayming Daniel Tai, Cupertino, CA US
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20110035494 | NETWORK VIRTUALIZATION FOR A VIRTUALIZED SERVER DATA CENTER ENVIRONMENT - A data center includes a physical host machine operating a virtualized entity and a network switch having a physical port connected to the physical host machine. To configure the network switch, the network switch has a management module that acquires information about the virtualized entity operating on the physical host machine. The network switch associates the acquired information about the virtualized entity with the physical port, assigns the virtualized entity to a group associated with a traffic-handling policy, and processes packet traffic from the virtualized entity in accordance with the traffic-handling policy. The virtualized entity can be, for example, a virtual machine or a multi-queue network input/output adapter operating on the physical host machine. | 02-10-2011 |
Wei Chan Tai, Emeryville, CA US
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20100081150 | Methods for Generating Host Cells - The present disclosure provides compositions and methods comprising cells producing glycoproteins with variant glycosylation patterns. The methods and compositions may be used in producing antibodies and proteins of therapeutic value. | 04-01-2010 |
20100081172 | N-Glycans and Uses Thereof - The present disclosure provides compositions and methods comprising cells producing glycoproteins with variant glycosylation patterns. The methods and compositions may be used in producing antibodies and proteins of therapeutic value. | 04-01-2010 |
20100081195 | Modified Host Cells and Uses Thereof - The present disclosure provides compositions and methods comprising cells producing glycoproteins with variant glycosylation patterns. The methods and compositions may be used in producing antibodies and proteins of therapeutic value. | 04-01-2010 |
20100081794 | Modified Glycoproteins and Uses Thereof - The present disclosure provides compositions and methods comprising cells producing glycoproteins with variant glycosylation patterns. The methods and compositions may be used in producing antibodies and proteins of therapeutic value. | 04-01-2010 |
20120107874 | Modified Host Cells and Uses Thereof - The present disclosure provides compositions and methods comprising cells producing glycoproteins with variant glycosylation patterns. The methods and compositions may be used in producing antibodies and proteins of therapeutic value. | 05-03-2012 |
Wen-Tin Tai, Fremont, CA US
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20120314054 | METHOD AND MACHINE FOR EXAMINING WAFERS - Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time. | 12-13-2012 |
Wen-Ting Tai, Fremont, CA US
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20100211202 | METHOD AND MACHINE FOR EXAMINING WAFERS - Method and machine utilizes the real-time recipe to examine a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time. | 08-19-2010 |
William Tai, Irvine, CA US
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20150146364 | SOLID STATE DRIVE (SSD) ASSEMBLY AND AN ASSEMBLY METHOD FOR SSD - A solid state drive (SSD) assembly and an assembly method for solid state drives, which does not require using screws. The assembly method includes aligning a printed circuit board with a first cover and a second cover, the first cover having pre-installed standoffs on an inner surface thereof. The printed circuit board and the second cover respectively having a first set of through-holes, and the first set of through-holes correspond to the standoffs. The assembly method further includes placing the printed circuit board between the first and second covers, thereby exposing an end portion of each of the standoffs in the through-holes of the second cover, and deforming the end portion of each of the standoffs about the through-holes, thereby fastening the first and second covers with one another. | 05-28-2015 |
William P. Tai, Menlo Park, CA US
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20120324004 | SYSTEMS AND METHODS FOR ANALYZING SOCIAL NETWORK USER DATA - One embodiment of a method for analyzing the social network data of one or more users can retrieving from a server data indicative of a user interest profile; determining an initial interest set from the user interest profile using a social graph function; determining a user network influence score including both an influence score for a user and one or more user connections; and generating a final user interest profile in response to an iterative combination of the initial interest set and the user network influence score such that in response to a query, the final user interest profile is returned. Preferably, the preferred method returns the final user interest profile from a central computer to a second computer associated with a third party initiating the query. | 12-20-2012 |
Ying Yu Tai, Mountain View, CA US
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20130117613 | Statistical Read Comparison Signal Generation for Memory Systems - Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition. | 05-09-2013 |
20130117616 | Adaptive Read Comparison Signal Generation for Memory Systems - Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition. | 05-09-2013 |
20130117640 | Soft Information Generation for Memory Systems - Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition. | 05-09-2013 |
20150301887 | HIGH-SPEED MULTI-BLOCK-ROW LAYERED DECODER FOR LOW DENSITY PARITY CHECK (LDPC) CODES - High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed. | 10-22-2015 |
20150301985 | LOW COMPLEXITY PARTIAL PARALLEL ARCHITECTURES FOR FOURIER TRANSFORM AND INVERSE FOURIER TRANSFORM OVER SUBFIELDS OF A FINITE FIELD - Low complexity partial parallel architectures for performing a Fourier transform and an inverse Fourier transform over subfields of a finite field are described. For example, circuits to perform the Fourier transforms and the inverse Fourier transform as described herein may have architectures that have simplified multipliers and/or computational units as compared to traditional Fourier transform circuits and traditional inverse Fourier transform circuits that have partial parallel designs. In a particular embodiment, a method includes, in a data storage device including a controller and a non-volatile memory, the controller includes an inverse Fourier transform circuit having a first number of inputs coupled to multipliers, receiving elements of an input vector and providing the elements to the multipliers. The multipliers are configured to perform calculations associated with an inverse Fourier transform operation. The first number is less than a number of inverse Fourier transform results corresponding to the inverse Fourier transform operation. | 10-22-2015 |
20150381204 | ENCODER WITH TRANSFORM ARCHITECTURE FOR LDPC CODES OVER SUBFIELDS USING MESSAGE MAPPING - A low-density parity-check (LDPC) encoder is configured to encode data for storage into a non-volatile memory of a data storage device. The LDPC encoder includes a message mapping circuit configured to receive an input message and to generate a mapped message based on the input message. The LDPC encoder also includes a matrix multiplier circuit configured to multiply the mapped message with columns of a Fourier transform of an LDPC generator matrix to generate at least a portion of a transform of an LDPC codeword. The LDPC encoder is configured to provide the transform of the LDPC codeword to an inverse Fourier transform circuit to generate the LDPC codeword. | 12-31-2015 |
20150381205 | ENCODER FOR QUASI-CYCLIC LOW-DENSITY PARITY-CHECK CODES OVER SUBFIELDS USING FOURIER TRANSFORM - A quasi-cyclic low-density parity-check (QC-LDPC) encoder includes a Fourier transform circuit configured to receive an input message and to generate a transformed message based on the input message. The transformed message includes leading symbols with indices corresponding to leading elements of cyclotomic cosets of a finite field with respect to a subfield. The QC-LDPC encoder further includes a matrix multiplier circuit configured to multiply the leading symbols of the transformed message by leading symbols of a transformed LDPC generator matrix to generate leading symbols of transformed parity symbols associated with an LDPC codeword. The QC-LDPC encoder is configured to provide the leading symbols of the transformed parity symbols to an inverse Fourier transform circuit to generate parity information of the LDPC codeword. | 12-31-2015 |
Yu-Chong Tai, Pasedena, CA US
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20090306585 | IMPLANTABLE PUMPS AND CANNULAS THEREFOR - In various embodiments, an implantable pump includes a cannula. The pump (e.g., the cannula thereof) may include, for example, flow sensors, pressure sensors, filters, and/or other components. | 12-10-2009 |
20090306594 | DRUG-DELIVERY PUMPS AND METHODS OF MANUFACTURE - Embodiments of an implantable electrolytic pump include a drug reservoir, a cannula fluidly coupled to the reservoir, a pumping mechanism for forcing liquid from the reservoir through the cannula, control circuitry for operating the pumping mechanism, and a power source comprising primary and auxiliary batteries in a stacked configuration, only the main battery being operatively coupled to the control circuitry during normal operation, the control circuitry operatively coupling the back-up battery upon detection of an electrical fault. The pump may further include a hermetic enclosure containing the control circuitry and the power source. | 12-10-2009 |
20090306595 | IMPLANTABLE DRUG-DELIVERY DEVICES, AND APPARATUS AND METHODS FOR FILLING THE DEVICES - In various embodiments, a tool is employed in filling a drug-delivery device. The tool may include, for example, a needle that is admitted through a fill port of the drug-delivery device. | 12-10-2009 |
20090311133 | DRUG-DELIVERY PUMPS AND METHODS OF MANUFACTURE - Embodiments of method of manufacturing an implantable pump, including providing an upper layer comprising a dome structure for housing a drug chamber and a cannula in fluid communication with the drug chamber, providing a middle deflection layer adjacent the drug chamber, providing a bottom layer comprising electrolysis electrodes, and bonding the upper layer, middle deflection layer, and bottom layer to form the pump. | 12-17-2009 |
20090312742 | DRUG-DELIVERY PUMPS AND METHODS OF MANUFACTURE - Embodiments of an implantable electrolytic pump include a first expandable diaphragm and a second flexible diaphragm, and first and second chambers each for containing a fluid, wherein the first expandable diaphragm separates the first and second chambers and provides a fluid barrier therebetween, and the second chamber is formed between the first expandable diaphragm and the second flexible diaphragms. The pump may further include electrolysis electrodes within the first chamber for causing generation of a gas therein and to thereby expand the expandable diaphragm so that fluid is forced from the second chamber into a cannula. | 12-17-2009 |
20100004639 | DRUG-DELIVERY PUMPS AND METHODS OF MANUFACTURE - Embodiments of an implantable electrolytic pump include an electrolysis chamber, a drug chamber and an osmosis chamber, the osmosis chamber having a first portion in contact with the drug chamber and a second portion exposed to facilitate contact with a surrounding fluid. The pump further includes a cannula for conducting liquid from the drug chamber and electrolysis electrodes within the electrolysis chamber for causing generation of a gas therein, the electrolysis and drug chambers being in contact such that gas electrolysis within electrolysis chamber forces fluid from the drug chamber into the cannula, contact between the drug chamber and the osmosis chamber permitting fluid admitted into the osmotic chamber from the surrounding fluid to offset volume loss from the drug chamber and prevent buildup of vacuum pressure thereon. | 01-07-2010 |
20120277733 | DRUG-DELIVERY PUMPS AND METHODS OF MANUFACTURE - Embodiments of an implantable electrolytic pump include a first expandable diaphragm and a second flexible diaphragm, and first and second chambers each for containing a fluid, wherein the first expandable diaphragm separates the first and second chambers and provides a fluid barrier therebetween, and the second chamber is formed between the first expandable diaphragm and the second flexible diaphragms. The pump may further include electrolysis electrodes within the first chamber for causing generation of a gas therein and to thereby expand the expandable diaphragm so that fluid is forced from the second chamber into a cannula. | 11-01-2012 |
20120323218 | DRUG-DELIVERY PUMPS AND METHODS OF MANUFACTURE - Embodiments of an implantable electrolytic pump include an electrolysis chamber, a drug chamber and an osmosis chamber, the osmosis chamber having a first portion in contact with the drug chamber and a second portion exposed to facilitate contact with a surrounding fluid. The pump further includes a cannula for conducting liquid from the drug chamber and electrolysis electrodes within the electrolysis chamber for causing generation of a gas therein, the electrolysis and drug chambers being in contact such that gas electrolysis within electrolysis chamber forces fluid from the drug chamber into the cannula, contact between the drug chamber and the osmosis chamber permitting fluid admitted into the osmotic chamber from the surrounding fluid to offset volume loss from the drug chamber and prevent buildup of vacuum pressure thereon. | 12-20-2012 |
Yu Chuan Tai, Pleasanton, CA US
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20130040831 | Predicting Response to Anti-CD40 Therapy in DLBCL Patients - This invention provides methods, compositions, and kits relating to biomarkers whose expression levels are correlated with diffuse large B-cell lymphoma (DLCBL) patients' response to treatment with a CD20 antagonist, such as a CD20 antibody, exemplified by rituximab. The methods, compositions, and kits of the invention can be used to identify DLBCL patients who are likely or not likely, to respond to anti-CD20 treatments. | 02-14-2013 |
20160083787 | DIGITAL PCR FOR NON-INVASIVE PRENATAL TESTING - Techniques are provided for determining settings of a dPCR experiment for the detection of a chromosomal aneuploidy in a plasma sample from a female pregnant with a fetus. Data about the sample, the dPCR process, and a desired accuracy can be used to determine the settings. Such settings can include a minimal input number of control chromosome molecules for the dPCR experiment, a minimal number of control chromosome molecules for a pre-amplification procedure, and a number of PCR cycles in the pre-amplification procedure. These settings can be used to satisfy the accuracy specified by the accuracy data. Thus, the dPCR experiment can be designed to achieve the desired accuracy while reducing cost, e.g., by not using more of a sample than needed and not performing more pre-amplification than needed or performing more manipulations than needed. | 03-24-2016 |