Patent application number | Description | Published |
20140004361 | SUBSTRATE CORES FOR LASER THROUGH HOLE FORMATION | 01-02-2014 |
20140204454 | CONFIGURATION OF ACOUSTO-OPTIC DEFLECTORS FOR LASER BEAM SCANNING - A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second acousto-optic deflector receives the diffracted laser beam. The second acousto-optic deflector diffracts the received diffracted laser beam along a second axis. | 07-24-2014 |
20140299356 | PROTECTIVE FILM WITH DYE MATERIALS FOR LASER ABSORPTION ENHANCEMENT FOR VIA DRILLING - Embodiments of preventing unwanted damage to microelectronic substrates from laser drilling are generally described herein. In some embodiments, the method includes forming a microelectronic substrate, and adding a layer of protective material to dielectric material of the microelectronic substrate. The microelectronic substrate is configured for mounting one or more integrated circuits (ICs) thereon and includes interconnection for a plurality of electronic circuits. The protective material is configured to absorb laser energy applied in laser drilling of the microelectronic substrate. | 10-09-2014 |
20140321091 | PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE - Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed. | 10-30-2014 |
20150028486 | INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE - Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed. | 01-29-2015 |
20150048515 | FABRICATION OF A SUBSTRATE WITH AN EMBEDDED DIE USING PROJECTION PATTERNING AND ASSOCIATED PACKAGE CONFIGURATIONS - Embodiments of the present disclosure are directed towards techniques and configurations for using projection patterning in making an electronic substrate with an embedded die. In one embodiment, a method may include providing a die embedded in dielectric material of a substrate, and projecting a laser beam through a mask with a preconfigured pattern to create a projected mask pattern on a surface of the dielectric material in accordance with the preconfigured pattern. The projected mask pattern may include a via disposed over the die. Other embodiments may be described and/or claimed. | 02-19-2015 |
20150279817 | LASER CAVITY FORMATION FOR EMBEDDED DIES OR COMPONENTS IN SUBSTRATE BUILD-UP LAYERS - An apparatus including a package substrate including a plurality of layers of conductive material, the package substrate including a cavity; and a device in the cavity, wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points of the device. An apparatus including a package substrate comprising a plurality of conductive layers and a silicon bridge die disposed between ones of the plurality of conductive layers and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the silicon bridge die; and a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers. | 10-01-2015 |
20150338718 | ACOUSTO-OPTIC DEFLECTOR WITH MULTIPLE TRANSDUCERS FOR OPTICAL BEAM STEERING - An acousto-optic deflector with multiple acoustic transducers is described that is suitable for use in substrate processing. In one example a method includes transmitting an optic beam through an acousto-optic deflector, applying an acoustic signal with a phase delay across multiple transducers of the acousto-optic deflector to deflect the beam along a first axis by the acousto-optic deflector, and directing the deflected beam onto a workpiece. | 11-26-2015 |
Patent application number | Description | Published |
20140273043 | TRI-COLOR DUAL GLUCOSE AND OXYGEN SENSORS AND METHODS OF PREPARING AND USING THEM - The present disclosure relates to an optical fluorescence sensor comprising a probe for sensing glucose, an intra-reference probe, and a matrix. The present disclosure also relates to an optical fluorescence dual sensor comprising a probe for sensing glucose, a probe for sensing oxygen, an intra-reference probe, and a matrix. The present disclosure additionally relates to methods of preparing these sensors and methods of using them. | 09-18-2014 |
20150126404 | CELLARIUM: THIN-FILM SENSOR WITH MICROARRAY SEAL - A triple sensor structured for simultaneous measurement of glucose, oxygen, and pH. The sensor components are in thin film states such as sensing films or membranes, with a glucose probe associated with emission of radiation in the blue part of the spectrum, an oxygen probe associated with radiation in red portion of the spectrum, and a pH probe—with a green portion of the spectrum. The optical probes are chemically grafted or immobilized in a suitable polymer matrix, alleviating the leaching of the probes from the matrix, improving the thin film sensing stability, and enabling the repeatable use of the same sensing films. | 05-07-2015 |
20150253333 | CELLARIUM: GLUCOSE, PH, AND OXYGEN TRIPLE SENSOR - A triple sensor structured for simultaneous measurement of glucose, oxygen, and pH. The sensor components are in thin film states such as sensing films or membranes, with a glucose probe associated with emission of radiation in the blue part of the spectrum, an oxygen probe associated with radiation in red portion of the spectrum, and a pH probe—with a green portion of the spectrum. The optical probes are chemically grafted or immobilized in a suitable polymer matrix, alleviating the leaching of the probes from the matrix, improving the thin film sensing stability, and enabling the repeatable use of the same sensing films. | 09-10-2015 |
Patent application number | Description | Published |
20090018028 | Self-Assembled Nucleic Acid Nanoarrays and Uses Therefor - The present invention provides self-assembling, finite nucleic acid tiling arrays, and methods for their synthesis and use, which overcome a major hurdle in self-assembled DNA nanostructures, and therefore have numerous potential applications for nanofabrication of complex structures and useful devices, as further disclosed herein. | 01-15-2009 |
20100216658 | Modified Nucleic Acid Nanoarrays and Uses Therefor - The present invention provides finite, addressable, and self-assembling nucleic acid tiling arrays, and methods for their use. | 08-26-2010 |
20110120868 | Nanopore and Carbon Nanotube Based DNA Sequencer and a Serial Recognition Sequencer - The present invention is directed to systems, devices and methods for identifying biopolymers, such as strands of DNA, as they pass through a constriction such as a carbon nanotube nanopore. More particularly, the invention is directed to such systems, devices and methods in which a newly translocated portion of the biopolymer forms a temporary electrical circuit between the nanotube nanopore and a second electrode, which may also be a nanotube. Further, the invention is directed to such systems, devices and methods in which the constriction is provided with a functionalized unit which, together with a newly translocated portion of the biopolymer, forms a temporary electrical circuit that can be used to characterize that portion of the biopolymer. | 05-26-2011 |
20110168562 | Nanopore and Carbon Nanotube Based DNA Sequencer - The present invention provides a device for analyzing the composition of a heteropolymer comprising a carbon nanotube through which the heteropolymer is driven by electrophoresis. The carbon nanotube also serves as one electrode in a reading circuit. One end of the carbon nanotube is held in close proximity to a second electrode, and each end of the carbon nanotube is functionalized with flexibly-tethered chemical-recognition moieties, such that one will bind one site on the emerging polymer, and the second will bind another site in close proximity, generating an electrical signal between the two electrodes when the circuit is completed by the process of chemical recognition. | 07-14-2011 |
20120288948 | CONTROLLED TUNNEL GAP DEVICE FOR SEQUENCING POLYMERS - The invention includes compositions, devices, and methods for analyzing a polymer and/or polymer unit. The polymer may be a homo- or hetero-polymer such as DNA, RNA, a polysaccharide, or a peptide. The device includes electrodes that form a tunnel gap through which the polymer can pass. The electrodes are functionalized with a reagent attached thereto, and the reagent is capable of forming a transient bond to a polymer unit. When the transient bond forms between the reagent and the unit, a detectable signal is generated and used to analyze the polymer. | 11-15-2012 |
20130186757 | Nanopore and Carbon Nanotube Based Dna Sequencer and A Serial Recognition Elements - The present invention is directed to systems, devices and methods for identifying biopolymers, such as strands of DNA, as they pass through a constriction such as a carbon nanotube nanopore. More particularly, the invention is directed to such systems, devices and methods in which a newly translocated portion of the biopolymer forms a temporary electrical circuit between the nanotube nanopore and a second electrode, which may also be a nanotube. Further, the invention is directed to such systems, devices and methods in which the constriction is provided with a functionalized unit which, together with a newly translocated portion of the biopolymer, forms a temporary electrical circuit that can be used to characterize that portion of the biopolymer. | 07-25-2013 |
20130302901 | Electrodes for Sensing Chemical Composition - Some embodiments of the present disclosure provide methods, devices, and systems for sequencing nucleic acid polymers that utilize palladium (Pd), for example, at least in part, as an electrode material that is (i) functionalized with one or more adaptor molecules and (ii) capable for use to sense one or more chemical compositions. | 11-14-2013 |
20150144506 | SYSTEM, METHOD AND DEVICE FOR ANALYSIS OF CARBOHYDRATES - Embodiments of the present disclosure are directed to recognition tunneling methods, systems and devices for the detection of carbohydrates by measuring tunneling currents of sugars which give distinct electronic signals in a tunnel gap functionalized respectively with, for example, in some embodiments, 4(5)-(2-mercaptoethyl)-1H imideazole-2-carboxamide and 4-mercaptophenylboronic acid molecules on at least one, and preferably each electrode. | 05-28-2015 |
20150211059 | TRANS-BASE TUNNEL READER FOR SEQUENCING - The present invention is directed to systems, devices and methods for identifying biopolymers, such as strands of DNA, as they pass through a constriction such as a carbon nanotube nanopore. More particularly, the invention is directed to such systems, devices and methods in which a newly translocated portion of the iopolymer forms a temporary electrical circuit between the nanotube nanopore and a second electrode, which may also be a nanotube. Further, the invention is directed to such systems, devices and methods in which the constriction is provided with a transnaionilized unit which, together with a newly translocated portion of the biopolymer, forms a temporary electrical circuit that can be used to characterize the portion of the biopolymer. | 07-30-2015 |
20160097759 | CONTROLLED TUNNEL GAP DEVICE FOR SEQUENCING POLYMERS - The invention includes compositions, devices, and methods for analyzing a polymer and/or polymer unit. The polymer may be a homo or hetero-polymer such as DNA, RNA, a polysaccharide, or a peptide. The device includes electrodes that form a tunnel gap through which the polymer can pass. The electrodes are functionalized with a reagent attached thereto, and the reagent is capable of forming a transient bond to a polymer unit. When the transient bond forms between the reagent and the unit, a detectable signal is generated and used to analyze the polymer. | 04-07-2016 |
20160108002 | UNIVERSAL READER MOLECULE FOR RECOGNITION TUNNELING - Some embodiments of the present disclosure are directed to a compound 5(6)-mercapto-1H-benzo[d]imidazole-2-carboxamide (“BIA”) which yields enhanced signals for recognition tunneling. Other embodiments are directed toward methods for producing such compounds as well as apparatuses and systems which utilize such compounds for recognition tunneling for molecule identification/sequencing (for example). | 04-21-2016 |
Patent application number | Description | Published |
20130320547 | ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS BUILD-UP LAYER (BBUL) PACKAGE - A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process. | 12-05-2013 |
20140268612 | CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS - Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate. | 09-18-2014 |
20140321087 | INTEGRATED CIRCUIT PACKAGE SUBSTRATE - Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed. | 10-30-2014 |
20140353827 | BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. | 12-04-2014 |
20140353831 | METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES - Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region. | 12-04-2014 |
20140376195 | Methods of forming dual sided coreless package structures with land side capacitor - Methods of forming coreless package structures comprising backside land side capacitors (LSC) and dual sided solder resist are described. Those methods and structures may include forming a nickel coating on a first and second side of a core, forming a conductive plating on the nickel coating, forming building up layers on the conductive plating to form two panels on the core, de-paneling the panels from the core to form two coreless substrates, forming a laminate on the first and second sides of the coreless substrates, and forming an LSC on a backside of the coreless substrates. | 12-25-2014 |
20150028486 | INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE - Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed. | 01-29-2015 |
20150179593 | LOW Z-HEIGHT PACKAGE ASSEMBLY - In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die and one or more of the conductive pads. The package assembly may further include a solder resist layer coupled with the die and the conductive pads, and one or more interconnects positioned at least partially within the solder resist layer and directly coupled with one or more of the conductive pads. | 06-25-2015 |
20150279817 | LASER CAVITY FORMATION FOR EMBEDDED DIES OR COMPONENTS IN SUBSTRATE BUILD-UP LAYERS - An apparatus including a package substrate including a plurality of layers of conductive material, the package substrate including a cavity; and a device in the cavity, wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points of the device. An apparatus including a package substrate comprising a plurality of conductive layers and a silicon bridge die disposed between ones of the plurality of conductive layers and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the silicon bridge die; and a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers. | 10-01-2015 |
20150318236 | INTEGRATED CIRCUIT PACKAGE SUBSTRATE - Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed. | 11-05-2015 |
20150364423 | BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. | 12-17-2015 |
20160104679 | METHODS OF FORMING SUBSTRATE MICROVIAS WITH ANCHOR STRUCTURES - Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region. | 04-14-2016 |
Patent application number | Description | Published |
20100301454 | LATTICE MATCHED MULTI-JUNCTION PHOTOVOLTAIC AND OPTOELECTRONIC DEVICES - The present invention provides semiconductor structures comprising a substrate and at least three III-V and/or II-VI multi junction building blocks, each comprising a p-n junction having at least two alloy layers, formed over the substrate, provided at least one multi-junction building block comprises II-VI alloy layers. Further described are methods for preparing semiconductor structures utilizing a sacrificial or etch-stop ternary III-V alloy layer over an III-V substrate. | 12-02-2010 |
20120073638 | InP-Based Multi-Junction Photovoltaic and Optoelectronic Devices - Lattice-matched II-VI (ZnCdHg)(SeTe) and III-V (InGaAsP) semiconductors grown on InP substrates can be used for preparing multi junction solar cells that can potentially reach efficiencies greater than 40% under one sun. For example, a semiconductor structure can be prepared comprising, an InP substrate; an optional InGaAsP building block formed over the InP substrate; an InP building block formed over either the InGaAsP building block, when present, or the InP substrate and at least one (ZnCdHg)(SeTe) building block formed over the InP building block. | 03-29-2012 |
20120212820 | OPTICAL DIFFRACTION GRATINGS AND METHODS FOR MANUFACTURING SAME - Described herein are diffraction gratings and methods for the manufacture thereof. One method comprises applying a force to a substrate to strain the substrate, disposing a thin film on at least a portion of the substrate, and reducing the force applied to the substrate, thereby causing the thin film to buckle. | 08-23-2012 |
20130193308 | Multiband Photodetector Utilizing Unipolar and Bipolar Devices - Multi-band photodetectors can be formed by series connecting unipolar and, optionally, bipolar semiconductor structures, each having different photodetection bands. Under default mode of operation, the detector with highest resistance and lowest current will be the current limiting device and will be the active photodetector. When the active photodetector is illuminated with strong light in its own detection band it will be optically biased. This active photodetector will no longer be the highest resistance device, and the next photodetector will be the active photodetector. Repeating this operation pattern, allows switching photodetection bands of the multi-band photodetector. The resistances, dark current and photocurrent of the devices should be engineered to have proper switching. Moreover, the illuminating surface, and photodetector placement should be optimized for proper light biasing. The current passing through the device will always be equal to the current of the active photodetector. | 08-01-2013 |
20130278244 | SYSTEMS AND METHODS FOR ELIMINATING MEASUREMENT ARTIFACTS OF EXTERNAL QUANTUM EFFICIENCY OF MULTI-JUNCTION SOLAR CELLS - A pulsed voltage bias method and/or pulsed light bias method may be used to reduce, minimize, and/or eliminate external quantum efficiency measurement artifacts of multi-junction solar cells, for example artifacts caused by the shunt effect. In this manner, multi-junction solar cells may be designed and constructed with improved performance, efficiency, and the like. | 10-24-2013 |
20130301668 | 6.1 ANGSTROM III-V and II-VI SEMICONDUCTOR PLATFORM - Use of semiconductor materials having a lattice constant of within +/−1.6% of 6.1 angstroms facilitates improved semiconductor device performance and new semiconductor structures, for example integration of field-effect devices and optoelectronic devices on a single wafer. High-mobility channels are enabled, improving device performance. | 11-14-2013 |
20140251425 | Heterostructure Si Solar Cells Using Wide-Bandgap Semiconductors - To improve the efficiency of heterostructure silicon photovoltaic devices, II-VI wide bandgap semiconductor layers can replace the TCO/doped amorphous silicon/intrinsic amorphous silicon layers on the front side or on both sides of the silicon bulk layer. For example, photovoltaic devices are described containing a first contact electrode; a first doped II-VI semiconductor layer disposed over the first contact electrode; a doped crystalline silicon layer disposed over the first doped II-VI semiconductor layer; and a second contact electrode disposed over the doped silicon layer, where one of the doped crystalline silicon layer and the first doped II-VI semiconductor layer is n-doped N and the other is p-doped. | 09-11-2014 |
Patent application number | Description | Published |
20120081858 | FLEX CABLE AND METHOD FOR MAKING THE SAME - An assembly of substrate packages interconnected with flex cables. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing detachable inter-package flex cable connection. The flex cable comprises a transmission region that includes a plurality of signal traces and a ground plane. A plurality of solder mask strips are disposed on the plurality of signals traces to provide anchoring for the signal traces. The solder mask strips intersect the signals traces. The exposed signal traces and the ground plane are coated with organic solderability preservative material. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads. | 04-05-2012 |
20140113464 | FLEXIBLE PACKAGE-TO-SOCKET INTERPOSER - A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate. | 04-24-2014 |
20140151875 | CROSSTALK POLARITY REVERSAL AND CANCELLATION THROUGH SUBSTRATE MATERIAL TUNING - Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s). | 06-05-2014 |
20140160707 | NON-UNIFORM SUBSTRATE STACKUP - Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described. | 06-12-2014 |
20140162475 | CONNECTOR ASSEMBLY AND METHOD - Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port. | 06-12-2014 |
20140174808 | REDUCED CAPACITANCE LAND PAD - A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area. | 06-26-2014 |
20140189190 | MECHANISM FOR FACILITATING DYNAMIC CANCELLATION OF SIGNAL CROSSTALK IN DIFFERENTIAL INPUT/OUTPUT CHANNELS - A mechanism is described for facilitating dynamic cancellation of signal crosstalk in input/output differential channels according to one embodiment. A method of embodiments may include detecting crosstalk between a first differential signal channel pair (“differential pair”) and a second differential pair of a plurality of differential pairs at a computing system, and switching polarity relating to the first transmission links of the first differential pair to cancel out the crosstalk with the second differential pair. | 07-03-2014 |
20140268614 | COUPLED VIAS FOR CHANNEL CROSS-TALK REDUCTION - Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board. | 09-18-2014 |
20150214665 | TWO PIECE SHIELDED SOCKET - A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via. | 07-30-2015 |
20150249298 | CONNECTOR ASSEMBLY AND METHOD - Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port. | 09-03-2015 |
20150262916 | FLEXIBLE PACKAGE-TO-SOCKET INTERPOSER - A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate. | 09-17-2015 |
20160104632 | NON-UNIFORM SUBSTRATE STACKUP - Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described. | 04-14-2016 |
Patent application number | Description | Published |
20130265068 | BUILT-IN SELF-TEST METHOD AND STRUCTURE - A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST. | 10-10-2013 |
20130285201 | MIM CAPACITOR FORMATION METHOD AND STRUCTURE - Metal-insulator metal (MIM) capacitors are formed by providing a substrate having a first surface, forming thereon a first electrode having conductive and insulating regions wherein the conductive regions desirably have an area density D | 10-31-2013 |
20130292764 | Semiconductor Device with Drain-End Drift Diminution - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction. | 11-07-2013 |
20130299939 | CHIP IDENTIFICATION PATTERN AND METHOD OF FORMING - Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip. | 11-14-2013 |
20140027849 | LDMOS DEVICE AND METHOD FOR IMPROVED SOA - A lateral-diffused-metal-oxide-semiconductor device having improved safe-operating-area is provided. The LDMOS device includes spaced-apart source and drain, separated by a first insulated gate structure, and spaced-apart source and body contact The spaced-apart source and BC are part of the emitter-base circuit of a parasitic bipolar transistor that can turn on prematurely, thereby degrading the SOA of prior art four-terminal LDMOS devices. Rather than separating the source and BC with a shallow-trench-isolation region as in the prior art, the semiconductor surface in the gap between the spaced-apart source and BC has there-over a second insulated gate structure, with its gate conductor electrically tied to the BC. When biased, the second insulated gate structure couples the source and BC lowering the parasitic resistance in the emitter-base circuit, thereby delaying turn-on of the parasitic transistor and improving the SOA of such 4-T LDMOS devices. | 01-30-2014 |
20140070311 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region. | 03-13-2014 |
20140203358 | SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region. | 07-24-2014 |
20140203410 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 07-24-2014 |
20140209988 | NONVOLATILE MEMORY BITCELL - A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention. | 07-31-2014 |
20140264724 | DEEP TRENCH ISOLATION - An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type. | 09-18-2014 |
20150056751 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 02-26-2015 |
20150097238 | Mergeable Semiconductor Device with Improved Reliability - A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure. | 04-09-2015 |
20150270333 | Semiconductor Device with Peripheral Breakdown Protection - A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type. | 09-24-2015 |
20150325565 | Composite Semiconductor Device with Multiple Threshold Voltages - A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor. | 11-12-2015 |
20150333177 | SEMICONDUCTOR DEVICE WITH COMPOSITE DRIFT REGION AND RELATED FABRICATION METHOD - A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section. | 11-19-2015 |
20150364576 | RELIABILITY IN MERGEABLE SEMICONDUCTOR DEVICES - A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region. | 12-17-2015 |
20160087096 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material. | 03-24-2016 |
Patent application number | Description | Published |
20090294849 | RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices ( | 12-03-2009 |
20130175616 | RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall. | 07-11-2013 |
20150243781 | RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall. | 08-27-2015 |