Patent application number | Description | Published |
20080237712 | SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO - By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake. | 10-02-2008 |
20080268597 | TECHNIQUE FOR ENHANCING DOPANT ACTIVATION BY USING MULTIPLE SEQUENTIAL ADVANCED LASER/FLASH ANNEAL PROCESSES - By performing multiple radiation-based anneal processes on the basis of less critical process parameters, the overall risk for creating anneal-induced damage, such as melting of gate portions, may be substantially avoided while nevertheless the respective degree of dopant activation may be enhanced for each individual anneal process. Consequently, the sheet resistance of advanced transistor devices may be reduced with a decreasing number of sequential anneal processes. | 10-30-2008 |
20090085652 | COMPENSATION OF OPERATING TIME RELATED DEGRADATION OF OPERATING SPEED BY ADAPTING THE SUPPLY VOLTAGE - By controlled increase of the supply voltage of sophisticated integrated circuits, the performance degradation over a lifetime may be significantly reduced. For this purpose, the upper limits of the supply voltage and the thermal design power are taken into consideration when increasing the supply voltage, which may then compensate for a typical performance degradation resulting in a more stable overall performance of integrated circuits. Thus, greatly reduced guard bands for parts classification may be used compared to conventional strategies. | 04-02-2009 |
20090142900 | METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS - By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps. | 06-04-2009 |
20090166618 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 07-02-2009 |
20090166794 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY THERMOCOUPLES DISTRIBUTED IN THE CONTACT STRUCTURE - By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer. | 07-02-2009 |
20090221115 | REDUCTION OF MEMORY INSTABILITY BY LOCAL ADAPTATION OF RE-CRYSTALLIZATION CONDITIONS IN A CACHE AREA OF A SEMICONDUCTOR DEVICE - By appropriately locally controlling the conditions during a re-growth process in a memory region and a speed-critical device region, the creation of dislocation defects may be reduced in the memory region, thereby enhancing overall stability of respective memory cells. On the other hand, enhanced strain levels may be obtained in the speed-critical device region by performing an efficient amorphization process and re-crystallizing amorphized portions, for instance, in the presence of a rigid material to provide a desired high strain level. | 09-03-2009 |
20090294860 | IN SITU FORMED DRAIN AND SOURCE REGIONS IN A SILICON/GERMANIUM CONTAINING TRANSISTOR DEVICE - By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes. | 12-03-2009 |
20090295457 | COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE - Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures. | 12-03-2009 |
20100078691 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 04-01-2010 |
20100081244 | TRANSISTOR DEVICE COMPRISING AN ASYMMETRIC EMBEDDED SEMICONDUCTOR ALLOY - Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process. | 04-01-2010 |
20100090321 | HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS - By providing a high-k dielectric etch stop material as an etch stop layer for patterning an interlayer dielectric material, enhanced performance and higher flexibility may be achieved since, for instance, an increased amount of highly stressed dielectric material may be positioned more closely to the respective transistors due to the reduced thickness of the high-k dielectric etch stop material. | 04-15-2010 |
20100155727 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 06-24-2010 |
20120211810 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 08-23-2012 |
20120223309 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 09-06-2012 |