Patent application number | Description | Published |
20100020255 | LIQUID CRYSTAL PANEL - A liquid crystal panel including a bottom substrate, a top substrate and a liquid crystal layer is provided. The bottom substrate includes a base plate, an active array structure layer, a color filter layer with plural colors and plural transparent pixel electrodes. The active array structure layer includes plural transparent bottom electrodes and plural transistor structures, at least one insulation layer, plural scan lines and plural data lines both formed on the base plate. At least one insulation layer covers the transparent bottom electrodes. The color filter layer is formed on the active array structure layer. The transparent pixel electrodes are formed on the color filter layer. Each transparent pixel electrode partially overlaps the corresponding transparent bottom electrodes so as to form plural storage capacitor structures. The top substrate is substantially parallel to the bottom substrate. The liquid crystal layer is located between the top substrate and the bottom substrate. | 01-28-2010 |
20140085261 | TOUCH PANEL AND TOUCH DISPLAY PANEL - A touch panel including a substrate, a decoration layer and a first touch unit is provided. The decoration layer is disposed on the substrate, wherein the decoration layer has a window, and the location of the decoration layer is defined as a peripheral region. The first touch unit is at least disposed within the window, and the first touch unit has a plurality of electrode pairs. The electrode pairs are disposed on the substrate. Each of the electrode pairs includes a driving electrode and a sensing electrode. The driving electrode and the sensing electrode are separated by a distance, and the distance is between 300 micrometers and 900 micrometers. | 03-27-2014 |
20140346027 | TOUCH PANEL - A touch panel, having a viewing region and a peripheral region adjacent to at least one edge of the viewing region, includes a plurality of first axis electrodes, a plurality of second axis electrodes, and a plurality of first traces. The first axis electrodes are disposed in the viewing region and extend along a first direction. The second axis electrodes are disposed in the viewing region and extend along a second direction. The first direction is not parallel to the second direction. The first traces are at least partially disposed in the viewing region. Each of the first traces is electrically connected to at least one of the first axis electrodes. The first traces extend from the viewing region to the peripheral region. | 11-27-2014 |
Patent application number | Description | Published |
20100020629 | WORD LINE DRIVER CIRCUIT - A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y−1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m. | 01-28-2010 |
20100149901 | WORD LINE DECODER CIRCUIT - A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal. | 06-17-2010 |
Patent application number | Description | Published |
20100080204 | WLAN TRANSCEIVING SYSTEM - A WLAN transceiving system, which comprises: a plurality of antennas; a plurality of receiving circuits, wherein each one of receiving circuits is coupled to one of the antenna to receive a input signal from the antennas; and a plurality of transmitting circuits, for outputting one of an output signal and an amplified output signal, wherein at least one of the transmitting circuit includes a power amplifier and utilizes at least one of the power amplifier to amplify an output signal to generate the amplified output signal, where a number of the power amplifiers is less than a number of the antennas. | 04-01-2010 |
20120314810 | RECEIVER/TRANSMITTER CAPABLE OF SIMULTANEOUSLY RECEIVING/TRANSMITTING DISCONTINUOUS FREQUENCY SIGNALS AND METHOD THEREOF - A receiver/transmitter and related receiving/method capable of simultaneously receiving/transmitting discontinuous frequency band signal components of an input/output signal are provided. Phase swapping on in-phase/quadrature-phase local oscillation differential signals is applied to frequency down-conversion of the input signal or frequency up-conversion of a baseband signal to be outputted to radio domain, and thereby achieve simultaneously receiving discontinuous frequency bands of the input signal and simultaneously sending different baseband signal components on discontinuous frequency bands of the output signal. | 12-13-2012 |
20130278320 | MIXER FOR MIXING INPUT SIGNAL WITH MULTIPLE OSCILLATING SIGNALS HAVING DIFFERENT PHASES AND RELATED MIXING METHOD THEREOF - A mixer includes a transformer and a mixing circuit. The transformer is employed for receiving an input signal to generate a differential output. The mixing circuit is coupled to the transformer, and employed for mixing the differential output with N oscillating signals having different phases to generate a plurality of mixed output signals, wherein N is greater than 2. | 10-24-2013 |
20130307620 | SIGNAL AMPLIFYING CIRCUIT WITH REDUCED OUTPUT SIGNAL NOISE BY INTRODUCING COUPLING EFFECT AND RELATED METHOD THEREOF - A signal amplifying circuit includes: an input stage circuit, arranged to receive an input signal; a first inductive device coupled between the input stage circuit and a first reference voltage; an output stage circuit arranged to generate an output signal according to the input signal; and a second inductive device coupled between the output stage circuit and a second reference voltage, wherein at least a part of a winding of the first inductive element is cross-coupled to at least a part of a winding of the second inductive element. | 11-21-2013 |
20140022018 | AMPLIFIER WITH GAIN CIRCUIT COUPELD TO PRIMARY COIL OF TRANSFORMER - An amplifier includes a transformer and a first stage gain circuit. The transformer includes a primary coil and a secondary coil. The primary coil is utilized for receiving an input signal. The first stage gain circuit has a first input port, which is coupled to the primary coil. The first stage gain circuit is utilized for gaining the input signal so as to generate a first output. | 01-23-2014 |
20140049441 | SIGNAL CONVERTING CIRCUIT CAPABLE OF REDUCING/AVOIDING SIGNAL LEAKAGE AND RELATED SIGNAL CONVERTING METHOD - A signal converting circuit includes: a first switching circuit; a second switching circuit; and a first balance-unbalance circuit (Balun) having a first signal terminal coupled to an antenna, a second signal terminal coupled to the first switching circuit, and a third signal terminal coupled to the second switching circuit; wherein when the first balance-unbalance circuit operates in a first signal converting mode, the first switching circuit and the second switching circuit are arranged to couple the second signal terminal and the third signal terminal, respectively, to a first signal processing circuit, and when the first balance-unbalance circuit does not operate in the first signal converting mode, the first switching circuit and the second switching circuit are arranged to couple the second signal terminal and the third signal terminal, respectively, to a reference voltage. | 02-20-2014 |
Patent application number | Description | Published |
20080254642 | METHOD OF FABRICATING GATE DIELECTRIC LAYER - A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate. | 10-16-2008 |
20080318405 | METHOD OF FABRICATING GATE STRUCTURE - A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure. | 12-25-2008 |
20120202328 | METHOD FOR FABRICATING MOS TRANSISTOR - The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed. | 08-09-2012 |
20120309171 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. | 12-06-2012 |
Patent application number | Description | Published |
20090322659 | LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A liquid crystal display panel including a first substrate, a liquid crystal layer, an alignment layer, a polymer layer, scan lines, data lines, pixel structures, first capacitor bottom electrodes and second capacitor bottom electrodes, and a manufacturing method thereof are provided. Each pixel structure has a first pixel electrode and a second pixel electrode. Each first capacitor bottom electrode is disposed between the first pixel electrode and the first substrate. Each second capacitor bottom electrode disposed between the second pixel electrode and the first substrate includes a first pattern and a plurality of second patterns. The first pattern extends from a first side to an opposite second side of the second pixel electrode. The second patterns connected to the first pattern are disposed on the first side and the second side. The second pattern at least partly overlaps a region between the second pixel electrode and the data line. | 12-31-2009 |
20100240273 | MANUFACTURING METHOD OF LIQUID CRYSTAL DISPLAY PANEL - A method for manufacturing a liquid crystal display panel including the steps is provided. A semi-finished liquid crystal display panel including a first substrate, a second substrate, a liquid crystal layer, an opposing electrode, scan lines, data lines, polymerizable molecules, pixel structures, first capacitor bottom electrodes, and second capacitor bottom electrodes is provided. Each pixel structure has a first pixel electrode and a second pixel electrode, and the blocks of the liquid crystal layer corresponding to the first pixel electrodes and the second pixel electrodes are respectively a plurality of first blocks and a plurality of second blocks. Then, a first voltage difference and a second voltage difference are respectively formed in the first blocks and the second blocks respectively, wherein the first voltage difference is different from the second voltage difference. Accordingly, the polymerizable molecules are polymerized to form the liquid crystal display panel. | 09-23-2010 |
20110157121 | PIXEL ARRAY - A pixel array including a plurality of scan lines, a plurality of data lines, and a plurality of sub-pixels is provided. Each sub-pixel is electrically connected to one of the scan lines and one of the data lines correspondingly. Each sub-pixel arranged in the n | 06-30-2011 |
20120002148 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel including an active device array substrate, an opposite substrate, and a liquid crystal layer is provided. The active device array substrate includes a plurality of pixel electrodes and each of the pixel electrodes includes a plurality of sets of stripe patterns extending along different directions. Each of the stripe patterns has a width of L and a space between two neighboring stripe patterns is S. The opposite substrate is disposed over the active device array substrate. The liquid crystal layer is disposed between the active device array substrate and the opposite substrate. A cell gap between the active device array substrate and the opposite substrate is d, birefringence of the liquid crystal layer is Δn, and dielectric anisotropy of the liquid crystal layer is Δ∈, wherein S, d, Δn, and Δ∈ comply with the inequality: S/|Δ∈|≦2.8×Δn×d. | 01-05-2012 |
20120162591 | PIXEL STRUCTURE - A pixel structure electrically connected to a scan line and a data line is provided. The pixel structure includes an active device and a pixel electrode, wherein the active device is electrically connected to the scan line and the data line, and the pixel electrode is electrically connected to the active device. The pixel electrode has a plurality of strip-shaped slit groups. Each of the strip-shaped slit groups includes a plurality of strip-shaped slits whose extending directions are substantially parallel to each other, and contours of at least parts of the strip-shaped slits are non-isosceles trapezoids. | 06-28-2012 |