Patent application number | Description | Published |
20090187038 | REAGENTS AND METHODS FOR THE BETA-KETO AMIDE SYNTHESIS OF A SYNTHETIC PRECURSOR TO IMMUNOLOGICAL ADJUVANT E6020 - This invention relates to the synthesis for a precursor of E6020, compound 26, via a β-keto amide alcohol intermediate, compound 22. The synthesis reacts compound 22 with compound 25 and the resultant intermediate is oxidized to produce compound 26, the precursor to E6020. Compounds 22 and 25, and their crystalline forms, represent separate embodiments of the invention. The invention also relates to compounds of formulas (3) and (4) and processes for their preparation. | 07-23-2009 |
20100197951 | COMPOUNDS FOR PREPARING IMMUNOLOGICAL ADJUVANT - The present invention provides methods for preparing TLR-4 receptor agonist E6020: | 08-05-2010 |
20110060151 | REAGENTS AND METHODS FOR THE BETA-KETO AMIDE SYNTHESIS OF A SYNTHETIC PRECURSOR TO IMMUNOLOGICAL ADJUVANT E6020 - This invention relates to the synthesis for a precursor of E6020, compound 26, via a β-keto amide alcohol intermediate, compound 22. The synthesis reacts compound 22 with compound 25 and the resultant intermediate is oxidized to produce compound 26, the precursor to E6020. Compounds 22 and 25, and their crystalline forms, represent separate embodiments of the invention. The invention also relates to compounds of formulas (3) and (4) and processes for their preparation. | 03-10-2011 |
20120232298 | COMPOUNDS FOR PREPARING IMMUNOLOGICAL ADJUVANT - The present invention provides methods for preparing TLR-4 receptor agonist E6020: | 09-13-2012 |
20140012011 | COMPOUNDS FOR PREPARING IMMUNOLOGICAL ADJUVANT - The present invention provides methods for preparing TLR-4 receptor agonist E6020: | 01-09-2014 |
20140323739 | COMPOUNDS FOR PREPARING IMMUNOLOGICAL ADJUVANT - The present invention provides methods for preparing TLR-4 receptor agonist E6020: | 10-30-2014 |
Patent application number | Description | Published |
20090008710 | Robust ESD LDMOS Device - A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width. | 01-08-2009 |
20110039387 | Fully Isolated High-Voltage MOS Device - A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub. | 02-17-2011 |
20140231908 | High Voltage Transistor Structure and Method - A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer. | 08-21-2014 |
Patent application number | Description | Published |
20090008711 | Fully Isolated High-Voltage MOS Device - A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub. | 01-08-2009 |
20090020826 | Integrated Schottky Diode and Power MOSFET - A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer. | 01-22-2009 |
20110298045 | SELF-ALIGNED CONTACT FOR TRENCH MOSFET - The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased. | 12-08-2011 |
20120061737 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND PATTERNING MASK UTILIZIED BY THE METHOD - A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode. | 03-15-2012 |
20120273883 | HIGH VOLTAGE DEVICES AND METHODS FOR FORMING THE SAME - A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is disposed over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is disposed over a second well region of a second dopant type. The first thickness is larger than the second thickness. An isolation structure is disposed between the gate dielectric structure and a drain region disposed within the first well region. A gate electrode is disposed over the gate dielectric structure. | 11-01-2012 |
20130277736 | SELF-ALIGNED CONTACT FOR TRENCH MOSFET - A trench metal oxide semiconductor field effect transistor (MOSFET) includes an epitaxial layer over a substrate a first trench in the epitaxial layer and a second trench in the epitaxial layer. A depth of the first trench is different from a depth of the second trench. The trench MOSFET further includes a source region surrounding the self-aligned source contact, wherein the source region is convex-shaped. The trench MOSFET further includes a self-aligned source contact between the first trench and the second trench; wherein the self-aligned source contact is connected to the source region. | 10-24-2013 |
20130292781 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A buck pick-up region adjoins the source feature in the at least one lightly doped region. The buck pick-up region has a second conductivity type. | 11-07-2013 |
20140264588 | Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide - The present disclosure relates to a method of ultra-high voltage UHV device formation which utilizes a composite step oxide as a gate oxide to achieve isolation of the gate and drain-side spacer from the drain region. The thickness of the step gate oxide improves device breakdown voltage, and allows for the drain to be self-aligned to the gate, thus reducing device drift region and improves device on state resistance. The composite isolation layer comprises two or more dielectric layers which are formed through a series of deposition and etch steps including thermal oxidation and chemical vapor deposition. The composite isolation layer may then be etched to form a self-align structure which utilizes the spacers as hard mask to achieve a reduced device pitch relative to some prior art methods. A thicker gate oxide under one or both spacers can improve yield and high temperature operating life of the UHV device. | 09-18-2014 |