Patent application number | Description | Published |
20080237640 | N-FACE HIGH ELECTRON MOBILITY TRANSISTORS WITH LOW BUFFER LEAKAGE AND LOW PARASITIC RESISTANCE - A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed. | 10-02-2008 |
20080258150 | METHOD TO FABRICATE III-N FIELD EFFECT TRANSISTORS USING ION IMPLANTATION WITH REDUCED DOPANT ACTIVATION AND DAMAGE RECOVERY TEMPERATURE - Structures to reduce dopant activation temperatures for ion implantation in III-N transistors, using low aluminum content layers in proximity to the conducting channel, are disclosed. A method to increase the temperature at which structures can be annealed by annealing in an active nitrogen ambient, for example, in NH | 10-23-2008 |
20080277682 | DUAL SURFACE-ROUGHENED N-FACE HIGH-BRIGHTNESS LED - A light emitting diode, comprising a substrate, a buffer layer on the substrate, an active layer on the buffer layer and between an n-type layer and a p-type layer, a tunnel junction adjacent the p-type layer, and n-type contacts to the tunnel junction and the n-type layer, wherein the buffer layer, n-type layer, p-type layer, active region and tunnel junction comprise III-nitride material grown in a nitrogen-face (N-face) orientation. The substrate surface upon which the III-nitride material is deposited is patterned to provide embedded backside roughening. A top surface of the tunnel junction, which also the top surface of the III-nitride material, is roughened. | 11-13-2008 |
20080296617 | METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS - A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor. | 12-04-2008 |
20080296618 | P-GaN/AlGaN/AlN/GaN ENHANCEMENT-MODE FIELD EFFECT TRANSISTOR - An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel. | 12-04-2008 |
20080308813 | HIGH BREAKDOWN ENHANCEMENT MODE GALLIUM NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTORS WITH INTEGRATED SLANT FIELD PLATE - High breakdown enhancement mode gallium nitride (GaN) based high electron mobility transistors (HEMTs) with integrated slant field plates. These HEMTs have an epilayer structure comprised of AlGaN/GaN buffer. Before the formation of the gate electrode, a passivation layer is deposited, and then the opening for the gate is patterned. The passivation layer below the gate is etched using an etch condition that creates a slanted sidewalls. Then, the charge below the channel is removed either by Fluorine-based plasma treatment and/or by a recess etch. The gate metal is deposited with an angled rotation to form a gate structure with an inherent field plate with rounded edges. | 12-18-2008 |
20090085065 | METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL - A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces. | 04-02-2009 |
20090218599 | POLARIZATION-INDUCED BARRIERS FOR N-FACE NITRIDE-BASED ELECTRONICS - A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient. | 09-03-2009 |
20090230411 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 09-17-2009 |
20090246944 | METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GaN, InN, AND AlN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION - Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible. | 10-01-2009 |
20100109018 | METHOD OF FABRICATING SEMI-INSULATING GALLIUM NITRIDE USING AN ALUMINUM GALLIUM NITRIDE BLOCKING LAYER - A method for fabricating a single crystal, high quality, semi-insulating (SI) gallium nitride (GaN) layer using an Al | 05-06-2010 |
20100193911 | IN-SITU DEFECT REDUCTION TECHNIQUES FOR NONPOLAR AND SEMIPOLAR (Al, Ga, In)N - A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiN | 08-05-2010 |
20100224860 | HIGH EFFICIENCY LEDS WITH TUNNEL JUNCTIONS - An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction. | 09-09-2010 |
20110018062 | FABRICATION OF SINGLE OR MULTIPLE GATE FIELD PLATES - A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices. | 01-27-2011 |
20110044364 | STRUCTURE AND METHOD FOR ACHIEVING SELECTIVE ETCHING IN (Ga,Al,In,B)N LASER DIODES - A structure and method that can be used to achieve selective etching in (Ga, Al, In, B) N laser diodes, comprising fabricating (Ga, Al, In, B) N laser diodes with one or more Al-containing etch stop layers. | 02-24-2011 |
20110057198 | TECHNIQUE FOR DEVELOPMENT OF HIGH CURRENT DENSITY HETEROJUNCTION FIELD EFFECT TRANSISTORS BASED ON (10-10)-PLANE GaN BY DELTA-DOPING - A delta (δ)-doped (10-10)-plane GaN transistor is disclosed. Delta doping can achieve a transistor having at least 10 times higher current density than a conventional (10-10)-plane GaN transistor. | 03-10-2011 |
20110108886 | METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. | 05-12-2011 |
20110156572 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 06-30-2011 |
20110169050 | METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS - A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor. | 07-14-2011 |
20110204329 | NON-POLAR (Al,B,In,Ga)N QUANTUM WELL AND HETEROSTRUCTURE MATERIALS AND DEVICES - A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 | 08-25-2011 |
20120068191 | METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. | 03-22-2012 |
20120091467 | IN-SITU DEFECT REDUCTION TECHNIQUES FOR NONPOLAR AND SEMIPOLAR (Al, Ga, In)N - A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiN | 04-19-2012 |
20120104411 | TEXTURED III-V SEMICONDUCTOR - A method for fabricating a III-nitride semiconductor film, comprising depositing or growing a III-nitride semiconductor film in a semiconductor light absorbing or light emitting device structure; and growing a textured or structured surface of the III-nitride nitride semiconductor film in situ with the growing or the deposition of the III-nitride semiconductor film, by controlling the growing of the III-nitride semiconductor film to obtain a texture of the textured surface, or one or more structures of the structured surface, that increase output power of light from the light emitting device, or increase absorption of light in the light absorbing device. | 05-03-2012 |
20120180868 | III-NITRIDE FLIP-CHIP SOLAR CELLS - A III-nitride photovoltaic device structure and method for fabricating the III-nitride photovoltaic device that increases the light collection efficiency of the III-nitride photovoltaic device. The III-nitride photovoltaic device includes one or more III-nitride device layers, and the III-nitride photovoltaic device functions by collecting light that is incident on the back-side of the III-nitride device layers. The III-nitride device layers are grown on a substrate, wherein the III-nitride device layers are exposed when the substrate is removed and the exposed III-nitride device layers are then intentionally roughened to enhance their light collection efficiency. The collection of the incident light via the back-side of the device simplifies the fabrication of the multiple junctions in the device. The III-nitride photovoltaic device may include grid-like contacts, transparent or semi-transparent contacts, or reflective contacts. | 07-19-2012 |
20120193638 | METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH-QUALITY N-FACE GaN, InN, AND AIN AND THEIR ALLOYS BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION - Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible. | 08-02-2012 |
20120205623 | NON-POLAR (Al,B,In,Ga)N QUANTUM WELL AND HETEROSTRUCTURE MATERIALS AND DEVICES - A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 | 08-16-2012 |
20120319127 | CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER - A current aperture vertical electron transistor (CAVET) with ammonia (NH | 12-20-2012 |
20130015760 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension 1. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 01-17-2013 |
20130264540 | FABRICATION OF NONPOLAR INDIUM GALLIUM NITRIDE THIN FILMS, HETEROSTRUCTURES, AND DEVICES BY METALORGANIC CHEMICAL VAPOR DEPOSITION - A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes. | 10-10-2013 |
20130307027 | METHOD FOR HETEROEPITAXIAL GROWTH OF HIGH CHANNEL CONDUCTIVITY AND HIGH BREAKDOWN VOLTAGE NITROGEN POLAR HIGH ELECTRON MOBILITY TRANSISTORS - A method for growing high mobility, high charge Nitrogen polar (N-polar) or Nitrogen face (In, Al, Ga)N/GaN High Electron Mobility Transistors (HEMTs). The method can provide a successful approach to increase the breakdown voltage and reduce the gate leakage of the N-polar HEMTs, which has great potential to improve the N-polar or N-face HEMTs' high frequency and high power performance. | 11-21-2013 |
20140211820 | TECHNIQUE FOR THE GROWTH AND FABRICATION OF SEMIPOLAR (Ga,Al,In,B)N THIN FILMS, HETEROSTRUCTURES, AND DEVICES - A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface. | 07-31-2014 |
20140299900 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension 1. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 10-09-2014 |
20140367698 | METHOD OF CONTROLLING STRESS IN GROUP-III NITRIDE FILMS DEPOSITED ON SUBSTRATES - Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. | 12-18-2014 |
20150076533 | INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES - The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel. | 03-19-2015 |