Patent application number | Description | Published |
20140120711 | METHOD OF FORMING METAL GATE - Provided is a method of forming a metal gate including the following steps. A dielectric layer is formed on a substrate, wherein a gate trench is formed in the dielectric layer and a gate dielectric layer is formed in the gate trench. A first metal layer is formed in the gate trench by applying a AC bias between a target and the substrate during physical vapor deposition. A second metal layer is formed in the gate trench by applying a DC bias between the target and the substrate during physical vapor deposition. | 05-01-2014 |
20140239419 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially. | 08-28-2014 |
20140295634 | MULTI-GATE FIELD-EFFECT TRANSISTOR PROCESS - A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor. | 10-02-2014 |
20140306273 | STRUCTURE OF METAL GATE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer. | 10-16-2014 |
20140346616 | TRANSISTOR AND SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided. | 11-27-2014 |
20140374909 | METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME - A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method. | 12-25-2014 |
20150061042 | METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer. | 03-05-2015 |
Patent application number | Description | Published |
20090092946 | Method of generating a digital supplementary device for dental implant planning - A method of generating a digital supplementary device for dental implantation by: preparing a mouth model based on the internal shape of the oral cavity of the patient; performing a 3D scan to obtain digital model of the mouth model, the digital model of the patient's oral cavity and the digital model of the tooth model; defining the digital models as the “positioning object,” “the reference object” and the “attached positioning object”; obtaining characteristic points after joining the positioning object and the attached positioning object and positioning the positioning object and the reference object based on the characteristic points; and then outputting the attached positioning object with the positioning data obtained after positioning of the attached positioning object. The output thus obtained is the desired digital supplementary device for dental implant planning. | 04-09-2009 |
20090104583 | Method for Designing an Abutment - A method for designing an abutment tooth which mainly comprises the steps of: setting a reference abutment device with a feature on an analog of a mouth model; positioning a digital abutment with the same configuration as the reference abutment device on the analog to obtain the configuration data of the positioning of the digital abutment on the analog; optimally adjusting the digital abutment by using as a reference the configuration digital data without affecting the configuration of the digital abutment and the analog, thus finishing the design of the abutment. | 04-23-2009 |
20090111071 | Method for designing a digital abutment for dental implant - A method for designing a digital abutment for a dental implant includes the steps of: a) implant planning where implant planning is initiated based on digital data obtained from the patient and loaded into a computer system to enable an implant fixture to be implanted at the implant site in the best position, b) establishment of digital reference abutment where a digital reference abutment is established at the implant site and positioned on the implant fixture, c) adjustment of the digital reference abutment where the digital reference abutment has a subgingival part and a supragingival part at the top side of the subgingival part, and the angle between the subgingival part and the supragingival part is adjusted based on the best prosthesis position, and d) finish of digital abutment where the digital reference abutment becomes a digital abutment for placement after the adjustment. | 04-30-2009 |
20100316974 | METHOD OF MAKING A SURGICAL TEMPLATE USED FOR A COMPUTER-GUIDED DENTAL IMPLANT SURGERY - A method of making a surgical template comprises: producing a 3-D geometrical image by a CT scanning performed on a patient's jaw and establishing corresponding implant planning data to obtain a 3-D first digital image, making a positive plaster model of the patient's jaw, scanning the plaster model to obtain a 3-D second digital image, overlapping the second digital image on the first digital image to obtain a computer representation of the plaster model and at least one implant to be mounted according to the implant planning data, drilling the plaster model to form at least one pinhole according to the implant planning data, inserting a pin into the pinhole, producing a negative template body from an assembly of the plaster model and the pin with a thermoplastic dental material so that the negative template body has at least one implant guide hole and constitutes the surgical template. | 12-16-2010 |
20110123954 | Method of designing dental-implant prosthesis - A method of designing a dental-implant prosthesis includes the steps of arranging a referential jig and combining the referential jig into a fixture installed in a patient's oral cavity, the referential jig having at least one feature point, the fixture having a connection interface, the referential jig having an opposite-joint interface; scanning the patient's oral cavity to acquire an oral digital data and a referential-jig digital data having at least one feature-point digital data; selecting one digital dental-implant prosthesis from a prosthetic database in a computer, a digital positioning jig overlapping the digital dental-implant prosthesis for combination with the connection interface, and proceeding with overlapping and localization of the digital positioning jig and the referential jig digital data to combine the referential jig digital data into the connection interface; and adjusting the position, size, and angle of the digital dental-implant prosthesis to acquire the digital dental-implant prosthesis which is most suitable to the patient. | 05-26-2011 |
20110123955 | Method of preparing digital model and artificial tooth applied to dental implant - A method of preparing a digital model and an artificial tooth applied to dental implant includes the steps of a) combining a jig into a fixture in a patient's oral cavity and scanning the patient's oral cavity by an oral scanner to acquire a first oral digital data and saving it in a computer; b) operating the computer to select one of digital prostheses from a prosthetic database in the computer, arranging a digital positioning jig to correspond to the jig in the first oral digital data, and then combining the selected digital prosthesis with the first oral digital data to generate a second oral data; c) generating a digital oral model based on the second oral digital data; and d) creating a solid oral model. | 05-26-2011 |
Patent application number | Description | Published |
20130043693 | HOLDING SUPPORT FOR ELECTRONIC DEVICE - The instant disclosure relates to a holding support for electronic device, which includes a case and a bracket. A bracket compartment is formed on the case and defined by an opening formed on the outer surface of the case. The bracket has a body and at least one finger hole formed thereon for sliding a finger through. The bracket can be retracted in or extended from the bracket compartment by being arranged at a retracted position or extended position, respectively. Therefore, the user can firmly secure the electronic device and prevent from dropping it accidentally. | 02-21-2013 |
20130044454 | ANGLE ADJUSTABLE DEVICE AND ELECTRONIC DISPLAY UNIT USING THE SAME - The instant disclosure relates to an angle adjustable device, which includes: a base having a fixing member disposed thereon, where the fixing member has a fixing surface; a switch mechanism having a locking ring, a first gear, and a second gear, while at least one block protrudes from the inner surface of the locking ring, with the first gear having a contact incline slidingly abutted by the block, where the contact incline is defined with a first end and a second end, where the first gear is received by the locking ring and capable of meshing with the second gear; and a rotator having at least one connecting member connected to the second gear. The instant disclosure also discloses an electronic display unit using the same. | 02-21-2013 |
20150346772 | SUPPORTING STRUCTURE AND DOCKING STATION USING THE SAME - A supporting structure and a docking station using the same are provided. The supporting structure includes an elastic member, a sliding member, a lifting element and a damper. The sliding member having an inclined plane is connected to the elastic member. When the elastic member receives a force, the elastic member forces the sliding member to move along an axis line with the inclined plane facing to the lifting element. The lifting element is arranged over a travel path of the inclined plane and has an abutting portion. When the lifting element receives another force so that the abutting portion abuts against the inclined plane, the sliding member stops moving and the height position of the lifting element is fixed. The damper is mated with the sliding member to slow down the velocity of the sliding member. | 12-03-2015 |
Patent application number | Description | Published |
20130342799 | DRIVEN ELECTRODE STRUCTURE OF IN-PLANE SWITCHING LIQUID CRYSTAL DISPLAY - A driven electrode structure of an in-plane switching liquid crystal display is divided into a plurality of sub-regions, each of the sub-regions includes a plurality of sub-driven electrodes, a plurality of intervals is formed between adjacent sub-driven electrodes, so as each of the sub-regions has the intervals, and at least two of the intervals in the sub-regions are different from one another. By changing the width or shape of each sub-driven electrode, at least two of the intervals in the sub-regions are different from one another, so as the Mura condition of the in-plane switching liquid crystal display can be obscure, so as the Mura defect can be minimized uniformly without being visually recognized by human eyes and further improve the visual defect of the Mura. | 12-26-2013 |
20140127891 | METHOD FOR MANUFACTURING PIXEL STRUCTURE - A method for manufacturing pixel structure is provided. A patterned conductor layer including a gate, a scan line and a conductor pattern is formed on a substrate. A gate insulating layer, a metal oxide material layer and an etching stop material layer are formed on the substrate. Using the patterned conductor layer as mask, a patterned photoresist layer is formed on the etching stop material layer through a back exposure process. Using the patterned photoresist layer as mask, a metal oxide channel layer and an etching stop layer are formed above the gate. A source and a drain are formed on the etching stop layer. A passivation layer is formed on the substrate. A halftone mask is used to form a photosensitive layer on the passivation layer. The metal oxide material layer and the etching stop material layer on the scan line and the conductor pattern are removed. | 05-08-2014 |
20140138123 | CIRCUIT STACK STRUCTURE - A circuit stack structure is provided. The circuit stack structure includes a conductor layer having metal wires arranged at intervals, propping portions respectively disposed in a gap between any two of the neighboring metal wires, and a protective layer covering the metal wires and the propping portions. The propping portions are electrically isolated with the metal wires. With supporting by the propping portions, all regions of a top surface of the protective layer corresponding to one of the propping portions are coplanar with all regions of the top surface of the protective layer corresponding to each of the metal wires. | 05-22-2014 |
Patent application number | Description | Published |
20110127563 | DIE-BONDING METHOD OF LED CHIP AND LED MANUFACTURED BY THE SAME - A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C. | 06-02-2011 |
20110156071 | MULTI-STACK PACKAGE LED - A multi-stack package light emitting diode (LED) includes an LED chip, a first fluorescent powder layer, a first optical bandpass filter layer and a second fluorescent powder layer. The LED chip generates an LED light. The first fluorescent powder layer and the second fluorescent powder layer respectively have a first fluorescent powder and a second fluorescent powder. The first fluorescent powder and the second fluorescent powder are excited by the LED light to respectively generate a first excitation light and a second excitation light. The first optical bandpass filter layer allows the LED light and the first excitation light to pass and reflects the second excitation light. A wavelength of the LED light is shorter than a wavelength of the second excitation light. The wavelength of the second excitation light is shorter than a wavelength of the first excitation light. Therefore, the multi-stack package LED improves a light emission efficiency. | 06-30-2011 |
20120256228 | DIE-BONDED LED - An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics. | 10-11-2012 |
Patent application number | Description | Published |
20130219713 | METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD WITH A MULTILAYER CIRCUIT STRUCTURE - A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented. | 08-29-2013 |
20130224513 | LAMINATE CIRCUIT BOARD WITH A MULTI-LAYER CIRCUIT STRUCTURE - A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface overlaps the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases. | 08-29-2013 |
Patent application number | Description | Published |
20080237562 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSi | 10-02-2008 |
20080251498 | PHASE CHANGE MEMORY DEVICE AND FABRICATIONS THEREOF - A method for forming a memory device is disclosed. A dielectric layer is formed on a substrate. A Sn doped phase change layer is formed on the dielectric layer. A patterned mask layer is formed on the Sn doped phase change layer. The Sn doped phase change layer is etched by an etchant comprising fluorine-based etchant added with chlorine using the patterned mask layer as a mask to pattern the Sn doped phase change layer. An electrode is formed, electrically connecting the patterned Sn doped phase change layer. | 10-16-2008 |
20080311699 | PHASE-CHANGE MEMORY AND FABRICATION METHOD THEREOF - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 12-18-2008 |
20090278546 | SOLAR CELL TESTING APPARATUS - A solar cell testing apparatus including a stage, a movable chuck, a light source and a plurality of probes is provided. The movable chuck is disposed on the stage and capable of carrying a sample sheet to move. The sample sheet has a light incident side, a rear side opposite to the light incident side, and a plurality of electrodes disposed on the rear side. The light source is disposed above the stage and capable of providing testing light to the light incident side of the sample sheet. The probes are located on the rear side of the sample sheet and capable of contacting the electrodes of the sample sheet. The present invention not only can be used to test a substrate type solar cell, but also can be used to test a superstrate type solar cell. | 11-12-2009 |
20100047960 | METHOD OF FABRICATING A PHASE-CHANGE MEMORY - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 02-25-2010 |
20100154882 | SOLAR CELL - A solar cell is provided and includes a front contact, a first conductive type layer, an intrinsic (I) layer, a second conductive type layer, and a back contact. The first conductive type layer is a material layer of low refractive index which has a refractive index lower than 3. The material layer with low refractive index was used to increase light transmittance of the solar cell and decrease reflection which occurs at interfaces in the solar cell, and thus the solar cell has an optimum sunlight utility rate. Therefore, the solar cell has a large short circuit current (Jsc) and high efficiency. | 06-24-2010 |
20100200040 | DEVICE AND METHOD FOR REPAIRING SOLAR CELL MODULE - A device for repairing a solar cell module is described. The solar cell module includes a first solar cell and a second solar cell serially connected to each other. The device for repairing the solar cell module includes a first terminal, a second terminal, and a power supply device. The power supply device applies a biased voltage signal to the solar cells via the first terminal and the second terminal. The biased voltage signal includes a forward biased voltage part and a reversed biased voltage part. The reversed biased voltage part has multiple voltage bands arranged by time, and a voltage value of each voltage band is a fixed value. The voltage value of the earlier-generated voltage band is greater than the voltage value of the later-generated voltage band, and a duration of the reversed biased voltage part is longer than a duration of the forward biased voltage part. | 08-12-2010 |
20140087487 | METHOD FOR REPAIRING SOLAR CELL MODULE - A method for repairing a solar cell module includes the following steps. A solar cell module, which is provided, includes a first and a second solar cell serially connected. A first terminal is electrically connected to a first electrode layer of the first solar cell. A second terminal is electrically connected to a second electrode layer of the second solar cell. A polarity of the first electrode layer is the same as that of the second electrode layer. A biased voltage signal is generated and transmitted to the first solar cell and the second solar cell through the first terminal and the second terminal. The biased voltage signal includes a forward biased voltage part greater than zero and a reversed biased voltage part smaller than zero. The voltage value of the reversed biased voltage part is increasingly decreased in a step-like manner as time goes by. | 03-27-2014 |
Patent application number | Description | Published |
20140354048 | Integrated Lamp with Automatic Emergency Light and Regular Light - An integrated lamp with automatic emergency light and regular light is provided in the present invention. The integrated lamp with automatic emergency light and regular light is coupled to an AC power source, wherein the AC power source includes a first AC terminal and a second AC terminal. The integrated lamp is controlled by a lamp switch, where the lamp switch includes a first terminal and a second terminal, where an indication light circuit is coupled between the first terminal and the second terminal of the lamp switch. The integrated lamp includes an AC detector. The AC detector is coupled between the second terminal of the lamp switch and the second AC terminal. When the lamp switch is turned off, the AC detector determines whether the current state is a power failure state or a normal state according to the electrical current and/or voltage from the indication light circuit to the second AC terminal. | 12-04-2014 |
20150156839 | METHOD AND APPARATUS FOR ADJUSTING COLOR TEMPERATURE OF LUMINANCE OF LAMP - A method and an apparatus for adjusting color temperature or luminance of lamp are provided in the present invention. The lamp at least includes a white light and a warm white light, and the method includes the steps of: providing a control interface circuit, which is configured at the position of the lamp switch on the wall, wherein the control interface circuit receives an AC signal and outputs a phase chopping signal according to a user's operation; asymmetrically cutting the AC signal to obtain the phase chopping signal when the user uses the control interface circuit to adjust a luminance and/or a color temperature. When the lamp receives the phase chopping signal, the method further comprises: determining whether a positive half cycle of the phase chopping signal and/or the negative half cycle of the phase chopping signal is chopped or not; adjusting the luminance of the white light and the warm white light of the lamp according to the on-time of the positive half cycle and the on-time of the negative half cycle of the phase chopping signal, such that the luminance and/or the color temperature is adjusted. | 06-04-2015 |
20150319816 | SINGLE-WIRE DIMMING METHOD - A single-wire dimming method is provided in the present invention. The method is adapted for a lamp with a first color light source and a second color light source. The method includes: providing a dimming control interface, wherein the power voltage is chopped when the dimming control interface is operated; dividing a period of the power voltage into a first phase period, a second phase period and a third phase period; chopping the power voltage at the first phase period when a user adjust the dimming control interface to turn on a first color light; chopping the power voltage at the second phase period when a user adjust the dimming control interface to turn on a second color light; chopping the power voltage at the third phase period when a user adjust the dimming control interface to turn on a mix color light, wherein the mix color light is to combine the first color light and the second color light. | 11-05-2015 |
Patent application number | Description | Published |
20130114883 | APPARATUS FOR EVALUATING VOLUME AND METHOD THEREOF - An apparatus for evaluating a volume of an object and a method thereof are provided. The provided apparatus and the method can precisely evaluate the volume of the object with a single camera, and the required evaluation time is short. Accordingly, shipping companies can utilize the most appropriate container or cargo space for each object to deliver, thereby reducing operation costs and optimizing the transportation fleet. | 05-09-2013 |
20130120550 | EXTENDED DEPTH OF FIELD MICROSCOPE SYSTEM - An extended depth of field microscope system for phase object detection includes an imaging optical module and a phase/intensity converting module. The imaging optical module has an object lens group, in which an axial symmetric phase coding is added, to produce an axial symmetric spherical aberration. A point spread function (PSF) and an image with extended depth of field can be obtained with a predetermined level of similarity. The phase/intensity converting module converts the phase change of the light passing the phase object, into an image light with change of light intensity. | 05-16-2013 |
20130169595 | RANGING APPARATUS, RANGING METHOD, AND INTERACTIVE DISPLAY SYSTEM - A ranging apparatus including an image sensor, an imaging lens, and a processor is provided. The imaging lens is configured to image an object on the image sensor to produce an image signal having at least one image parameter, wherein the at least one image parameter changes with a change of an object distance of the object. The processor is configured to determine the change of the object distance according to a change of the at least one image parameter. A ranging method and an interactive display system are also provided. | 07-04-2013 |
Patent application number | Description | Published |
20100110022 | TOUCH DISPLAY PANEL - A touch display panel including a first substrate, a second substrate and a liquid crystal layer is provided. The first substrate includes sensing areas and a non-sensing area outside the sensing areas. Each sensing area is provided with a first electrode thereon. The second substrate includes main spacers, sensing protrusions, first sub-spacers and second sub-spacers. The main spacers are connected to the non-sensing area. The sensing protrusions are corresponding to the sensing area and respectively have a second electrode. A sensing gap exists between each second electrode and the corresponding first electrode. The first sub-spacers are corresponding to the non-sensing area and respectively keep a first sub-spacer gap from the first substrate. The second sub-spacers are corresponding to the non-sensing area and respectively keep a second sub-spacer gap from the first substrate. The sensing gap is greater than the first sub-spacer gap and less than the second sub-spacer gap. | 05-06-2010 |
20100315362 | TOUCH-SENSING LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY - A touch-sensing liquid crystal display (LCD) panel including an active device array substrate, an opposite substrate, and a liquid crystal layer disposed therebetween is provided. The active device array substrate includes a first substrate, a pixel array, a plurality of touch-sensing pads, and an electric field shielding layer. The pixel array is disposed on the first substrate and includes a plurality of sub-pixels arranged in an array, a plurality of scan lines, and a plurality of data lines. The touch-sensing pads are disposed on the first substrate. The electric field shielding layer is disposed on the pixel array and arranged between sub-pixels adjacent to each other, and the electric field shielding layer includes a pattern. The opposite substrate includes a common electrode and a plurality of touch-sensing protrusions disposed above the touch-sensing pads. Therefore, when the touch-sensing LCD panel is pressed, press mura is substantially eliminated. | 12-16-2010 |
20110134053 | TOUCH DISPLAY PANEL, PIXEL STRUCTURE AND MULTI-SENSING STRUCTURE - A touch display panel which includes a first substrate, a second substrate, at least a multi-sensing structure, a display medium and at least a display controlling device is provided. The multi-sensing structure is disposed between the first substrate and the second substrate, and the multi-sensing structure includes a sensing upper electrode and a plurality of first sensing lower electrodes. The sensing upper electrode is disposed on the second substrate. The first sensing lower electrodes are disposed on the first substrate and electrically connected to each other in serious, wherein a plurality of first sensing gaps are designed between the first sensing lower electrodes and the sensing upper electrode, and the first sensing gaps have different distances. The display medium is sandwiched between the first substrate and the second substrate. The display controlling device is disposed on the first substrate for controlling the display medium. | 06-09-2011 |
20110199316 | SENSOR STRUCTURE AND TOUCH DISPLAY PANEL - A touch display panel including a first substrate and a second substrate is provided. A plurality of sensing units is disposed on the first substrate, and each sensing unit includes a main-sensing pattern and at least one sub-sensing pattern. The at least one sub-sensing pattern is electrically connected to the main-sensing pattern, and the size of the at least one sub-sensing pattern is smaller than the size of the main-sensing pattern. A plurality of sensing electrodes is disposed on the second substrate, and each of the sensing electrodes is disposed corresponding to one of the sensing units on the first substrate. | 08-18-2011 |
20110291094 | DISPLAY PANEL - A display panel including a first substrate, a second substrate opposite to the first substrate and a display medium between the first substrate and the second substrate is provided. The first substrate has a scan line, a data line and an active device electrically connected to the scan line and the data line. The second substrate has a common electrode layer, an insulting layer covering the common electrode layer, a pixel electrode on the insulating layer and a contact structure on the insulating layer. More specifically, the contact structure is electrically connected to the pixel structure and electrically connected to the active device on the first substrate. | 12-01-2011 |
20110309397 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure including a substrate, a color filter layer, a conductive light-shielding layer, a buffer layer, a scan line, a data line, an active device, and a pixel electrode is provided. The substrate has a pixel region. The color filter layer is disposed corresponding to the pixel region. The conductive light-shielding layer is disposed corresponding to the periphery of the pixel region. The buffer layer covers the conductive light-shielding layer and color filter layer. The scan line and the data line are disposed on the buffer layer. The active device is disposed on the buffer layer and electrically connected to the scan line and data line. The pixel electrode is disposed on the buffer layer and electrically connected to the active device, wherein an overlapping area between the pixel electrode and the conductive light-shielding layer constitutes a storage capacitor. A method for manufacturing the pixel structure is also provided. | 12-22-2011 |
20120073124 | METHOD OF FABRICATING TOUCH PANEL - A method of fabricating a touch panel is provided. A substrate having a touch-sensing region and a peripheral region is provided. A touch-sensing circuit layer including first sensing series, second meshed metal sensing pads, and peripheral circuits is formed on the touch-sensing region of the substrate. An insulating layer having first contact windows and second contact windows is formed on the substrate to cover the touch-sensing circuit layer. The first contact windows expose a portion of the second meshed metal sensing pads. A transparent conductive layer including second transparent bridge lines and transparent contact pads is formed on the insulating layer located in the touch-sensing region of the substrate. Each second transparent bridge line is electrically connected to two adjacent second meshed metal sensing pads through two first contact windows. Each transparent contact pad is electrically connected to the corresponding peripheral circuit through the second contact window. | 03-29-2012 |
20130312253 | METHOD OF FABRICATING TOUCH PANEL - A method of fabricating a touch panel is provided. A substrate having a touch-sensing region and a peripheral region is provided. A touch-sensing circuit layer including first sensing series, and second meshed metal sensing pads is formed on the touch-sensing region of the substrate. An insulating layer having first contact windows is formed on the substrate to cover the touch-sensing circuit layer. The first contact windows expose a portion of the second meshed metal sensing pads. A plurality of second transparent bridge lines are formed on the insulating layer located in the touch-sensing region. Each second transparent bridge line is electrically connected to two adjacent second meshed metal sensing pads through two first contact windows. The second transparent bridge lines completely cover the portion of the second meshed metal sensing pads exposed by the first contact windows. | 11-28-2013 |
20130313599 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure including a substrate, a color filter layer, a conductive light-shielding layer, a buffer layer, a scan line, a data line, an active device, and a pixel electrode is provided. The substrate has a pixel region. The color filter layer is disposed corresponding to the pixel region. The conductive light-shielding layer is disposed corresponding to the periphery of the pixel region. The buffer layer covers the conductive light-shielding layer and color filter layer. The scan line and the data line are disposed on the buffer layer. The active device is disposed on the buffer layer and electrically connected to the scan line and data line. The pixel electrode is disposed on the buffer layer and electrically connected to the active device, wherein an overlapping area between the pixel electrode and the conductive light-shielding layer constitutes a storage capacitor. A method for manufacturing the pixel structure is also provided. | 11-28-2013 |
20130313600 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure including a substrate, a color filter layer, a conductive light-shielding layer, a buffer layer, a scan line, a data line, an active device, and a pixel electrode is provided. The substrate has a pixel region. The color filter layer is disposed corresponding to the pixel region. The conductive light-shielding layer is disposed corresponding to the periphery of the pixel region. The buffer layer covers the conductive light-shielding layer and color filter layer. The scan line and the data line are disposed on the buffer layer. The active device is disposed on the buffer layer and electrically connected to the scan line and data line. The pixel electrode is disposed on the buffer layer and electrically connected to the active device, wherein an overlapping area between the pixel electrode and the conductive light-shielding layer constitutes a storage capacitor. A method for manufacturing the pixel structure is also provided. | 11-28-2013 |