Patent application number | Description | Published |
20100073671 | ALIGNMENT MARK AND DEFECT INSPECTION METHOD - A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection. | 03-25-2010 |
20100213554 | GATE STRUCTURE AND METHOD FOR TRIMMING SPACERS - A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer. | 08-26-2010 |
20100327451 | ALIGNMENT MARK - An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region. | 12-30-2010 |
20110006437 | OPENING STRUCTURE - An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings. | 01-13-2011 |
20110143511 | Method of fabricating n-channel metal-oxide semiconductor transistor - A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer. | 06-16-2011 |
20120001338 | OPENING STRUCTURE - An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings. | 01-05-2012 |
20120256273 | METHOD OF UNIFYING DEVICE PERFORMANCE WITHIN DIE - A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped. | 10-11-2012 |
20130234261 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain. | 09-12-2013 |
20150349088 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain. | 12-03-2015 |
Patent application number | Description | Published |
20110007452 | Lamellar Stacked Solid Electrolytic Capacitor - A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit. | 01-13-2011 |
20140259580 | METHOD FOR FABRICATING SOLID ELECTROLYTIC CAPACITORS - The instant disclosure relates to an improved method for the production of solid electrolytic capacitor, comprising the following steps. First, provide an insulating substrate. Next, form a plurality of conducting gels including aluminum powder on the insulating substrate. Thirdly, execute a high-temperature sintering process to metalize the conducting gels to form a plurality of aluminum plates. Next, form a dielectric layer on every aluminum plate. Then form an isolation layer on every dielectric layer to define an anodic region and a cathodic region. Lastly, form a conductive layer on the dielectric layer of every cathodic region, thus defining a solid electrolytic capacitor unit. | 09-18-2014 |
20140262459 | WINDING-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE USING A CARRIER BOARD AND METHOD OF MANUFACTURING THE SAME - A winding-type solid electrolytic capacitor package structure includes a substrate body, a winding capacitor, a package body and an electrode unit. The winding capacitor has a winding body, a positive conductive lead pin having a positive end surface, and a negative conductive lead pin having a negative end surface. The package body is disposed on the substrate body to enclose the winding body, and the package body has a first lateral surface substantially flushed with the positive end surface and a second lateral surface substantially flushed with the negative end surface. The electrode unit includes a positive electrode structure for covering the first lateral surface and electrically contacting the positive end surface and a negative electrode structure for covering the second lateral surface and electrically contacting the negative end surface. | 09-18-2014 |
20140268500 | WINDING-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE USING A LEAD FRAME AND METHOD OF MANUFACTURING THE SAME - A winding-type solid electrolytic capacitor package structure includes a winding capacitor unit, a package body and a conductive unit. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin having a cutting surface, and a negative conductive lead pin having a grinding surface. The conductive unit includes a positive conductive terminal electrically connected to the positive conductive lead pin and a negative conductive terminal electrically connected to the negative conductive lead pin. The positive conductive terminal has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body. The negative conductive terminal has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body. The first and the second exposed portions are extended along the outer surface of the package body. | 09-18-2014 |
20140268503 | WINDING-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE WITHOUT USING A LEAD FRAME AND METHOD OF MANUFACTURING THE SAME - A winding-type solid electrolytic capacitor package structure without using any lead frame includes a winding capacitor and a package body. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin extended from a first lateral side of the winding body, and a negative conductive lead pin extended from a second lateral side of the winding body. The positive conductive lead pin has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body and extended along the first lateral surface and the bottom surface of the package body. The negative conductive lead pin has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body and extended along the second lateral surface and the bottom surface of the package body. | 09-18-2014 |
20150194262 | SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND CONDUCTIVE UNIT - A solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes at least one first conductive terminal and at least one second conductive terminal. The first conductive terminal includes a first core layer and a first enclosing layer. The first core layer has a first top exposed surface exposed from the first enclosing layer, and the first top exposed surface has a first top covering area covered by the package body. The second conductive terminal includes a second core layer and a second enclosing layer. The second core layer has a second top exposed surface exposed from the second enclosing layer, and the second top exposed surface has a second top covering area covered by the package body. | 07-09-2015 |
20150318116 | METHOD FOR FABRICATING SOLID ELECTROLYTIC CAPACITORS - The instant disclosure relates to an improved method for the production of solid electrolytic capacitor, comprising the following steps. First, provide an insulating substrate. Next, form a plurality of conducting gels including aluminum powder on the insulating substrate. Thirdly, execute a high-temperature sintering process to metalize the conducting gels to form a plurality of aluminum plates. Next, form a dielectric layer on every aluminum plate. Then form an isolation layer on every dielectric layer to define an anodic region and a cathodic region. Lastly, form a conductive layer on the dielectric layer of every cathodic region, thus defining a solid electrolytic capacitor unit. | 11-05-2015 |
Patent application number | Description | Published |
20120092810 | INSULATING ENCAPSULATION STRUCTURE FOR SOLID CHIP ELECTROLYTIC CAPACITOR - An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced. | 04-19-2012 |
20140218842 | CAPACITOR CATHODE FOIL STRUCTURE AND MANUFACTURING METHOD THEREOF - The instant disclosure relates to a manufacturing method of capacitor cathode foil structure, comprising the following steps. The first step is providing a base foil, subsequently inserting the foil into a reactor. The next step is executing a heating process for heat the base foil to a temperature region of 400° C. to 1000° C. The next step is directing a carbon containing precursor gas into the reactor. The last step is executing a cooling process for cooling the base foil to a temperature below 100° C. to deposit a graphene-based layer on one surface of the base foil, wherein the graphene-based layer is consisted of a plurality of graphene-based thin films in stacked arrangement. | 08-07-2014 |
20150364262 | METHOD OF MANUFACTURING A WINDING-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE USING A LEAD FRAME - A winding-type solid electrolytic capacitor package structure includes a winding capacitor unit, a package body and a conductive unit. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin having a cutting surface, and a negative conductive lead pin having a grinding surface. The conductive unit includes a positive conductive terminal electrically connected to the positive conductive lead pin and a negative conductive terminal electrically connected to the negative conductive lead pin. The positive conductive terminal has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body. The negative conductive terminal has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body. The first and the second exposed portions are extended along the outer surface of the package body. | 12-17-2015 |
20150371783 | METHOD OF MANUFACTURING A WINDING-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE WITHOUT USING A LEAD FRAME - A winding-type solid electrolytic capacitor package structure without using any lead frame includes a winding capacitor and a package body. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin extended from a first lateral side of the winding body, and a negative conductive lead pin extended from a second lateral side of the winding body. The positive conductive lead pin has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body and extended along the first lateral surface and the bottom surface of the package body. The negative conductive lead pin has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body and extended along the second lateral surface and the bottom surface of the package body. | 12-24-2015 |
Patent application number | Description | Published |
20120198133 | ELECTRONIC DEVICE WITH EXPANDABLE MEMORY CAPACITY AND AN EXPANSION METHOD THEREOF - An electronic device includes a processor, an internal memory for storing system information and installing programs, and a memory expansion interface for connecting an expansion memory. The expansion memory is partitioned into at least one region to expand the internal memory. The internal memory is partitioned into a system region and a user region; the system region is used to store system information while the user region can be controlled and used by a user. The processor further includes a detection unit and a memory management unit. The detection unit detects the connection of the expansion memory to the memory expansion interface, and the memory management unit determines whether the expansion memory has been previously configured to expand the internal memory, and if not, the memory management unit associates the expansion memory with the internal memory to expand the internal memory. | 08-02-2012 |
20120264403 | COMMUNICATION CONTROL SYSTEM AND METHOD THEREOF - A communication control system includes an electronic device and a communication apparatus paired with the electronic device. The electronic device includes an input unit, a first BLUETOOTH unit, and a dialing control module. The input unit generates commands in response to operations of a user. The dialing control module generates dial information when a dialing command is received, and controls the first BLUETOOTH unit to transmit the dial information to the communication apparatus. The communication apparatus includes a wireless communication unit, a second BLUETOOTH unit, and a dialing module. The dialing module controls the wireless communication unit to dial according to the dial information. The dialing module also controls the second BLUETOOTH unit to transmit real-time dial information and voice signals of the user to the electronic device. A related method is also provided. | 10-18-2012 |
20130007666 | ELECTRONIC DEVICE WITH TOUCH SCREEN DEVICE, METHOD OF MOVING FUNCTION ICON AND COMPUTER READABLE STORAGE MEDIA COMPRISING COMPUTER EXECUTABLE INSTRUCTIONS - An electronic device with a touch screen device selectively displaying one of a plurality of desktop screens is disclosed. Each desktop screen includes function icons and page icons associated with desktop screens. The electronic device further includes a function icon sensing module, a function icon moving module, a page icon sensing module and a page flipping module. The function icon sensing module senses touch on the function icons. The function icon moving module moves the function icon when an icon move operation has been performed. The page icon sensing module senses the touch on a page icon. The page flipping module controls the touch screen device to display a desired desktop screen associated with the selected page icon and add the selected function icon to the desired desktop screen. A method of moving function icon and one or more computer readable storage media comprising computer executable instructions are also disclosed. | 01-03-2013 |
Patent application number | Description | Published |
20130109163 | FABRICATING METHOD OF SEMICONDUCTOR ELEMENT | 05-02-2013 |
20130234292 | THIN FILM RESISTOR STRUCTURE - A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD. | 09-12-2013 |
20130240956 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device. | 09-19-2013 |
20160049506 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device. | 02-18-2016 |
Patent application number | Description | Published |
20140244776 | DEVICE, AND METHOD AND SYSTEM FOR MONITORING MULTIPLE DEVICES - A method and a system for monitoring at least one device group each having a master device and multiple slave devices are provided. The multiple slave devices are connected in sequence and are finally connected to the master device. Each device stores a multi-bits string, wherein the value of each bit of the string associates with the status of a device according to the connection sequence of the device group. Each device self-tests its own status and outputs a corresponding self-test signal. Each device updates one bit of the stored string corresponding to the device with the output self-test signal, and updates the other bits of the stored string with corresponding bits of a multi-bits string transmitted from a connected rear device. Each slave device transmits the updated stored string to a connected previous device, and the master device transmits the updated stored string to a remote server for monitoring. | 08-28-2014 |
20140310548 | ELECTRONIC DEVICE AND METHOD FOR POWER MANAGEMENT - In a method for managing power of slave electronic devices using a master electronic device, the slave electronic devices are connected in sequence and an end one of the slave electronic devices is connected to the master electronic device. Each of the slave electronic devices determines and transmits their charging priority information to the master electronic device. The master electronic device determines a charging sequence of the slave electronic devices, determines a target one of the slave electronic devices according to the charging sequence, and sends a charging signal to the connected slave electronic devices, to charge the target one of the slave electronic devices. | 10-16-2014 |
20140313101 | ELECTRONIC DEVICE AND METHOD FOR IMAGE CONTENT ASSIGNMENT - In a method for assigning image content displayed on electronic devices connected to a server, each electronic device has display screens. The server determines image content for each electronic device, organizes the determined image contents of each electronic device according to configuration information of display screens of each electronic device, packets the organized image contents of each of the electronic devices into a data packet according to the configuration information, with each data packet being associated to a destination electronic device, and sends the data packets to the electronic devices. Each electronic device can obtain image content from the data packet if the electronic device is a destination electronic device of the data packet, in addition, can assign image content for each display screen of the current electronic device to display according to the configuration information of the display screens. | 10-23-2014 |