Patent application number | Description | Published |
20100073073 | MICROPROCESSOR WITH SUBSTRATE BIAS CLAMPS - A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes. | 03-25-2010 |
20100073074 | MICROPROCESSOR WITH SELECTIVE SUBSTRATE BIASING FOR CLOCK-GATED FUNCTIONAL BLOCKS - A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail. | 03-25-2010 |
20100264903 | METHOD AND APPARATUS FOR DETERMINING PEAK PHASE ERROR BETWEEN CLOCK SIGNALS - A peak phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the pulse difference signal and provides a peak phase error value representing peak phase error between the clock signals. The delay and register logic may include a delay line with multiple delay cells and taps coupled in series in which each tap provides an output state of a delay cell. The register logic registers a state of each tap to provide delay bits in response to each trailing edge of the difference pulses. Each delay bit remains set until reset so that the longest pulse difference signal is registered to provide the peak phase error. | 10-21-2010 |
20140204691 | SOURCE SYNCHRONOUS BUS SIGNAL ALIGNMENT COMPENSATION MECHANISM - An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus. | 07-24-2014 |
20140207735 | APPARATUS AND METHOD FOR DYNAMIC ALIGNMENT OF SOURCE SYNCHRONOUS BUS SIGNALS - An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. | 07-24-2014 |
20140208147 | APPARATUS AND METHOD FOR LOCALLY OPTIMIZING SOURCE SYNCHRONOUS DATA STROBES - An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a bit lag control element and a synchronous lag receiver. The bit lag control element is configured to measure a propagation time beginning with assertion of a strobe and ending with assertion of a first one of a plurality of radially distributed strobes corresponding to the strobe, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive the first one of the plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. | 07-24-2014 |
20140208148 | AUTOMATIC SOURCE SYNCHRONOUS BUS SIGNAL ALIGNMENT COMPENSATION MECHANISM - An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus. | 07-24-2014 |
20140208149 | APPARATUS AND METHOD FOR DYNAMICALLY ALIGNED SOURCE SYNCHRONOUS RECEIVER - An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals. | 07-24-2014 |