Patent application number | Description | Published |
20100031265 | Method and System for Implementing Realtime Spinlocks - A system and method for receiving a request from a requester for access to a computing resource, instructing the requester to wait for access to the resource when the resource is unavailable and allowing the requester to perform other tasks while waiting, determining whether the requester is available when the resource subsequently becomes available, and granting access to the resource by the requester if the requester is available. | 02-04-2010 |
20100332796 | Method and System for a CPU-Local Storage Mechanism - Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local storage mechanism. Each of the plurality of processors of the system may have controlled access to the resource and each of the processors is dedicated to one of a plurality of tasks of an application. The application including the plurality of tasks may be replicated using the processor local storage mechanism, wherein each of the tasks of the replicated application includes an affinity to one of the plurality of processors. | 12-30-2010 |
20110029953 | System and Method for Scalable Handling of Debug Information - Described herein are systems and tools for scalable handling of debug information. The system includes a memory storing an application, and a processor executing a set of instructions operable to generate a plurality of subsets from the application, produce a linkable file for each of the subsets, each linkable file including debug information for the corresponding subset, create a path from the application to the linkable files based on linked information, and load one of the linkable files for a selected subset. The debugging tool includes a removing means removing debug information from an application, a generating means generating a plurality of subsets within the application, a producing means producing a linkable debug file for each of the subsets of the application, each linkable debug file including debug information for the corresponding subset, a relocating means relocating each of the subsets within the application based on linked information, and a loading means loading the linkable debug file for a selected subset in order to debug the subset. | 02-03-2011 |
20110191627 | System And Method for Handling a Failover Event - A system comprising a memory storing a set of instructions executable by a processor. The instructions being operable to monitor progress of an application executing in a first operating system (OS) instance, the progress occurring on data stored within a shared memory area, detect a failover event in the application and copy, upon the detection of the failover event, the data from the shared memory area to a fail memory area of a second instance of the OS, the fail memory area being an area of memory mapped for receiving data from another instance of the OS only if the application executing on the another instance experiences a failover event. | 08-04-2011 |
20110271076 | Optimizing Task Management - An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to one of the single-core processing mode and the multi-core processing mode as a function of the number of tasks. | 11-03-2011 |
20120198283 | System And Method for Fast Boot from Non-Volatile Memory - Described herein are systems and methods for fast boot from non-volatile (“NV”) memory. The exemplary embodiments relate to systems and methods for significant improvements in performance speed with simple implementations. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions operable to identify a page fault, determine whether the page fault occurred due to a read from a NV memory, copy a page from the NV memory to a random-access memory (“RAM”) storage, and create an identity mapping for the page in the RAM storage. A further embodiment relates to a system comprising a NV memory, a random access memory, and a processor executing a set of instructions, wherein the set of instructions being operable to identify a page fault, determine whether a page fault occurred due to a read from the NV memory, copy a page from the NV memory to the RAM storage, and create an identity mapping for the page in the RAM storage. | 08-02-2012 |
20120233367 | Interrupt Latency Measurement - A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp. | 09-13-2012 |
20140108690 | System And Method for Operating System Aware Low Latency Interrupt Handling - The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section. | 04-17-2014 |