Patent application number | Description | Published |
20100071759 | Electrochemical Device and Method of Fabricating the Same - A method of forming an electrode including an electrochemical catalyst layer is disclosed, which comprises forming a graphitized porous conductive fabric layer, optionally conditioning the graphitized porous conductive fabric layer, and dipping the graphitized porous conductive fabric layer into a solution containing polymer-capped noble metal nanoclusters dispersed therein. The polymer-capped noble metal nanoclusters as an electrochemical catalyst layer are adsorbed onto the graphitized porous conductive fabric layer. An electrochemical device with the electrode made thereby is also contemplated. | 03-25-2010 |
20100071839 | Electrochemical Device and Method of Fabricating the Same - A method of forming an electrode including an electrochemical catalyst layer is disclosed, which comprises forming a graphitized porous conductive fabric layer, optionally conditioning the graphitized porous conductive fabric layer, and dipping the graphitized porous conductive fabric layer into a solution containing a plurality of polymer-capped noble metal nanoclusters dispersed therein. The polymer-capped noble metal nanoclusters as an electrochemical catalyst layer are adsorbed onto the graphitized porous conductive fabric layer. An electrochemical device with the electrode made thereby is also contemplated. | 03-25-2010 |
20100101623 | PACKAGING STRUCTURE - A packaging structure with a box for containing at least a portable electronic device is provided. The box has plates, which are connected to one another and surrounded to form an opening for the portable electronic device passing through, and a lid selectively covering or exposing the opening. First solar cells each fastened on an inner surface of each plate in the box. At least a cable electrically connects the first solar cells and is operated for electrically connecting the portable electronic device. | 04-29-2010 |
20100101644 | ELECTROLYTE COMPOSITION AND DYE-SENSITIZED SOLAR CELL (DSSC) COMPRISING THE SAME - Disclosed herein is a dye-sensitized solar cell. The dye-sensitized solar cell includes a semiconductor electrode with a dye adsorbed thereon; a counter electrode; and an electrolyte composition provided between the semiconductor electrode and the counter electrode; wherein the electrolyte composition comprises an oxidation-reduction mediator and a eutectic ionic liquid including a choline halide or derivatives thereof mixed with alcohols or urea. | 04-29-2010 |
20100108240 | Method of Forming an Electrode Including an Electrochemical Catalyst Layer - A method of forming an electrode having an electrochemical catalyst layer is disclosed. The method includes etching a surface of a substrate, followed by immersing the substrate in a solution containing surfactants to form a conditioner layer on the surface of the substrate, and immersing the substrate in a solution containing polymer-capped noble metal nanoclusters dispersed therein to form a polymer-protected electrochemical catalyst layer on the conditioner layer. | 05-06-2010 |
Patent application number | Description | Published |
20140092689 | METHOD FOR PROGRAMMING NON-VOLATILE MEMORY CELL, NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY APPARATUS - A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure. | 04-03-2014 |
20140175531 | NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure. | 06-26-2014 |
20140197472 | NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously. | 07-17-2014 |
20140198574 | NONVOLATILE MEMORY AND MANIPULATING METHOD THEREOF - A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line. | 07-17-2014 |
20150056775 | NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure. | 02-26-2015 |