Patent application number | Description | Published |
20120311042 | DISTRIBUTION METHOD AND DISTRIBUTION SYSTEM - A distribution method is performed in a distribution system including a distribution source device for distributing data and a plurality of distribution destination devices. The distribution method includes searching, by the distribution source device, for the distribution destination devices by expanding a search range by plural stages; executing in each stage, by the distribution source device, an allowance process of allowing distribution of the data to the distribution destination devices found by searching in each stage; detecting in a predetermined range, by the distribution destination device, another distribution destination device that has acquired the data before the distribution destination device performing the detecting; and executing, by the distribution destination device, an acquiring process of acquiring the data from the other distribution destination device, according to allowance of distribution. | 12-06-2012 |
20140380298 | WIRELESS COMMUNICATION TERMINAL, SOFTWARE UPDATE SYSTEM, AND SOFTWARE UPDATE METHOD - A software update system includes an administration server, a wireless communication terminal, and a wireless-communication key station. The wireless communication terminal is configured to be connected to the administration server through a communication network. The a wireless-communication key station is configured to be positioned between the administration server and the wireless communication terminal, and to perform processing of distributing software of an update object transmitted from the administration server to the wireless communication terminal. | 12-25-2014 |
Patent application number | Description | Published |
20080294847 | Cache control device and computer-readable recording medium storing cache control program - A cache control device controlling a cache memory having ways based on an access request includes an error number count memory unit that counts the total number of errors occurred in response to the access request regardless of in which way they occur, a degeneration information memory unit that stores cache line degeneration information indicating degeneration of a specific cache line, a degeneration information writing unit that writes, when the counted number of errors reaches a predetermined upper limit number, the cache line degeneration information into the degeneration information memory unit for a cache line, error in which causes the number to reach the predetermined upper limit number, and a replace control unit that performs, in response to a replace request to the cache line corresponding to the cache line degeneration information stored in the degeneration information memory unit, a replace control to exclude the cache line from replace candidates. | 11-27-2008 |
20100070708 | ARITHMETIC PROCESSING APPARATUS AND METHOD - An apparatus includes a TLB storing a part of a TSB area included in a memory accessed by the apparatus. The TSB area stores an address translation pair for translating a virtual address into a physical address. The apparatus further includes a cache memory that temporarily stores the pair; a storing unit that stores a starting physical address of the pair stored in the memory unit; a calculating unit that calculates, based on the starting physical address and a virtual address to be converted, a TSB pointer used in obtaining from the TSB area a corresponding address translation pair corresponding to the virtual address to be converted; and an obtaining unit that obtains the corresponding pair from the TSB area using the TSB pointer calculated and stores the corresponding pair in the cache memory, if the corresponding pair is not retrieved from the TLB or the cache memory. | 03-18-2010 |
20100332790 | PROCESSOR AND ADDRESS TRANSLATING METHOD - An address translation buffer of a processor including a memory unit that has a first area with first entries storing first address translation pairs of a virtual address and a physical address corresponding to the virtual address, each of the first address translation pairs is subjected to a index tag which is a part of the virtual address, and a second area with second entries storing second address translation pairs, each of the second address translation pairs is subjected to a whole part of the virtual address, and a search unit that searches the first area for an address translation pair by using a index tag included in a virtual address to be translated, and searches the second area for the address translation pair by using a whole part of the virtual address when the address translation pair is not found in the first area. | 12-30-2010 |
20130080733 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor connected to a storage device including a buffer area where an address translation pair is stored includes: an LRU register that holds a number of a plurality of real address registers, the real address register being the oldest in a use history; a reading unit that reads the number of the real address register held in the LRU register when a real address included in an access request to the storage device does not fall within a range of a real address space from a lower limit real address held in a lower limit real address register to an upper limit real address held in an upper limit real address register; and a setting unit that invalidates the real address register corresponding to the read number and sets a real address space corresponding to the real address included in the access request to the invalided real address register. | 03-28-2013 |
20130151809 | ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: an processing unit configured to execute threads and output a memory request including a virtual address; a buffer configured to register some of address translation pairs stored in a memory, each of the address translation pairs including a virtual address and a physical address; a controller configured to issue requests for obtaining the corresponding address translation pairs to the memory for individual threads when an address translation pair corresponding to the virtual address included in the memory request output from the processing unit is not registered in the buffer; table fetch units configured to obtain the corresponding address translation pairs from the memory for individual threads when the requests for obtaining the corresponding address translation pairs are issued; and a registration controller configured to register one of the obtained address translation pairs in the buffer. | 06-13-2013 |
20150089180 | ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, CONTROL METHOD FOR INFORMATION PROCESSING DEVICE, AND CONTROL PROGRAM FOR INFORMATION PROCESSING DEVICE - An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area. | 03-26-2015 |
Patent application number | Description | Published |
20080203558 | Method of semiconductor device protection, package of semiconductor device - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 08-28-2008 |
20080227226 | Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device - A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line. | 09-18-2008 |
20080251788 | Wafer-level package having test terminal - A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member. | 10-16-2008 |
20080299790 | METHOD OF ATTACHING ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT ATTACHING TOOL - An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket. | 12-04-2008 |
20110049699 | METHOD OF SEMICONDUCTOR DEVICE PROTECTION, PACKAGE OF SEMICONDUCTOR DEVICE - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 03-03-2011 |
20120005875 | METHOD OF SEMICONDUCTOR DEVICE PROTECTION - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 01-12-2012 |
20120005883 | METHOD OF ATTACHING ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT ATTACHING TOOL - An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket. | 01-12-2012 |
20130171748 | METHOD OF TESTING A SEMICONDUCTOR DEVICE AND SUCTIONING A SEMICONDUCTOR DEVICE IN THE WAFER STATE - A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts. | 07-04-2013 |
Patent application number | Description | Published |
20080218889 | INFORMATION TRANSFER MASTER FOR MAGNETIC TRANSFER AND MAGNETIC TRANSFER METHOD - An information transfer master has servo information pattern to be magnetically transferred to a magnetic recording medium having a lubrication layer thereon; and a contact surface to contact the magnetic recording medium has surface free energy that is 45 mN/m or less when the servo information pattern is magnetically transferred. | 09-11-2008 |
20080312891 | DESIGN METHOD, DESIGN SUPPORT APPARATUS, AND COMPUTER PRODUCT FOR FEEDBACK CONTROL SYSTEM - A control system is designed in which a controlled plant is controlled based on output feedback from the controlled plant. An all-pass filter is modeled that is formed of a synthesis of a notch filter compensating for a resonance mode in the control system and the resonance mode. A design controlled plant including the all-pass filter is determined. A controller controls the design controlled plant and includes a weighting function, and, after the weighting function is derived, gain of the weighting function is adjusted using desired gain crossover frequency and phase margin. A phase variable included in a phase-lead weight is determined, and thus the weighting function is determined. H∞ loop shaping is applied to the weighting function and the design controlled plant to obtain an H∞ loop controller. | 12-18-2008 |
20090244768 | MAGNETIC HEAD POSITIONING CONTROL METHOD AND MAGNETIC HEAD POSITIONING CONTROL APPARATUS - N groups of servo patterns, each corresponding to the predetermined number of servo sectors, are recorded in a magnetic disk. The magnetic head positioning control apparatus of the present invention produces an RRO current correction table corresponding to each group of servo patters and selects the group of servo patterns that is the best in transferred quality of the sevro pattern as SPopt. For servo sectors (target servo sectors) corresponding to other groups of servo patterns and existing between two adjacent servo sectors corresponding to the SPopt, the magnetic head positioning control apparatus calculates an RRO current correction amount corresponding to the target servo sector by a linear interpolation calculation using the RRO current correction amount corresponding to each of the adjacent servo sectors in the RRO current correction table corresponding to the SPopt to perform the magnetic head positioning control based on the calculated RRO current correction amount. | 10-01-2009 |
20100039725 | ECCENTRICITY CORRECTION METHOD, SIGNAL PROCESSING CIRCUIT, MAGNETIC STORAGE APPARATUS AND PERPENDICULAR MAGNETIC RECORDING MEDIUM - A magnetic storage apparatus has a reproducing head to reproduce information from a perpendicular magnetic recording medium that is recorded with servo information, eccentricity correction data and read/write data. The apparatus further has a filter part to filter a reproduced output of the reproducing head by filtering the servo information which has a differentiated waveform by a non-differentiating characteristic and by filtering the eccentricity correction data and the read/write data which have rectangular waveforms by a differentiating characteristic, a demodulating part to demodulate the servo information, the eccentricity correction data and the read/write data that are filtered by the filter part, and a servo system to carry out a control process including an eccentricity control based on the servo information and the eccentricity correction data that are demodulated. | 02-18-2010 |
20110077836 | ENGINE CONTROL APPARATUS AND METHOD - By using a model of a transient response characteristic of an engine and a model of a steady-state characteristic of the engine, a disturbance estimate value is calculated. By using this disturbance estimate value, initial command values of a nozzle opening degree of a Variable Nozzle Turbo and a valve opening degree of a Exhaust Gas Recirculator are adjusted in order to reduce model errors and appropriately handle the disturbance. Hence, it is possible to cause Mass Air Flow and Manifold Air Pressure to follow their target values stably. | 03-31-2011 |
20120221301 | MATRIX GENERATION TECHNIQUE AND PLANT CONTROL TECHNIQUE - In this disclosure, equations to be solved in the model predictive control are transformed by using an off-line algebraic simplification method into a matrix operational expression representing a product of a coefficient matrix and a vector regarding solution inputs within a control horizon is equal to a function vector regarding target values of output states and the output states. The size of the coefficient matrix is reduced compared with the conventional matrix. Then, the matrix operational expression is solved in an online plant control apparatus with present output states and present target values of the output stats of a plant to be controlled, by the direct method, to output the solution to the plant. | 08-30-2012 |
20150025865 | MATRIX GENERATION TECHNIQUE AND PLANT CONTROL TECHNIQUE - In this disclosure, equations to be solved in the model predictive control are transformed by using an off-line algebraic simplification method into a matrix operational expression representing a product of a coefficient matrix and a vector regarding solution inputs within a control horizon is equal to a function vector regarding target values of output states and the output states. The size of the coefficient matrix is reduced compared with the conventional matrix. Then, the matrix operational expression is solved in an online plant control apparatus with present output states and present target values of the output stats of a plant to be controlled, by the direct method, to output the solution to the plant. | 01-22-2015 |